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1/*2 * Copyright 2014 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#ifndef __AMDGPU_RLC_H__25#define __AMDGPU_RLC_H__26 27#include "clearstate_defs.h"28 29#define AMDGPU_MAX_RLC_INSTANCES 830 31/* firmware ID used in rlc toc */32typedef enum _FIRMWARE_ID_ {33 FIRMWARE_ID_INVALID = 0,34 FIRMWARE_ID_RLC_G_UCODE = 1,35 FIRMWARE_ID_RLC_TOC = 2,36 FIRMWARE_ID_RLCG_SCRATCH = 3,37 FIRMWARE_ID_RLC_SRM_ARAM = 4,38 FIRMWARE_ID_RLC_SRM_INDEX_ADDR = 5,39 FIRMWARE_ID_RLC_SRM_INDEX_DATA = 6,40 FIRMWARE_ID_RLC_P_UCODE = 7,41 FIRMWARE_ID_RLC_V_UCODE = 8,42 FIRMWARE_ID_RLX6_UCODE = 9,43 FIRMWARE_ID_RLX6_DRAM_BOOT = 10,44 FIRMWARE_ID_GLOBAL_TAP_DELAYS = 11,45 FIRMWARE_ID_SE0_TAP_DELAYS = 12,46 FIRMWARE_ID_SE1_TAP_DELAYS = 13,47 FIRMWARE_ID_GLOBAL_SE0_SE1_SKEW_DELAYS = 14,48 FIRMWARE_ID_SDMA0_UCODE = 15,49 FIRMWARE_ID_SDMA0_JT = 16,50 FIRMWARE_ID_SDMA1_UCODE = 17,51 FIRMWARE_ID_SDMA1_JT = 18,52 FIRMWARE_ID_CP_CE = 19,53 FIRMWARE_ID_CP_PFP = 20,54 FIRMWARE_ID_CP_ME = 21,55 FIRMWARE_ID_CP_MEC = 22,56 FIRMWARE_ID_CP_MES = 23,57 FIRMWARE_ID_MES_STACK = 24,58 FIRMWARE_ID_RLC_SRM_DRAM_SR = 25,59 FIRMWARE_ID_RLCG_SCRATCH_SR = 26,60 FIRMWARE_ID_RLCP_SCRATCH_SR = 27,61 FIRMWARE_ID_RLCV_SCRATCH_SR = 28,62 FIRMWARE_ID_RLX6_DRAM_SR = 29,63 FIRMWARE_ID_SDMA0_PG_CONTEXT = 30,64 FIRMWARE_ID_SDMA1_PG_CONTEXT = 31,65 FIRMWARE_ID_GLOBAL_MUX_SELECT_RAM = 32,66 FIRMWARE_ID_SE0_MUX_SELECT_RAM = 33,67 FIRMWARE_ID_SE1_MUX_SELECT_RAM = 34,68 FIRMWARE_ID_ACCUM_CTRL_RAM = 35,69 FIRMWARE_ID_RLCP_CAM = 36,70 FIRMWARE_ID_RLC_SPP_CAM_EXT = 37,71 FIRMWARE_ID_MAX = 38,72} FIRMWARE_ID;73 74typedef enum _SOC21_FIRMWARE_ID_ {75 SOC21_FIRMWARE_ID_INVALID = 0,76 SOC21_FIRMWARE_ID_RLC_G_UCODE = 1,77 SOC21_FIRMWARE_ID_RLC_TOC = 2,78 SOC21_FIRMWARE_ID_RLCG_SCRATCH = 3,79 SOC21_FIRMWARE_ID_RLC_SRM_ARAM = 4,80 SOC21_FIRMWARE_ID_RLC_P_UCODE = 5,81 SOC21_FIRMWARE_ID_RLC_V_UCODE = 6,82 SOC21_FIRMWARE_ID_RLX6_UCODE = 7,83 SOC21_FIRMWARE_ID_RLX6_UCODE_CORE1 = 8,84 SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT = 9,85 SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT_CORE1 = 10,86 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0 = 11,87 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1 = 12,88 SOC21_FIRMWARE_ID_CP_PFP = 13,89 SOC21_FIRMWARE_ID_CP_ME = 14,90 SOC21_FIRMWARE_ID_CP_MEC = 15,91 SOC21_FIRMWARE_ID_RS64_MES_P0 = 16,92 SOC21_FIRMWARE_ID_RS64_MES_P1 = 17,93 SOC21_FIRMWARE_ID_RS64_PFP = 18,94 SOC21_FIRMWARE_ID_RS64_ME = 19,95 SOC21_FIRMWARE_ID_RS64_MEC = 20,96 SOC21_FIRMWARE_ID_RS64_MES_P0_STACK = 21,97 SOC21_FIRMWARE_ID_RS64_MES_P1_STACK = 22,98 SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK = 23,99 SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK = 24,100 SOC21_FIRMWARE_ID_RS64_ME_P0_STACK = 25,101 SOC21_FIRMWARE_ID_RS64_ME_P1_STACK = 26,102 SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK = 27,103 SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK = 28,104 SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK = 29,105 SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK = 30,106 SOC21_FIRMWARE_ID_RLC_SRM_DRAM_SR = 31,107 SOC21_FIRMWARE_ID_RLCG_SCRATCH_SR = 32,108 SOC21_FIRMWARE_ID_RLCP_SCRATCH_SR = 33,109 SOC21_FIRMWARE_ID_RLCV_SCRATCH_SR = 34,110 SOC21_FIRMWARE_ID_RLX6_DRAM_SR = 35,111 SOC21_FIRMWARE_ID_RLX6_DRAM_SR_CORE1 = 36,112 SOC21_FIRMWARE_ID_MAX = 37113} SOC21_FIRMWARE_ID;114 115typedef enum _SOC24_FIRMWARE_ID_ {116 SOC24_FIRMWARE_ID_INVALID = 0,117 SOC24_FIRMWARE_ID_RLC_G_UCODE = 1,118 SOC24_FIRMWARE_ID_RLC_TOC = 2,119 SOC24_FIRMWARE_ID_RLCG_SCRATCH = 3,120 SOC24_FIRMWARE_ID_RLC_SRM_ARAM = 4,121 SOC24_FIRMWARE_ID_RLC_P_UCODE = 5,122 SOC24_FIRMWARE_ID_RLC_V_UCODE = 6,123 SOC24_FIRMWARE_ID_RLX6_UCODE = 7,124 SOC24_FIRMWARE_ID_RLX6_UCODE_CORE1 = 8,125 SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT = 9,126 SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT_CORE1 = 10,127 SOC24_FIRMWARE_ID_SDMA_UCODE_TH0 = 11,128 SOC24_FIRMWARE_ID_SDMA_UCODE_TH1 = 12,129 SOC24_FIRMWARE_ID_CP_PFP = 13,130 SOC24_FIRMWARE_ID_CP_ME = 14,131 SOC24_FIRMWARE_ID_CP_MEC = 15,132 SOC24_FIRMWARE_ID_RS64_MES_P0 = 16,133 SOC24_FIRMWARE_ID_RS64_MES_P1 = 17,134 SOC24_FIRMWARE_ID_RS64_PFP = 18,135 SOC24_FIRMWARE_ID_RS64_ME = 19,136 SOC24_FIRMWARE_ID_RS64_MEC = 20,137 SOC24_FIRMWARE_ID_RS64_MES_P0_STACK = 21,138 SOC24_FIRMWARE_ID_RS64_MES_P1_STACK = 22,139 SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK = 23,140 SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK = 24,141 SOC24_FIRMWARE_ID_RS64_ME_P0_STACK = 25,142 SOC24_FIRMWARE_ID_RS64_ME_P1_STACK = 26,143 SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK = 27,144 SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK = 28,145 SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK = 29,146 SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK = 30,147 SOC24_FIRMWARE_ID_RLC_SRM_DRAM_SR = 31,148 SOC24_FIRMWARE_ID_RLCG_SCRATCH_SR = 32,149 SOC24_FIRMWARE_ID_RLCP_SCRATCH_SR = 33,150 SOC24_FIRMWARE_ID_RLCV_SCRATCH_SR = 34,151 SOC24_FIRMWARE_ID_RLX6_DRAM_SR = 35,152 SOC24_FIRMWARE_ID_RLX6_DRAM_SR_CORE1 = 36,153 SOC24_FIRMWARE_ID_RLCDEBUGLOG = 37,154 SOC24_FIRMWARE_ID_SRIOV_DEBUG = 38,155 SOC24_FIRMWARE_ID_SRIOV_CSA_RLC = 39,156 SOC24_FIRMWARE_ID_SRIOV_CSA_SDMA = 40,157 SOC24_FIRMWARE_ID_SRIOV_CSA_CP = 41,158 SOC24_FIRMWARE_ID_UMF_ZONE_PAD = 42,159 SOC24_FIRMWARE_ID_MAX = 43160} SOC24_FIRMWARE_ID;161 162typedef struct _RLC_TABLE_OF_CONTENT {163 union {164 unsigned int DW0;165 struct {166 unsigned int offset : 25;167 unsigned int id : 7;168 };169 };170 171 union {172 unsigned int DW1;173 struct {174 unsigned int load_at_boot : 1;175 unsigned int load_at_vddgfx : 1;176 unsigned int load_at_reset : 1;177 unsigned int memory_destination : 2;178 unsigned int vfflr_image_code : 4;179 unsigned int load_mode_direct : 1;180 unsigned int save_for_vddgfx : 1;181 unsigned int save_for_vfflr : 1;182 unsigned int reserved : 1;183 unsigned int signed_source : 1;184 unsigned int size : 18;185 };186 };187 188 union {189 unsigned int DW2;190 struct {191 unsigned int indirect_addr_reg : 16;192 unsigned int index : 16;193 };194 };195 196 union {197 unsigned int DW3;198 struct {199 unsigned int indirect_data_reg : 16;200 unsigned int indirect_start_offset : 16;201 };202 };203} RLC_TABLE_OF_CONTENT;204 205typedef struct _RLC_TABLE_OF_CONTENT_V2 {206 union {207 unsigned int DW0;208 struct {209 uint32_t offset : 25;210 uint32_t id : 7;211 };212 };213 214 union {215 unsigned int DW1;216 struct {217 uint32_t reserved0 : 1;218 uint32_t reserved1 : 1;219 uint32_t reserved2 : 1;220 uint32_t memory_destination : 2;221 uint32_t vfflr_image_code : 4;222 uint32_t reserved9 : 1;223 uint32_t reserved10 : 1;224 uint32_t reserved11 : 1;225 uint32_t size_x16 : 1;226 uint32_t reserved13 : 1;227 uint32_t size : 18;228 };229 };230} RLC_TABLE_OF_CONTENT_V2;231 232#define RLC_TOC_MAX_SIZE 64233 234struct amdgpu_rlc_funcs {235 bool (*is_rlc_enabled)(struct amdgpu_device *adev);236 void (*set_safe_mode)(struct amdgpu_device *adev, int xcc_id);237 void (*unset_safe_mode)(struct amdgpu_device *adev, int xcc_id);238 int (*init)(struct amdgpu_device *adev);239 u32 (*get_csb_size)(struct amdgpu_device *adev);240 void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer);241 int (*get_cp_table_num)(struct amdgpu_device *adev);242 int (*resume)(struct amdgpu_device *adev);243 void (*stop)(struct amdgpu_device *adev);244 void (*reset)(struct amdgpu_device *adev);245 void (*start)(struct amdgpu_device *adev);246 void (*update_spm_vmid)(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid);247 bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);248};249 250struct amdgpu_rlcg_reg_access_ctrl {251 uint32_t scratch_reg0;252 uint32_t scratch_reg1;253 uint32_t scratch_reg2;254 uint32_t scratch_reg3;255 uint32_t grbm_cntl;256 uint32_t grbm_idx;257 uint32_t spare_int;258};259 260struct amdgpu_rlc {261 /* for power gating */262 struct amdgpu_bo *save_restore_obj;263 uint64_t save_restore_gpu_addr;264 volatile uint32_t *sr_ptr;265 const u32 *reg_list;266 u32 reg_list_size;267 /* for clear state */268 struct amdgpu_bo *clear_state_obj;269 uint64_t clear_state_gpu_addr;270 volatile uint32_t *cs_ptr;271 const struct cs_section_def *cs_data;272 u32 clear_state_size;273 /* for cp tables */274 struct amdgpu_bo *cp_table_obj;275 uint64_t cp_table_gpu_addr;276 volatile uint32_t *cp_table_ptr;277 u32 cp_table_size;278 279 /* safe mode for updating CG/PG state */280 bool in_safe_mode[AMDGPU_MAX_RLC_INSTANCES];281 const struct amdgpu_rlc_funcs *funcs;282 283 /* for firmware data */284 u32 save_and_restore_offset;285 u32 clear_state_descriptor_offset;286 u32 avail_scratch_ram_locations;287 u32 reg_restore_list_size;288 u32 reg_list_format_start;289 u32 reg_list_format_separate_start;290 u32 starting_offsets_start;291 u32 reg_list_format_size_bytes;292 u32 reg_list_size_bytes;293 u32 reg_list_format_direct_reg_list_length;294 u32 save_restore_list_cntl_size_bytes;295 u32 save_restore_list_gpm_size_bytes;296 u32 save_restore_list_srm_size_bytes;297 u32 rlc_iram_ucode_size_bytes;298 u32 rlc_dram_ucode_size_bytes;299 u32 rlcp_ucode_size_bytes;300 u32 rlcv_ucode_size_bytes;301 u32 global_tap_delays_ucode_size_bytes;302 u32 se0_tap_delays_ucode_size_bytes;303 u32 se1_tap_delays_ucode_size_bytes;304 u32 se2_tap_delays_ucode_size_bytes;305 u32 se3_tap_delays_ucode_size_bytes;306 307 u32 *register_list_format;308 u32 *register_restore;309 u8 *save_restore_list_cntl;310 u8 *save_restore_list_gpm;311 u8 *save_restore_list_srm;312 u8 *rlc_iram_ucode;313 u8 *rlc_dram_ucode;314 u8 *rlcp_ucode;315 u8 *rlcv_ucode;316 u8 *global_tap_delays_ucode;317 u8 *se0_tap_delays_ucode;318 u8 *se1_tap_delays_ucode;319 u8 *se2_tap_delays_ucode;320 u8 *se3_tap_delays_ucode;321 322 bool is_rlc_v2_1;323 324 /* for rlc autoload */325 struct amdgpu_bo *rlc_autoload_bo;326 u64 rlc_autoload_gpu_addr;327 void *rlc_autoload_ptr;328 329 /* rlc toc buffer */330 struct amdgpu_bo *rlc_toc_bo;331 uint64_t rlc_toc_gpu_addr;332 void *rlc_toc_buf;333 334 bool rlcg_reg_access_supported;335 /* registers for rlcg indirect reg access */336 struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl[AMDGPU_MAX_RLC_INSTANCES];337};338 339void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id);340void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id);341int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);342int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev);343int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);344void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev);345void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev);346int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev,347 uint16_t version_major,348 uint16_t version_minor);349#endif350