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1/*2 * Copyright 2011 Advanced Micro Devices, Inc.3 * All Rights Reserved.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the7 * "Software"), to deal in the Software without restriction, including8 * without limitation the rights to use, copy, modify, merge, publish,9 * distribute, sub license, and/or sell copies of the Software, and to10 * permit persons to whom the Software is furnished to do so, subject to11 * the following conditions:12 *13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE19 * USE OR OTHER DEALINGS IN THE SOFTWARE.20 *21 * The above copyright notice and this permission notice (including the22 * next paragraph) shall be included in all copies or substantial portions23 * of the Software.24 *25 */26/*27 * Authors:28 * Christian König <deathsimple@vodafone.de>29 */30 31#include <linux/firmware.h>32#include <linux/module.h>33 34#include <drm/drm.h>35#include <drm/drm_drv.h>36 37#include "amdgpu.h"38#include "amdgpu_pm.h"39#include "amdgpu_uvd.h"40#include "amdgpu_cs.h"41#include "cikd.h"42#include "uvd/uvd_4_2_d.h"43 44#include "amdgpu_ras.h"45 46/* 1 second timeout */47#define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)48 49/* Firmware versions for VI */50#define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8))51#define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8))52#define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8))53#define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8))54 55/* Polaris10/11 firmware version */56#define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))57 58/* Firmware Names */59#ifdef CONFIG_DRM_AMDGPU_SI60#define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin"61#define FIRMWARE_VERDE "amdgpu/verde_uvd.bin"62#define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin"63#define FIRMWARE_OLAND "amdgpu/oland_uvd.bin"64#endif65#ifdef CONFIG_DRM_AMDGPU_CIK66#define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin"67#define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin"68#define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin"69#define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin"70#define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin"71#endif72#define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"73#define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"74#define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"75#define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"76#define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin"77#define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"78#define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin"79#define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin"80 81#define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin"82#define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin"83#define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin"84 85/* These are common relative offsets for all asics, from uvd_7_0_offset.h, */86#define UVD_GPCOM_VCPU_CMD 0x03c387#define UVD_GPCOM_VCPU_DATA0 0x03c488#define UVD_GPCOM_VCPU_DATA1 0x03c589#define UVD_NO_OP 0x03ff90#define UVD_BASE_SI 0x380091 92/*93 * amdgpu_uvd_cs_ctx - Command submission parser context94 *95 * Used for emulating virtual memory support on UVD 4.2.96 */97struct amdgpu_uvd_cs_ctx {98 struct amdgpu_cs_parser *parser;99 unsigned int reg, count;100 unsigned int data0, data1;101 unsigned int idx;102 struct amdgpu_ib *ib;103 104 /* does the IB has a msg command */105 bool has_msg_cmd;106 107 /* minimum buffer sizes */108 unsigned int *buf_sizes;109};110 111#ifdef CONFIG_DRM_AMDGPU_SI112MODULE_FIRMWARE(FIRMWARE_TAHITI);113MODULE_FIRMWARE(FIRMWARE_VERDE);114MODULE_FIRMWARE(FIRMWARE_PITCAIRN);115MODULE_FIRMWARE(FIRMWARE_OLAND);116#endif117#ifdef CONFIG_DRM_AMDGPU_CIK118MODULE_FIRMWARE(FIRMWARE_BONAIRE);119MODULE_FIRMWARE(FIRMWARE_KABINI);120MODULE_FIRMWARE(FIRMWARE_KAVERI);121MODULE_FIRMWARE(FIRMWARE_HAWAII);122MODULE_FIRMWARE(FIRMWARE_MULLINS);123#endif124MODULE_FIRMWARE(FIRMWARE_TONGA);125MODULE_FIRMWARE(FIRMWARE_CARRIZO);126MODULE_FIRMWARE(FIRMWARE_FIJI);127MODULE_FIRMWARE(FIRMWARE_STONEY);128MODULE_FIRMWARE(FIRMWARE_POLARIS10);129MODULE_FIRMWARE(FIRMWARE_POLARIS11);130MODULE_FIRMWARE(FIRMWARE_POLARIS12);131MODULE_FIRMWARE(FIRMWARE_VEGAM);132 133MODULE_FIRMWARE(FIRMWARE_VEGA10);134MODULE_FIRMWARE(FIRMWARE_VEGA12);135MODULE_FIRMWARE(FIRMWARE_VEGA20);136 137static void amdgpu_uvd_idle_work_handler(struct work_struct *work);138static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo);139 140static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev,141 uint32_t size,142 struct amdgpu_bo **bo_ptr)143{144 struct ttm_operation_ctx ctx = { true, false };145 struct amdgpu_bo *bo = NULL;146 void *addr;147 int r;148 149 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,150 AMDGPU_GEM_DOMAIN_GTT,151 &bo, NULL, &addr);152 if (r)153 return r;154 155 if (adev->uvd.address_64_bit)156 goto succ;157 158 amdgpu_bo_kunmap(bo);159 amdgpu_bo_unpin(bo);160 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);161 amdgpu_uvd_force_into_uvd_segment(bo);162 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);163 if (r)164 goto err;165 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM);166 if (r)167 goto err_pin;168 r = amdgpu_bo_kmap(bo, &addr);169 if (r)170 goto err_kmap;171succ:172 amdgpu_bo_unreserve(bo);173 *bo_ptr = bo;174 return 0;175err_kmap:176 amdgpu_bo_unpin(bo);177err_pin:178err:179 amdgpu_bo_unreserve(bo);180 amdgpu_bo_unref(&bo);181 return r;182}183 184int amdgpu_uvd_sw_init(struct amdgpu_device *adev)185{186 unsigned long bo_size;187 const char *fw_name;188 const struct common_firmware_header *hdr;189 unsigned int family_id;190 int i, j, r;191 192 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);193 194 switch (adev->asic_type) {195#ifdef CONFIG_DRM_AMDGPU_SI196 case CHIP_TAHITI:197 fw_name = FIRMWARE_TAHITI;198 break;199 case CHIP_VERDE:200 fw_name = FIRMWARE_VERDE;201 break;202 case CHIP_PITCAIRN:203 fw_name = FIRMWARE_PITCAIRN;204 break;205 case CHIP_OLAND:206 fw_name = FIRMWARE_OLAND;207 break;208#endif209#ifdef CONFIG_DRM_AMDGPU_CIK210 case CHIP_BONAIRE:211 fw_name = FIRMWARE_BONAIRE;212 break;213 case CHIP_KABINI:214 fw_name = FIRMWARE_KABINI;215 break;216 case CHIP_KAVERI:217 fw_name = FIRMWARE_KAVERI;218 break;219 case CHIP_HAWAII:220 fw_name = FIRMWARE_HAWAII;221 break;222 case CHIP_MULLINS:223 fw_name = FIRMWARE_MULLINS;224 break;225#endif226 case CHIP_TONGA:227 fw_name = FIRMWARE_TONGA;228 break;229 case CHIP_FIJI:230 fw_name = FIRMWARE_FIJI;231 break;232 case CHIP_CARRIZO:233 fw_name = FIRMWARE_CARRIZO;234 break;235 case CHIP_STONEY:236 fw_name = FIRMWARE_STONEY;237 break;238 case CHIP_POLARIS10:239 fw_name = FIRMWARE_POLARIS10;240 break;241 case CHIP_POLARIS11:242 fw_name = FIRMWARE_POLARIS11;243 break;244 case CHIP_POLARIS12:245 fw_name = FIRMWARE_POLARIS12;246 break;247 case CHIP_VEGA10:248 fw_name = FIRMWARE_VEGA10;249 break;250 case CHIP_VEGA12:251 fw_name = FIRMWARE_VEGA12;252 break;253 case CHIP_VEGAM:254 fw_name = FIRMWARE_VEGAM;255 break;256 case CHIP_VEGA20:257 fw_name = FIRMWARE_VEGA20;258 break;259 default:260 return -EINVAL;261 }262 263 r = amdgpu_ucode_request(adev, &adev->uvd.fw, "%s", fw_name);264 if (r) {265 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",266 fw_name);267 amdgpu_ucode_release(&adev->uvd.fw);268 return r;269 }270 271 /* Set the default UVD handles that the firmware can handle */272 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;273 274 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;275 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;276 277 if (adev->asic_type < CHIP_VEGA20) {278 unsigned int version_major, version_minor;279 280 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;281 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;282 DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n",283 version_major, version_minor, family_id);284 285 /*286 * Limit the number of UVD handles depending on microcode major287 * and minor versions. The firmware version which has 40 UVD288 * instances support is 1.80. So all subsequent versions should289 * also have the same support.290 */291 if ((version_major > 0x01) ||292 ((version_major == 0x01) && (version_minor >= 0x50)))293 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;294 295 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |296 (family_id << 8));297 298 if ((adev->asic_type == CHIP_POLARIS10 ||299 adev->asic_type == CHIP_POLARIS11) &&300 (adev->uvd.fw_version < FW_1_66_16))301 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n",302 version_major, version_minor);303 } else {304 unsigned int enc_major, enc_minor, dec_minor;305 306 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;307 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;308 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;309 DRM_INFO("Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n",310 enc_major, enc_minor, dec_minor, family_id);311 312 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;313 314 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);315 }316 317 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE318 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;319 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)320 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);321 322 for (j = 0; j < adev->uvd.num_uvd_inst; j++) {323 if (adev->uvd.harvest_config & (1 << j))324 continue;325 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,326 AMDGPU_GEM_DOMAIN_VRAM |327 AMDGPU_GEM_DOMAIN_GTT,328 &adev->uvd.inst[j].vcpu_bo,329 &adev->uvd.inst[j].gpu_addr,330 &adev->uvd.inst[j].cpu_addr);331 if (r) {332 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);333 return r;334 }335 }336 337 for (i = 0; i < adev->uvd.max_handles; ++i) {338 atomic_set(&adev->uvd.handles[i], 0);339 adev->uvd.filp[i] = NULL;340 }341 342 /* from uvd v5.0 HW addressing capacity increased to 64 bits */343 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))344 adev->uvd.address_64_bit = true;345 346 r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo);347 if (r)348 return r;349 350 switch (adev->asic_type) {351 case CHIP_TONGA:352 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;353 break;354 case CHIP_CARRIZO:355 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;356 break;357 case CHIP_FIJI:358 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;359 break;360 case CHIP_STONEY:361 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;362 break;363 default:364 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;365 }366 367 return 0;368}369 370int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)371{372 void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo);373 int i, j;374 375 drm_sched_entity_destroy(&adev->uvd.entity);376 377 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {378 if (adev->uvd.harvest_config & (1 << j))379 continue;380 kvfree(adev->uvd.inst[j].saved_bo);381 382 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,383 &adev->uvd.inst[j].gpu_addr,384 (void **)&adev->uvd.inst[j].cpu_addr);385 386 amdgpu_ring_fini(&adev->uvd.inst[j].ring);387 388 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)389 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);390 }391 amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr);392 amdgpu_ucode_release(&adev->uvd.fw);393 394 return 0;395}396 397/**398 * amdgpu_uvd_entity_init - init entity399 *400 * @adev: amdgpu_device pointer401 * @ring: amdgpu_ring pointer to check402 *403 * Initialize the entity used for handle management in the kernel driver.404 */405int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring)406{407 if (ring == &adev->uvd.inst[0].ring) {408 struct drm_gpu_scheduler *sched = &ring->sched;409 int r;410 411 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL,412 &sched, 1, NULL);413 if (r) {414 DRM_ERROR("Failed setting up UVD kernel entity.\n");415 return r;416 }417 }418 419 return 0;420}421 422int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev)423{424 unsigned int size;425 void *ptr;426 int i, j, idx;427 428 cancel_delayed_work_sync(&adev->uvd.idle_work);429 430 /* only valid for physical mode */431 if (adev->asic_type < CHIP_POLARIS10) {432 for (i = 0; i < adev->uvd.max_handles; ++i)433 if (atomic_read(&adev->uvd.handles[i]))434 break;435 436 if (i == adev->uvd.max_handles)437 return 0;438 }439 440 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {441 if (adev->uvd.harvest_config & (1 << j))442 continue;443 if (adev->uvd.inst[j].vcpu_bo == NULL)444 continue;445 446 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);447 ptr = adev->uvd.inst[j].cpu_addr;448 449 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);450 if (!adev->uvd.inst[j].saved_bo)451 return -ENOMEM;452 453 if (drm_dev_enter(adev_to_drm(adev), &idx)) {454 /* re-write 0 since err_event_athub will corrupt VCPU buffer */455 if (amdgpu_ras_intr_triggered())456 memset(adev->uvd.inst[j].saved_bo, 0, size);457 else458 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);459 460 drm_dev_exit(idx);461 }462 }463 464 return 0;465}466 467int amdgpu_uvd_suspend(struct amdgpu_device *adev)468{469 if (amdgpu_ras_intr_triggered())470 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");471 472 return 0;473}474 475int amdgpu_uvd_resume(struct amdgpu_device *adev)476{477 unsigned int size;478 void *ptr;479 int i, idx;480 481 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {482 if (adev->uvd.harvest_config & (1 << i))483 continue;484 if (adev->uvd.inst[i].vcpu_bo == NULL)485 return -EINVAL;486 487 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);488 ptr = adev->uvd.inst[i].cpu_addr;489 490 if (adev->uvd.inst[i].saved_bo != NULL) {491 if (drm_dev_enter(adev_to_drm(adev), &idx)) {492 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);493 drm_dev_exit(idx);494 }495 kvfree(adev->uvd.inst[i].saved_bo);496 adev->uvd.inst[i].saved_bo = NULL;497 } else {498 const struct common_firmware_header *hdr;499 unsigned int offset;500 501 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;502 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {503 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);504 if (drm_dev_enter(adev_to_drm(adev), &idx)) {505 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,506 le32_to_cpu(hdr->ucode_size_bytes));507 drm_dev_exit(idx);508 }509 size -= le32_to_cpu(hdr->ucode_size_bytes);510 ptr += le32_to_cpu(hdr->ucode_size_bytes);511 }512 memset_io(ptr, 0, size);513 /* to restore uvd fence seq */514 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);515 }516 }517 return 0;518}519 520void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)521{522 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;523 int i, r;524 525 for (i = 0; i < adev->uvd.max_handles; ++i) {526 uint32_t handle = atomic_read(&adev->uvd.handles[i]);527 528 if (handle != 0 && adev->uvd.filp[i] == filp) {529 struct dma_fence *fence;530 531 r = amdgpu_uvd_get_destroy_msg(ring, handle, false,532 &fence);533 if (r) {534 DRM_ERROR("Error destroying UVD %d!\n", r);535 continue;536 }537 538 dma_fence_wait(fence, false);539 dma_fence_put(fence);540 541 adev->uvd.filp[i] = NULL;542 atomic_set(&adev->uvd.handles[i], 0);543 }544 }545}546 547static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)548{549 int i;550 551 for (i = 0; i < abo->placement.num_placement; ++i) {552 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;553 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;554 }555}556 557static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)558{559 uint32_t lo, hi;560 uint64_t addr;561 562 lo = amdgpu_ib_get_value(ctx->ib, ctx->data0);563 hi = amdgpu_ib_get_value(ctx->ib, ctx->data1);564 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);565 566 return addr;567}568 569/**570 * amdgpu_uvd_cs_pass1 - first parsing round571 *572 * @ctx: UVD parser context573 *574 * Make sure UVD message and feedback buffers are in VRAM and575 * nobody is violating an 256MB boundary.576 */577static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)578{579 struct ttm_operation_ctx tctx = { false, false };580 struct amdgpu_bo_va_mapping *mapping;581 struct amdgpu_bo *bo;582 uint32_t cmd;583 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);584 int r = 0;585 586 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);587 if (r) {588 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);589 return r;590 }591 592 if (!ctx->parser->adev->uvd.address_64_bit) {593 /* check if it's a message or feedback command */594 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1;595 if (cmd == 0x0 || cmd == 0x3) {596 /* yes, force it into VRAM */597 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;598 599 amdgpu_bo_placement_from_domain(bo, domain);600 }601 amdgpu_uvd_force_into_uvd_segment(bo);602 603 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);604 }605 606 return r;607}608 609/**610 * amdgpu_uvd_cs_msg_decode - handle UVD decode message611 *612 * @adev: amdgpu_device pointer613 * @msg: pointer to message structure614 * @buf_sizes: placeholder to put the different buffer lengths615 *616 * Peek into the decode message and calculate the necessary buffer sizes.617 */618static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,619 unsigned int buf_sizes[])620{621 unsigned int stream_type = msg[4];622 unsigned int width = msg[6];623 unsigned int height = msg[7];624 unsigned int dpb_size = msg[9];625 unsigned int pitch = msg[28];626 unsigned int level = msg[57];627 628 unsigned int width_in_mb = width / 16;629 unsigned int height_in_mb = ALIGN(height / 16, 2);630 unsigned int fs_in_mb = width_in_mb * height_in_mb;631 632 unsigned int image_size, tmp, min_dpb_size, num_dpb_buffer;633 unsigned int min_ctx_size = ~0;634 635 image_size = width * height;636 image_size += image_size / 2;637 image_size = ALIGN(image_size, 1024);638 639 switch (stream_type) {640 case 0: /* H264 */641 switch (level) {642 case 30:643 num_dpb_buffer = 8100 / fs_in_mb;644 break;645 case 31:646 num_dpb_buffer = 18000 / fs_in_mb;647 break;648 case 32:649 num_dpb_buffer = 20480 / fs_in_mb;650 break;651 case 41:652 num_dpb_buffer = 32768 / fs_in_mb;653 break;654 case 42:655 num_dpb_buffer = 34816 / fs_in_mb;656 break;657 case 50:658 num_dpb_buffer = 110400 / fs_in_mb;659 break;660 case 51:661 num_dpb_buffer = 184320 / fs_in_mb;662 break;663 default:664 num_dpb_buffer = 184320 / fs_in_mb;665 break;666 }667 num_dpb_buffer++;668 if (num_dpb_buffer > 17)669 num_dpb_buffer = 17;670 671 /* reference picture buffer */672 min_dpb_size = image_size * num_dpb_buffer;673 674 /* macroblock context buffer */675 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;676 677 /* IT surface buffer */678 min_dpb_size += width_in_mb * height_in_mb * 32;679 break;680 681 case 1: /* VC1 */682 683 /* reference picture buffer */684 min_dpb_size = image_size * 3;685 686 /* CONTEXT_BUFFER */687 min_dpb_size += width_in_mb * height_in_mb * 128;688 689 /* IT surface buffer */690 min_dpb_size += width_in_mb * 64;691 692 /* DB surface buffer */693 min_dpb_size += width_in_mb * 128;694 695 /* BP */696 tmp = max(width_in_mb, height_in_mb);697 min_dpb_size += ALIGN(tmp * 7 * 16, 64);698 break;699 700 case 3: /* MPEG2 */701 702 /* reference picture buffer */703 min_dpb_size = image_size * 3;704 break;705 706 case 4: /* MPEG4 */707 708 /* reference picture buffer */709 min_dpb_size = image_size * 3;710 711 /* CM */712 min_dpb_size += width_in_mb * height_in_mb * 64;713 714 /* IT surface buffer */715 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);716 break;717 718 case 7: /* H264 Perf */719 switch (level) {720 case 30:721 num_dpb_buffer = 8100 / fs_in_mb;722 break;723 case 31:724 num_dpb_buffer = 18000 / fs_in_mb;725 break;726 case 32:727 num_dpb_buffer = 20480 / fs_in_mb;728 break;729 case 41:730 num_dpb_buffer = 32768 / fs_in_mb;731 break;732 case 42:733 num_dpb_buffer = 34816 / fs_in_mb;734 break;735 case 50:736 num_dpb_buffer = 110400 / fs_in_mb;737 break;738 case 51:739 num_dpb_buffer = 184320 / fs_in_mb;740 break;741 default:742 num_dpb_buffer = 184320 / fs_in_mb;743 break;744 }745 num_dpb_buffer++;746 if (num_dpb_buffer > 17)747 num_dpb_buffer = 17;748 749 /* reference picture buffer */750 min_dpb_size = image_size * num_dpb_buffer;751 752 if (!adev->uvd.use_ctx_buf) {753 /* macroblock context buffer */754 min_dpb_size +=755 width_in_mb * height_in_mb * num_dpb_buffer * 192;756 757 /* IT surface buffer */758 min_dpb_size += width_in_mb * height_in_mb * 32;759 } else {760 /* macroblock context buffer */761 min_ctx_size =762 width_in_mb * height_in_mb * num_dpb_buffer * 192;763 }764 break;765 766 case 8: /* MJPEG */767 min_dpb_size = 0;768 break;769 770 case 16: /* H265 */771 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;772 image_size = ALIGN(image_size, 256);773 774 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;775 min_dpb_size = image_size * num_dpb_buffer;776 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)777 * 16 * num_dpb_buffer + 52 * 1024;778 break;779 780 default:781 DRM_ERROR("UVD codec not handled %d!\n", stream_type);782 return -EINVAL;783 }784 785 if (width > pitch) {786 DRM_ERROR("Invalid UVD decoding target pitch!\n");787 return -EINVAL;788 }789 790 if (dpb_size < min_dpb_size) {791 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",792 dpb_size, min_dpb_size);793 return -EINVAL;794 }795 796 buf_sizes[0x1] = dpb_size;797 buf_sizes[0x2] = image_size;798 buf_sizes[0x4] = min_ctx_size;799 /* store image width to adjust nb memory pstate */800 adev->uvd.decode_image_width = width;801 return 0;802}803 804/**805 * amdgpu_uvd_cs_msg - handle UVD message806 *807 * @ctx: UVD parser context808 * @bo: buffer object containing the message809 * @offset: offset into the buffer object810 *811 * Peek into the UVD message and extract the session id.812 * Make sure that we don't open up to many sessions.813 */814static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,815 struct amdgpu_bo *bo, unsigned int offset)816{817 struct amdgpu_device *adev = ctx->parser->adev;818 int32_t *msg, msg_type, handle;819 void *ptr;820 long r;821 int i;822 823 if (offset & 0x3F) {824 DRM_ERROR("UVD messages must be 64 byte aligned!\n");825 return -EINVAL;826 }827 828 r = amdgpu_bo_kmap(bo, &ptr);829 if (r) {830 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r);831 return r;832 }833 834 msg = ptr + offset;835 836 msg_type = msg[1];837 handle = msg[2];838 839 if (handle == 0) {840 amdgpu_bo_kunmap(bo);841 DRM_ERROR("Invalid UVD handle!\n");842 return -EINVAL;843 }844 845 switch (msg_type) {846 case 0:847 /* it's a create msg, calc image size (width * height) */848 amdgpu_bo_kunmap(bo);849 850 /* try to alloc a new handle */851 for (i = 0; i < adev->uvd.max_handles; ++i) {852 if (atomic_read(&adev->uvd.handles[i]) == handle) {853 DRM_ERROR(")Handle 0x%x already in use!\n",854 handle);855 return -EINVAL;856 }857 858 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {859 adev->uvd.filp[i] = ctx->parser->filp;860 return 0;861 }862 }863 864 DRM_ERROR("No more free UVD handles!\n");865 return -ENOSPC;866 867 case 1:868 /* it's a decode msg, calc buffer sizes */869 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);870 amdgpu_bo_kunmap(bo);871 if (r)872 return r;873 874 /* validate the handle */875 for (i = 0; i < adev->uvd.max_handles; ++i) {876 if (atomic_read(&adev->uvd.handles[i]) == handle) {877 if (adev->uvd.filp[i] != ctx->parser->filp) {878 DRM_ERROR("UVD handle collision detected!\n");879 return -EINVAL;880 }881 return 0;882 }883 }884 885 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);886 return -ENOENT;887 888 case 2:889 /* it's a destroy msg, free the handle */890 for (i = 0; i < adev->uvd.max_handles; ++i)891 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);892 amdgpu_bo_kunmap(bo);893 return 0;894 895 default:896 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);897 }898 899 amdgpu_bo_kunmap(bo);900 return -EINVAL;901}902 903/**904 * amdgpu_uvd_cs_pass2 - second parsing round905 *906 * @ctx: UVD parser context907 *908 * Patch buffer addresses, make sure buffer sizes are correct.909 */910static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)911{912 struct amdgpu_bo_va_mapping *mapping;913 struct amdgpu_bo *bo;914 uint32_t cmd;915 uint64_t start, end;916 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);917 int r;918 919 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);920 if (r) {921 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);922 return r;923 }924 925 start = amdgpu_bo_gpu_offset(bo);926 927 end = (mapping->last + 1 - mapping->start);928 end = end * AMDGPU_GPU_PAGE_SIZE + start;929 930 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;931 start += addr;932 933 amdgpu_ib_set_value(ctx->ib, ctx->data0, lower_32_bits(start));934 amdgpu_ib_set_value(ctx->ib, ctx->data1, upper_32_bits(start));935 936 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1;937 if (cmd < 0x4) {938 if ((end - start) < ctx->buf_sizes[cmd]) {939 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,940 (unsigned int)(end - start),941 ctx->buf_sizes[cmd]);942 return -EINVAL;943 }944 945 } else if (cmd == 0x206) {946 if ((end - start) < ctx->buf_sizes[4]) {947 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,948 (unsigned int)(end - start),949 ctx->buf_sizes[4]);950 return -EINVAL;951 }952 } else if ((cmd != 0x100) && (cmd != 0x204)) {953 DRM_ERROR("invalid UVD command %X!\n", cmd);954 return -EINVAL;955 }956 957 if (!ctx->parser->adev->uvd.address_64_bit) {958 if ((start >> 28) != ((end - 1) >> 28)) {959 DRM_ERROR("reloc %llx-%llx crossing 256MB boundary!\n",960 start, end);961 return -EINVAL;962 }963 964 if ((cmd == 0 || cmd == 0x3) &&965 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {966 DRM_ERROR("msg/fb buffer %llx-%llx out of 256MB segment!\n",967 start, end);968 return -EINVAL;969 }970 }971 972 if (cmd == 0) {973 ctx->has_msg_cmd = true;974 r = amdgpu_uvd_cs_msg(ctx, bo, addr);975 if (r)976 return r;977 } else if (!ctx->has_msg_cmd) {978 DRM_ERROR("Message needed before other commands are send!\n");979 return -EINVAL;980 }981 982 return 0;983}984 985/**986 * amdgpu_uvd_cs_reg - parse register writes987 *988 * @ctx: UVD parser context989 * @cb: callback function990 *991 * Parse the register writes, call cb on each complete command.992 */993static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,994 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))995{996 int i, r;997 998 ctx->idx++;999 for (i = 0; i <= ctx->count; ++i) {1000 unsigned int reg = ctx->reg + i;1001 1002 if (ctx->idx >= ctx->ib->length_dw) {1003 DRM_ERROR("Register command after end of CS!\n");1004 return -EINVAL;1005 }1006 1007 switch (reg) {1008 case mmUVD_GPCOM_VCPU_DATA0:1009 ctx->data0 = ctx->idx;1010 break;1011 case mmUVD_GPCOM_VCPU_DATA1:1012 ctx->data1 = ctx->idx;1013 break;1014 case mmUVD_GPCOM_VCPU_CMD:1015 r = cb(ctx);1016 if (r)1017 return r;1018 break;1019 case mmUVD_ENGINE_CNTL:1020 case mmUVD_NO_OP:1021 break;1022 default:1023 DRM_ERROR("Invalid reg 0x%X!\n", reg);1024 return -EINVAL;1025 }1026 ctx->idx++;1027 }1028 return 0;1029}1030 1031/**1032 * amdgpu_uvd_cs_packets - parse UVD packets1033 *1034 * @ctx: UVD parser context1035 * @cb: callback function1036 *1037 * Parse the command stream packets.1038 */1039static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,1040 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))1041{1042 int r;1043 1044 for (ctx->idx = 0 ; ctx->idx < ctx->ib->length_dw; ) {1045 uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx);1046 unsigned int type = CP_PACKET_GET_TYPE(cmd);1047 1048 switch (type) {1049 case PACKET_TYPE0:1050 ctx->reg = CP_PACKET0_GET_REG(cmd);1051 ctx->count = CP_PACKET_GET_COUNT(cmd);1052 r = amdgpu_uvd_cs_reg(ctx, cb);1053 if (r)1054 return r;1055 break;1056 case PACKET_TYPE2:1057 ++ctx->idx;1058 break;1059 default:1060 DRM_ERROR("Unknown packet type %d !\n", type);1061 return -EINVAL;1062 }1063 }1064 return 0;1065}1066 1067/**1068 * amdgpu_uvd_ring_parse_cs - UVD command submission parser1069 *1070 * @parser: Command submission parser context1071 * @job: the job to parse1072 * @ib: the IB to patch1073 *1074 * Parse the command stream, patch in addresses as necessary.1075 */1076int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser,1077 struct amdgpu_job *job,1078 struct amdgpu_ib *ib)1079{1080 struct amdgpu_uvd_cs_ctx ctx = {};1081 unsigned int buf_sizes[] = {1082 [0x00000000] = 2048,1083 [0x00000001] = 0xFFFFFFFF,1084 [0x00000002] = 0xFFFFFFFF,1085 [0x00000003] = 2048,1086 [0x00000004] = 0xFFFFFFFF,1087 };1088 int r;1089 1090 job->vm = NULL;1091 1092 if (ib->length_dw % 16) {1093 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",1094 ib->length_dw);1095 return -EINVAL;1096 }1097 1098 ctx.parser = parser;1099 ctx.buf_sizes = buf_sizes;1100 ctx.ib = ib;1101 1102 /* first round only required on chips without UVD 64 bit address support */1103 if (!parser->adev->uvd.address_64_bit) {1104 /* first round, make sure the buffers are actually in the UVD segment */1105 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);1106 if (r)1107 return r;1108 }1109 1110 /* second round, patch buffer addresses into the command stream */1111 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);1112 if (r)1113 return r;1114 1115 if (!ctx.has_msg_cmd) {1116 DRM_ERROR("UVD-IBs need a msg command!\n");1117 return -EINVAL;1118 }1119 1120 return 0;1121}1122 1123static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,1124 bool direct, struct dma_fence **fence)1125{1126 struct amdgpu_device *adev = ring->adev;1127 struct dma_fence *f = NULL;1128 uint32_t offset, data[4];1129 struct amdgpu_job *job;1130 struct amdgpu_ib *ib;1131 uint64_t addr;1132 int i, r;1133 1134 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity,1135 AMDGPU_FENCE_OWNER_UNDEFINED,1136 64, direct ? AMDGPU_IB_POOL_DIRECT :1137 AMDGPU_IB_POOL_DELAYED, &job);1138 if (r)1139 return r;1140 1141 if (adev->asic_type >= CHIP_VEGA10)1142 offset = adev->reg_offset[UVD_HWIP][ring->me][1];1143 else1144 offset = UVD_BASE_SI;1145 1146 data[0] = PACKET0(offset + UVD_GPCOM_VCPU_DATA0, 0);1147 data[1] = PACKET0(offset + UVD_GPCOM_VCPU_DATA1, 0);1148 data[2] = PACKET0(offset + UVD_GPCOM_VCPU_CMD, 0);1149 data[3] = PACKET0(offset + UVD_NO_OP, 0);1150 1151 ib = &job->ibs[0];1152 addr = amdgpu_bo_gpu_offset(bo);1153 ib->ptr[0] = data[0];1154 ib->ptr[1] = addr;1155 ib->ptr[2] = data[1];1156 ib->ptr[3] = addr >> 32;1157 ib->ptr[4] = data[2];1158 ib->ptr[5] = 0;1159 for (i = 6; i < 16; i += 2) {1160 ib->ptr[i] = data[3];1161 ib->ptr[i+1] = 0;1162 }1163 ib->length_dw = 16;1164 1165 if (direct) {1166 r = amdgpu_job_submit_direct(job, ring, &f);1167 if (r)1168 goto err_free;1169 } else {1170 r = drm_sched_job_add_resv_dependencies(&job->base,1171 bo->tbo.base.resv,1172 DMA_RESV_USAGE_KERNEL);1173 if (r)1174 goto err_free;1175 1176 f = amdgpu_job_submit(job);1177 }1178 1179 amdgpu_bo_reserve(bo, true);1180 amdgpu_bo_fence(bo, f, false);1181 amdgpu_bo_unreserve(bo);1182 1183 if (fence)1184 *fence = dma_fence_get(f);1185 dma_fence_put(f);1186 1187 return 0;1188 1189err_free:1190 amdgpu_job_free(job);1191 return r;1192}1193 1194/* multiple fence commands without any stream commands in between can1195 * crash the vcpu so just try to emmit a dummy create/destroy msg to1196 * avoid this1197 */1198int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,1199 struct dma_fence **fence)1200{1201 struct amdgpu_device *adev = ring->adev;1202 struct amdgpu_bo *bo = adev->uvd.ib_bo;1203 uint32_t *msg;1204 int i;1205 1206 msg = amdgpu_bo_kptr(bo);1207 /* stitch together an UVD create msg */1208 msg[0] = cpu_to_le32(0x00000de4);1209 msg[1] = cpu_to_le32(0x00000000);1210 msg[2] = cpu_to_le32(handle);1211 msg[3] = cpu_to_le32(0x00000000);1212 msg[4] = cpu_to_le32(0x00000000);1213 msg[5] = cpu_to_le32(0x00000000);1214 msg[6] = cpu_to_le32(0x00000000);1215 msg[7] = cpu_to_le32(0x00000780);1216 msg[8] = cpu_to_le32(0x00000440);1217 msg[9] = cpu_to_le32(0x00000000);1218 msg[10] = cpu_to_le32(0x01b37000);1219 for (i = 11; i < 1024; ++i)1220 msg[i] = cpu_to_le32(0x0);1221 1222 return amdgpu_uvd_send_msg(ring, bo, true, fence);1223 1224}1225 1226int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,1227 bool direct, struct dma_fence **fence)1228{1229 struct amdgpu_device *adev = ring->adev;1230 struct amdgpu_bo *bo = NULL;1231 uint32_t *msg;1232 int r, i;1233 1234 if (direct) {1235 bo = adev->uvd.ib_bo;1236 } else {1237 r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo);1238 if (r)1239 return r;1240 }1241 1242 msg = amdgpu_bo_kptr(bo);1243 /* stitch together an UVD destroy msg */1244 msg[0] = cpu_to_le32(0x00000de4);1245 msg[1] = cpu_to_le32(0x00000002);1246 msg[2] = cpu_to_le32(handle);1247 msg[3] = cpu_to_le32(0x00000000);1248 for (i = 4; i < 1024; ++i)1249 msg[i] = cpu_to_le32(0x0);1250 1251 r = amdgpu_uvd_send_msg(ring, bo, direct, fence);1252 1253 if (!direct)1254 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);1255 1256 return r;1257}1258 1259static void amdgpu_uvd_idle_work_handler(struct work_struct *work)1260{1261 struct amdgpu_device *adev =1262 container_of(work, struct amdgpu_device, uvd.idle_work.work);1263 unsigned int fences = 0, i, j;1264 1265 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {1266 if (adev->uvd.harvest_config & (1 << i))1267 continue;1268 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);1269 for (j = 0; j < adev->uvd.num_enc_rings; ++j)1270 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);1271 }1272 1273 if (fences == 0) {1274 if (adev->pm.dpm_enabled) {1275 amdgpu_dpm_enable_uvd(adev, false);1276 } else {1277 amdgpu_asic_set_uvd_clocks(adev, 0, 0);1278 /* shutdown the UVD block */1279 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,1280 AMD_PG_STATE_GATE);1281 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,1282 AMD_CG_STATE_GATE);1283 }1284 } else {1285 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);1286 }1287}1288 1289void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)1290{1291 struct amdgpu_device *adev = ring->adev;1292 bool set_clocks;1293 1294 if (amdgpu_sriov_vf(adev))1295 return;1296 1297 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);1298 if (set_clocks) {1299 if (adev->pm.dpm_enabled) {1300 amdgpu_dpm_enable_uvd(adev, true);1301 } else {1302 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);1303 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,1304 AMD_CG_STATE_UNGATE);1305 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,1306 AMD_PG_STATE_UNGATE);1307 }1308 }1309}1310 1311void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)1312{1313 if (!amdgpu_sriov_vf(ring->adev))1314 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);1315}1316 1317/**1318 * amdgpu_uvd_ring_test_ib - test ib execution1319 *1320 * @ring: amdgpu_ring pointer1321 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT1322 *1323 * Test if we can successfully execute an IB1324 */1325int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)1326{1327 struct dma_fence *fence;1328 long r;1329 1330 r = amdgpu_uvd_get_create_msg(ring, 1, &fence);1331 if (r)1332 goto error;1333 1334 r = dma_fence_wait_timeout(fence, false, timeout);1335 dma_fence_put(fence);1336 if (r == 0)1337 r = -ETIMEDOUT;1338 if (r < 0)1339 goto error;1340 1341 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);1342 if (r)1343 goto error;1344 1345 r = dma_fence_wait_timeout(fence, false, timeout);1346 if (r == 0)1347 r = -ETIMEDOUT;1348 else if (r > 0)1349 r = 0;1350 1351 dma_fence_put(fence);1352 1353error:1354 return r;1355}1356 1357/**1358 * amdgpu_uvd_used_handles - returns used UVD handles1359 *1360 * @adev: amdgpu_device pointer1361 *1362 * Returns the number of UVD handles in use1363 */1364uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)1365{1366 unsigned int i;1367 uint32_t used_handles = 0;1368 1369 for (i = 0; i < adev->uvd.max_handles; ++i) {1370 /*1371 * Handles can be freed in any order, and not1372 * necessarily linear. So we need to count1373 * all non-zero handles.1374 */1375 if (atomic_read(&adev->uvd.handles[i]))1376 used_handles++;1377 }1378 1379 return used_handles;1380}1381