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1/*2 * Copyright 2016 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#ifndef __AMDGPU_VCN_H__25#define __AMDGPU_VCN_H__26 27#include "amdgpu_ras.h"28 29#define AMDGPU_VCN_STACK_SIZE (128*1024)30#define AMDGPU_VCN_CONTEXT_SIZE (512*1024)31 32#define AMDGPU_VCN_FIRMWARE_OFFSET 25633#define AMDGPU_VCN_MAX_ENC_RINGS 334 35#define AMDGPU_MAX_VCN_INSTANCES 436#define AMDGPU_MAX_VCN_ENC_RINGS (AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES)37 38#define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)39#define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)40 41#define VCN_DEC_KMD_CMD 0x8000000042#define VCN_DEC_CMD_FENCE 0x0000000043#define VCN_DEC_CMD_TRAP 0x0000000144#define VCN_DEC_CMD_WRITE_REG 0x0000000445#define VCN_DEC_CMD_REG_READ_COND_WAIT 0x0000000646#define VCN_DEC_CMD_PACKET_START 0x0000000a47#define VCN_DEC_CMD_PACKET_END 0x0000000b48 49#define VCN_DEC_SW_CMD_NO_OP 0x0000000050#define VCN_DEC_SW_CMD_END 0x0000000151#define VCN_DEC_SW_CMD_IB 0x0000000252#define VCN_DEC_SW_CMD_FENCE 0x0000000353#define VCN_DEC_SW_CMD_TRAP 0x0000000454#define VCN_DEC_SW_CMD_IB_AUTO 0x0000000555#define VCN_DEC_SW_CMD_SEMAPHORE 0x0000000656#define VCN_DEC_SW_CMD_PREEMPT_FENCE 0x0000000957#define VCN_DEC_SW_CMD_REG_WRITE 0x0000000b58#define VCN_DEC_SW_CMD_REG_WAIT 0x0000000c59 60#define VCN_ENC_CMD_NO_OP 0x0000000061#define VCN_ENC_CMD_END 0x0000000162#define VCN_ENC_CMD_IB 0x0000000263#define VCN_ENC_CMD_FENCE 0x0000000364#define VCN_ENC_CMD_TRAP 0x0000000465#define VCN_ENC_CMD_REG_WRITE 0x0000000b66#define VCN_ENC_CMD_REG_WAIT 0x0000000c67 68#define VCN_AON_SOC_ADDRESS_2_0 0x1f80069#define VCN1_AON_SOC_ADDRESS_3_0 0x4800070#define VCN_VID_IP_ADDRESS_2_0 0x071#define VCN_AON_IP_ADDRESS_2_0 0x3000072 73#define mmUVD_RBC_XX_IB_REG_CHECK 0x026b74#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 175#define mmUVD_REG_XX_MASK 0x026c76#define mmUVD_REG_XX_MASK_BASE_IDX 177 78/* 1 second timeout */79#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)80 81#define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \82 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \84 UVD_DPG_LMA_CTL__MASK_EN_MASK | \85 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \86 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \87 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \88 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \89 })90 91#define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \92 do { \93 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \94 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \95 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \96 UVD_DPG_LMA_CTL__READ_WRITE_MASK | \97 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \98 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \99 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \100 } while (0)101 102#define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \103 ({ \104 uint32_t internal_reg_offset, addr; \105 bool video_range, video1_range, aon_range, aon1_range; \106 \107 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \108 addr <<= 2; \109 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \110 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \111 video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS_3_0)) && \112 ((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS_3_0 + 0x2600))))); \113 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && \114 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600))))); \115 aon1_range = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS_3_0)) && \116 ((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS_3_0 + 0x600))))); \117 if (video_range) \118 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + \119 (VCN_VID_IP_ADDRESS_2_0)); \120 else if (aon_range) \121 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + \122 (VCN_AON_IP_ADDRESS_2_0)); \123 else if (video1_range) \124 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS_3_0) + \125 (VCN_VID_IP_ADDRESS_2_0)); \126 else if (aon1_range) \127 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS_3_0) + \128 (VCN_AON_IP_ADDRESS_2_0)); \129 else \130 internal_reg_offset = (0xFFFFF & addr); \131 \132 internal_reg_offset >>= 2; \133 })134 135#define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) \136 ({ \137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \138 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \139 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \140 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \141 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \142 })143 144#define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \145 do { \146 if (!indirect) { \147 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \148 mmUVD_DPG_LMA_DATA, value); \149 WREG32_SOC15( \150 VCN, GET_INST(VCN, inst_idx), \151 mmUVD_DPG_LMA_CTL, \152 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \153 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \154 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \155 } else { \156 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \157 offset; \158 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \159 value; \160 } \161 } while (0)162 163#define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg) \164 ({ \165 uint32_t internal_reg_offset, addr; \166 bool video_range, aon_range; \167 \168 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \169 addr <<= 2; \170 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS)) && \171 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS + 0x2600))))); \172 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS)) && \173 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS + 0x600))))); \174 if (video_range) \175 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS) + \176 (VCN_VID_IP_ADDRESS)); \177 else if (aon_range) \178 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS) + \179 (VCN_AON_IP_ADDRESS)); \180 else \181 internal_reg_offset = (0xFFFFF & addr); \182 \183 internal_reg_offset >>= 2; \184 })185 186#define WREG32_SOC24_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \187 do { \188 if (!indirect) { \189 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \190 regUVD_DPG_LMA_DATA, value); \191 WREG32_SOC15( \192 VCN, GET_INST(VCN, inst_idx), \193 regUVD_DPG_LMA_CTL, \194 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \195 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \196 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \197 } else { \198 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \199 offset; \200 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \201 value; \202 } \203 } while (0)204 205#define AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE (1 << 2)206#define AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT (1 << 4)207#define AMDGPU_VCN_FW_SHARED_FLAG_0_RB (1 << 6)208#define AMDGPU_VCN_MULTI_QUEUE_FLAG (1 << 8)209#define AMDGPU_VCN_SW_RING_FLAG (1 << 9)210#define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10)211#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)212#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)213#define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14)214#define AMDGPU_VCN_VF_RB_DECOUPLE_FLAG (1 << 15)215 216#define MAX_NUM_VCN_RB_SETUP 4217 218#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001219#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001220 221#define VCN_CODEC_DISABLE_MASK_AV1 (1 << 0)222#define VCN_CODEC_DISABLE_MASK_VP9 (1 << 1)223#define VCN_CODEC_DISABLE_MASK_HEVC (1 << 2)224#define VCN_CODEC_DISABLE_MASK_H264 (1 << 3)225 226#define AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU (0)227#define AMDGPU_VCN_SMU_DPM_INTERFACE_APU (1)228 229#define AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING 2230 231enum fw_queue_mode {232 FW_QUEUE_RING_RESET = 1,233 FW_QUEUE_DPG_HOLD_OFF = 2,234};235 236enum engine_status_constants {237 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,238 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,239 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 = 0x2A2A8AA0,240 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,241 UVD_STATUS__UVD_BUSY = 0x00000004,242 GB_ADDR_CONFIG_DEFAULT = 0x26010011,243 UVD_STATUS__IDLE = 0x2,244 UVD_STATUS__BUSY = 0x5,245 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,246 UVD_STATUS__RBC_BUSY = 0x1,247 UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,248};249 250enum internal_dpg_state {251 VCN_DPG_STATE__UNPAUSE = 0,252 VCN_DPG_STATE__PAUSE,253};254 255struct dpg_pause_state {256 enum internal_dpg_state fw_based;257 enum internal_dpg_state jpeg;258};259 260struct amdgpu_vcn_reg{261 unsigned data0;262 unsigned data1;263 unsigned cmd;264 unsigned nop;265 unsigned context_id;266 unsigned ib_vmid;267 unsigned ib_bar_low;268 unsigned ib_bar_high;269 unsigned ib_size;270 unsigned gp_scratch8;271 unsigned scratch9;272};273 274struct amdgpu_vcn_fw_shared {275 void *cpu_addr;276 uint64_t gpu_addr;277 uint32_t mem_size;278 uint32_t log_offset;279};280 281struct amdgpu_vcn_inst {282 struct amdgpu_bo *vcpu_bo;283 void *cpu_addr;284 uint64_t gpu_addr;285 void *saved_bo;286 struct amdgpu_ring ring_dec;287 struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];288 atomic_t sched_score;289 struct amdgpu_irq_src irq;290 struct amdgpu_irq_src ras_poison_irq;291 struct amdgpu_vcn_reg external;292 struct amdgpu_bo *dpg_sram_bo;293 struct dpg_pause_state pause_state;294 void *dpg_sram_cpu_addr;295 uint64_t dpg_sram_gpu_addr;296 uint32_t *dpg_sram_curr_addr;297 atomic_t dpg_enc_submission_cnt;298 struct amdgpu_vcn_fw_shared fw_shared;299 uint8_t aid_id;300};301 302struct amdgpu_vcn_ras {303 struct amdgpu_ras_block_object ras_block;304};305 306struct amdgpu_vcn {307 unsigned fw_version;308 struct delayed_work idle_work;309 const struct firmware *fw[AMDGPU_MAX_VCN_INSTANCES]; /* VCN firmware */310 unsigned num_enc_rings;311 enum amd_powergating_state cur_state;312 bool indirect_sram;313 314 uint8_t num_vcn_inst;315 struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES];316 uint8_t vcn_config[AMDGPU_MAX_VCN_INSTANCES];317 uint32_t vcn_codec_disable_mask[AMDGPU_MAX_VCN_INSTANCES];318 struct amdgpu_vcn_reg internal;319 struct mutex vcn_pg_lock;320 struct mutex vcn1_jpeg1_workaround;321 atomic_t total_submission_cnt;322 323 unsigned harvest_config;324 int (*pause_dpg_mode)(struct amdgpu_device *adev,325 int inst_idx, struct dpg_pause_state *new_state);326 327 struct ras_common_if *ras_if;328 struct amdgpu_vcn_ras *ras;329 330 uint16_t inst_mask;331 uint8_t num_inst_per_aid;332 bool using_unified_queue;333 334 /* IP reg dump */335 uint32_t *ip_dump;336};337 338struct amdgpu_fw_shared_rb_ptrs_struct {339 /* to WA DPG R/W ptr issues.*/340 uint32_t rptr;341 uint32_t wptr;342};343 344struct amdgpu_fw_shared_multi_queue {345 uint8_t decode_queue_mode;346 uint8_t encode_generalpurpose_queue_mode;347 uint8_t encode_lowlatency_queue_mode;348 uint8_t encode_realtime_queue_mode;349 uint8_t padding[4];350};351 352struct amdgpu_fw_shared_sw_ring {353 uint8_t is_enabled;354 uint8_t padding[3];355};356 357struct amdgpu_fw_shared_unified_queue_struct {358 uint8_t is_enabled;359 uint8_t queue_mode;360 uint8_t queue_status;361 uint8_t padding[5];362};363 364struct amdgpu_fw_shared_fw_logging {365 uint8_t is_enabled;366 uint32_t addr_lo;367 uint32_t addr_hi;368 uint32_t size;369};370 371struct amdgpu_fw_shared_smu_interface_info {372 uint8_t smu_interface_type;373 uint8_t padding[3];374};375 376struct amdgpu_fw_shared {377 uint32_t present_flag_0;378 uint8_t pad[44];379 struct amdgpu_fw_shared_rb_ptrs_struct rb;380 uint8_t pad1[1];381 struct amdgpu_fw_shared_multi_queue multi_queue;382 struct amdgpu_fw_shared_sw_ring sw_ring;383 struct amdgpu_fw_shared_fw_logging fw_log;384 struct amdgpu_fw_shared_smu_interface_info smu_interface_info;385};386 387struct amdgpu_vcn_rb_setup_info {388 uint32_t rb_addr_lo;389 uint32_t rb_addr_hi;390 uint32_t rb_size;391};392 393struct amdgpu_fw_shared_rb_setup {394 uint32_t is_rb_enabled_flags;395 396 union {397 struct {398 uint32_t rb_addr_lo;399 uint32_t rb_addr_hi;400 uint32_t rb_size;401 uint32_t rb4_addr_lo;402 uint32_t rb4_addr_hi;403 uint32_t rb4_size;404 uint32_t reserved[6];405 };406 407 struct {408 struct amdgpu_vcn_rb_setup_info rb_info[MAX_NUM_VCN_RB_SETUP];409 };410 };411};412 413struct amdgpu_fw_shared_drm_key_wa {414 uint8_t method;415 uint8_t reserved[3];416};417 418struct amdgpu_fw_shared_queue_decouple {419 uint8_t is_enabled;420 uint8_t reserved[7];421};422 423struct amdgpu_vcn4_fw_shared {424 uint32_t present_flag_0;425 uint8_t pad[12];426 struct amdgpu_fw_shared_unified_queue_struct sq;427 uint8_t pad1[8];428 struct amdgpu_fw_shared_fw_logging fw_log;429 uint8_t pad2[20];430 struct amdgpu_fw_shared_rb_setup rb_setup;431 struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface;432 struct amdgpu_fw_shared_drm_key_wa drm_key_wa;433 uint8_t pad3[9];434 struct amdgpu_fw_shared_queue_decouple decouple;435};436 437struct amdgpu_vcn_fwlog {438 uint32_t rptr;439 uint32_t wptr;440 uint32_t buffer_size;441 uint32_t header_size;442 uint8_t wrapped;443};444 445struct amdgpu_vcn_decode_buffer {446 uint32_t valid_buf_flag;447 uint32_t msg_buffer_address_hi;448 uint32_t msg_buffer_address_lo;449 uint32_t pad[30];450};451 452struct amdgpu_vcn_rb_metadata {453 uint32_t size;454 uint32_t present_flag_0;455 456 uint8_t version;457 uint8_t ring_id;458 uint8_t pad[26];459};460 461struct amdgpu_vcn5_fw_shared {462 uint32_t present_flag_0;463 uint8_t pad[12];464 struct amdgpu_fw_shared_unified_queue_struct sq;465 uint8_t pad1[8];466 struct amdgpu_fw_shared_fw_logging fw_log;467 uint8_t pad2[20];468 struct amdgpu_fw_shared_rb_setup rb_setup;469 struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface;470 struct amdgpu_fw_shared_drm_key_wa drm_key_wa;471 uint8_t pad3[9];472};473 474#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80475#define VCN_BLOCK_DECODE_DISABLE_MASK 0x40476#define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0477 478enum vcn_ring_type {479 VCN_ENCODE_RING,480 VCN_DECODE_RING,481 VCN_UNIFIED_RING,482};483 484int amdgpu_vcn_early_init(struct amdgpu_device *adev);485int amdgpu_vcn_sw_init(struct amdgpu_device *adev);486int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);487int amdgpu_vcn_suspend(struct amdgpu_device *adev);488int amdgpu_vcn_resume(struct amdgpu_device *adev);489void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);490void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);491 492bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev,493 enum vcn_ring_type type, uint32_t vcn_instance);494 495int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);496int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);497int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);498int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout);499int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout);500 501int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);502int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);503 504enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring);505 506void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev);507 508void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn);509void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev,510 uint8_t i, struct amdgpu_vcn_inst *vcn);511 512int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,513 struct amdgpu_irq_src *source,514 struct amdgpu_iv_entry *entry);515int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev,516 struct ras_common_if *ras_block);517int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev);518 519int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,520 enum AMDGPU_UCODE_ID ucode_id);521 522#endif523