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1/*2 * Copyright 2022 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22 23#include <linux/firmware.h>24#include <drm/drm_drv.h>25 26#include "amdgpu.h"27#include "amdgpu_ucode.h"28#include "amdgpu_vpe.h"29#include "amdgpu_smu.h"30#include "soc15_common.h"31#include "vpe_v6_1.h"32 33#define AMDGPU_CSA_VPE_SIZE 6434/* VPE CSA resides in the 4th page of CSA */35#define AMDGPU_CSA_VPE_OFFSET (4096 * 3)36 37/* 1 second timeout */38#define VPE_IDLE_TIMEOUT msecs_to_jiffies(1000)39 40#define VPE_MAX_DPM_LEVEL 441#define FIXED1_8_BITS_PER_FRACTIONAL_PART 842#define GET_PRATIO_INTEGER_PART(x) ((x) >> FIXED1_8_BITS_PER_FRACTIONAL_PART)43 44static void vpe_set_ring_funcs(struct amdgpu_device *adev);45 46static inline uint16_t div16_u16_rem(uint16_t dividend, uint16_t divisor, uint16_t *remainder)47{48 *remainder = dividend % divisor;49 return dividend / divisor;50}51 52static inline uint16_t complete_integer_division_u16(53 uint16_t dividend,54 uint16_t divisor,55 uint16_t *remainder)56{57 return div16_u16_rem(dividend, divisor, (uint16_t *)remainder);58}59 60static uint16_t vpe_u1_8_from_fraction(uint16_t numerator, uint16_t denominator)61{62 u16 arg1_value = numerator;63 u16 arg2_value = denominator;64 65 uint16_t remainder;66 67 /* determine integer part */68 uint16_t res_value = complete_integer_division_u16(69 arg1_value, arg2_value, &remainder);70 71 if (res_value > 127 /* CHAR_MAX */)72 return 0;73 74 /* determine fractional part */75 {76 unsigned int i = FIXED1_8_BITS_PER_FRACTIONAL_PART;77 78 do {79 remainder <<= 1;80 81 res_value <<= 1;82 83 if (remainder >= arg2_value) {84 res_value |= 1;85 remainder -= arg2_value;86 }87 } while (--i != 0);88 }89 90 /* round up LSB */91 {92 uint16_t summand = (remainder << 1) >= arg2_value;93 94 if ((res_value + summand) > 32767 /* SHRT_MAX */)95 return 0;96 97 res_value += summand;98 }99 100 return res_value;101}102 103static uint16_t vpe_internal_get_pratio(uint16_t from_frequency, uint16_t to_frequency)104{105 uint16_t pratio = vpe_u1_8_from_fraction(from_frequency, to_frequency);106 107 if (GET_PRATIO_INTEGER_PART(pratio) > 1)108 pratio = 0;109 110 return pratio;111}112 113/*114 * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest),115 * VPE FW will dynamically decide which level should be used according to current loading.116 *117 * Get VPE and SOC clocks from PM, and select the appropriate four clock values,118 * calculate the ratios of adjusting from one clock to another.119 * The VPE FW can then request the appropriate frequency from the PMFW.120 */121int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)122{123 struct amdgpu_device *adev = vpe->ring.adev;124 uint32_t dpm_ctl;125 126 if (adev->pm.dpm_enabled) {127 struct dpm_clocks clock_table = { 0 };128 struct dpm_clock *VPEClks;129 struct dpm_clock *SOCClks;130 uint32_t idx;131 uint32_t vpeclk_enalbled_num = 0;132 uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0;133 uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0;134 135 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));136 dpm_ctl |= 1; /* DPM enablement */137 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);138 139 /* Get VPECLK and SOCCLK */140 if (amdgpu_dpm_get_dpm_clock_table(adev, &clock_table)) {141 dev_dbg(adev->dev, "%s: get clock failed!\n", __func__);142 goto disable_dpm;143 }144 145 SOCClks = clock_table.SocClocks;146 VPEClks = clock_table.VPEClocks;147 148 /* Comfirm enabled vpe clk num149 * Enabled VPE clocks are ordered from low to high in VPEClks150 * The highest valid clock index+1 is the number of VPEClks151 */152 for (idx = PP_SMU_NUM_VPECLK_DPM_LEVELS; idx && !vpeclk_enalbled_num; idx--)153 if (VPEClks[idx-1].Freq)154 vpeclk_enalbled_num = idx;155 156 /* vpe dpm only cares 4 levels. */157 for (idx = 0; idx < VPE_MAX_DPM_LEVEL; idx++) {158 uint32_t soc_dpm_level;159 uint32_t min_freq;160 161 if (idx == 0)162 soc_dpm_level = 0;163 else164 soc_dpm_level = (idx * 2) + 1;165 166 /* clamp the max level */167 if (soc_dpm_level > vpeclk_enalbled_num - 1)168 soc_dpm_level = vpeclk_enalbled_num - 1;169 170 min_freq = (SOCClks[soc_dpm_level].Freq < VPEClks[soc_dpm_level].Freq) ?171 SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq;172 173 switch (idx) {174 case 0:175 pratio_vmin_freq = min_freq;176 break;177 case 1:178 pratio_vmid_freq = min_freq;179 break;180 case 2:181 pratio_vnorm_freq = min_freq;182 break;183 case 3:184 pratio_vmax_freq = min_freq;185 break;186 default:187 break;188 }189 }190 191 if (pratio_vmin_freq && pratio_vmid_freq && pratio_vnorm_freq && pratio_vmax_freq) {192 uint32_t pratio_ctl;193 194 pratio_vmax_vnorm = (uint32_t)vpe_internal_get_pratio(pratio_vmax_freq, pratio_vnorm_freq);195 pratio_vnorm_vmid = (uint32_t)vpe_internal_get_pratio(pratio_vnorm_freq, pratio_vmid_freq);196 pratio_vmid_vmin = (uint32_t)vpe_internal_get_pratio(pratio_vmid_freq, pratio_vmin_freq);197 198 pratio_ctl = pratio_vmax_vnorm | (pratio_vnorm_vmid << 9) | (pratio_vmid_vmin << 18);199 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */200 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */201 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */202 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */203 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */204 dev_dbg(adev->dev, "%s: configure vpe dpm pratio done!\n", __func__);205 } else {206 dev_dbg(adev->dev, "%s: invalid pratio parameters!\n", __func__);207 goto disable_dpm;208 }209 }210 return 0;211 212disable_dpm:213 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));214 dpm_ctl &= 0xfffffffe; /* Disable DPM */215 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);216 dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__);217 return -EINVAL;218}219 220int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev)221{222 struct amdgpu_firmware_info ucode = {223 .ucode_id = AMDGPU_UCODE_ID_VPE,224 .mc_addr = adev->vpe.cmdbuf_gpu_addr,225 .ucode_size = 8,226 };227 228 return psp_execute_ip_fw_load(&adev->psp, &ucode);229}230 231int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe)232{233 struct amdgpu_device *adev = vpe->ring.adev;234 const struct vpe_firmware_header_v1_0 *vpe_hdr;235 char fw_prefix[32];236 int ret;237 238 amdgpu_ucode_ip_version_decode(adev, VPE_HWIP, fw_prefix, sizeof(fw_prefix));239 ret = amdgpu_ucode_request(adev, &adev->vpe.fw, "amdgpu/%s.bin", fw_prefix);240 if (ret)241 goto out;242 243 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;244 adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version);245 adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version);246 247 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {248 struct amdgpu_firmware_info *info;249 250 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTX];251 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTX;252 info->fw = adev->vpe.fw;253 adev->firmware.fw_size +=254 ALIGN(le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes), PAGE_SIZE);255 256 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTL];257 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTL;258 info->fw = adev->vpe.fw;259 adev->firmware.fw_size +=260 ALIGN(le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes), PAGE_SIZE);261 }262 263 return 0;264out:265 dev_err(adev->dev, "fail to initialize vpe microcode\n");266 release_firmware(adev->vpe.fw);267 adev->vpe.fw = NULL;268 return ret;269}270 271int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe)272{273 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);274 struct amdgpu_ring *ring = &vpe->ring;275 int ret;276 277 ring->ring_obj = NULL;278 ring->use_doorbell = true;279 ring->vm_hub = AMDGPU_MMHUB0(0);280 ring->doorbell_index = (adev->doorbell_index.vpe_ring << 1);281 snprintf(ring->name, 4, "vpe");282 283 ret = amdgpu_ring_init(adev, ring, 1024, &vpe->trap_irq, 0,284 AMDGPU_RING_PRIO_DEFAULT, NULL);285 if (ret)286 return ret;287 288 return 0;289}290 291int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe)292{293 amdgpu_ring_fini(&vpe->ring);294 295 return 0;296}297 298static int vpe_early_init(void *handle)299{300 struct amdgpu_device *adev = (struct amdgpu_device *)handle;301 struct amdgpu_vpe *vpe = &adev->vpe;302 303 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {304 case IP_VERSION(6, 1, 0):305 case IP_VERSION(6, 1, 3):306 vpe_v6_1_set_funcs(vpe);307 break;308 case IP_VERSION(6, 1, 1):309 vpe_v6_1_set_funcs(vpe);310 vpe->collaborate_mode = true;311 break;312 default:313 return -EINVAL;314 }315 316 vpe_set_ring_funcs(adev);317 vpe_set_regs(vpe);318 319 dev_info(adev->dev, "VPE: collaborate mode %s", vpe->collaborate_mode ? "true" : "false");320 321 return 0;322}323 324static void vpe_idle_work_handler(struct work_struct *work)325{326 struct amdgpu_device *adev =327 container_of(work, struct amdgpu_device, vpe.idle_work.work);328 unsigned int fences = 0;329 330 fences += amdgpu_fence_count_emitted(&adev->vpe.ring);331 332 if (fences == 0)333 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);334 else335 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);336}337 338static int vpe_common_init(struct amdgpu_vpe *vpe)339{340 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);341 int r;342 343 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,344 AMDGPU_GEM_DOMAIN_GTT,345 &adev->vpe.cmdbuf_obj,346 &adev->vpe.cmdbuf_gpu_addr,347 (void **)&adev->vpe.cmdbuf_cpu_addr);348 if (r) {349 dev_err(adev->dev, "VPE: failed to allocate cmdbuf bo %d\n", r);350 return r;351 }352 353 vpe->context_started = false;354 INIT_DELAYED_WORK(&adev->vpe.idle_work, vpe_idle_work_handler);355 356 return 0;357}358 359static int vpe_sw_init(void *handle)360{361 struct amdgpu_device *adev = (struct amdgpu_device *)handle;362 struct amdgpu_vpe *vpe = &adev->vpe;363 int ret;364 365 ret = vpe_common_init(vpe);366 if (ret)367 goto out;368 369 ret = vpe_irq_init(vpe);370 if (ret)371 goto out;372 373 ret = vpe_ring_init(vpe);374 if (ret)375 goto out;376 377 ret = vpe_init_microcode(vpe);378 if (ret)379 goto out;380out:381 return ret;382}383 384static int vpe_sw_fini(void *handle)385{386 struct amdgpu_device *adev = (struct amdgpu_device *)handle;387 struct amdgpu_vpe *vpe = &adev->vpe;388 389 release_firmware(vpe->fw);390 vpe->fw = NULL;391 392 vpe_ring_fini(vpe);393 394 amdgpu_bo_free_kernel(&adev->vpe.cmdbuf_obj,395 &adev->vpe.cmdbuf_gpu_addr,396 (void **)&adev->vpe.cmdbuf_cpu_addr);397 398 return 0;399}400 401static int vpe_hw_init(void *handle)402{403 struct amdgpu_device *adev = (struct amdgpu_device *)handle;404 struct amdgpu_vpe *vpe = &adev->vpe;405 int ret;406 407 /* Power on VPE */408 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE,409 AMD_PG_STATE_UNGATE);410 if (ret)411 return ret;412 413 ret = vpe_load_microcode(vpe);414 if (ret)415 return ret;416 417 ret = vpe_ring_start(vpe);418 if (ret)419 return ret;420 421 return 0;422}423 424static int vpe_hw_fini(void *handle)425{426 struct amdgpu_device *adev = (struct amdgpu_device *)handle;427 struct amdgpu_vpe *vpe = &adev->vpe;428 429 vpe_ring_stop(vpe);430 431 /* Power off VPE */432 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);433 434 return 0;435}436 437static int vpe_suspend(void *handle)438{439 struct amdgpu_device *adev = (struct amdgpu_device *)handle;440 441 cancel_delayed_work_sync(&adev->vpe.idle_work);442 443 return vpe_hw_fini(adev);444}445 446static int vpe_resume(void *handle)447{448 struct amdgpu_device *adev = (struct amdgpu_device *)handle;449 450 return vpe_hw_init(adev);451}452 453static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)454{455 int i;456 457 for (i = 0; i < count; i++)458 if (i == 0)459 amdgpu_ring_write(ring, ring->funcs->nop |460 VPE_CMD_NOP_HEADER_COUNT(count - 1));461 else462 amdgpu_ring_write(ring, ring->funcs->nop);463}464 465static uint64_t vpe_get_csa_mc_addr(struct amdgpu_ring *ring, uint32_t vmid)466{467 struct amdgpu_device *adev = ring->adev;468 uint32_t index = 0;469 uint64_t csa_mc_addr;470 471 if (amdgpu_sriov_vf(adev) || vmid == 0 || !adev->gfx.mcbp)472 return 0;473 474 csa_mc_addr = amdgpu_csa_vaddr(adev) + AMDGPU_CSA_VPE_OFFSET +475 index * AMDGPU_CSA_VPE_SIZE;476 477 return csa_mc_addr;478}479 480static void vpe_ring_emit_pred_exec(struct amdgpu_ring *ring,481 uint32_t device_select,482 uint32_t exec_count)483{484 if (!ring->adev->vpe.collaborate_mode)485 return;486 487 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_PRED_EXE, 0) |488 (device_select << 16));489 amdgpu_ring_write(ring, exec_count & 0x1fff);490}491 492static void vpe_ring_emit_ib(struct amdgpu_ring *ring,493 struct amdgpu_job *job,494 struct amdgpu_ib *ib,495 uint32_t flags)496{497 uint32_t vmid = AMDGPU_JOB_GET_VMID(job);498 uint64_t csa_mc_addr = vpe_get_csa_mc_addr(ring, vmid);499 500 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) |501 VPE_CMD_INDIRECT_HEADER_VMID(vmid & 0xf));502 503 /* base must be 32 byte aligned */504 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0);505 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));506 amdgpu_ring_write(ring, ib->length_dw);507 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));508 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));509}510 511static void vpe_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr,512 uint64_t seq, unsigned int flags)513{514 int i = 0;515 516 do {517 /* write the fence */518 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0));519 /* zero in first two bits */520 WARN_ON_ONCE(addr & 0x3);521 amdgpu_ring_write(ring, lower_32_bits(addr));522 amdgpu_ring_write(ring, upper_32_bits(addr));523 amdgpu_ring_write(ring, i == 0 ? lower_32_bits(seq) : upper_32_bits(seq));524 addr += 4;525 } while ((flags & AMDGPU_FENCE_FLAG_64BIT) && (i++ < 1));526 527 if (flags & AMDGPU_FENCE_FLAG_INT) {528 /* generate an interrupt */529 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_TRAP, 0));530 amdgpu_ring_write(ring, 0);531 }532 533}534 535static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring)536{537 uint32_t seq = ring->fence_drv.sync_seq;538 uint64_t addr = ring->fence_drv.gpu_addr;539 540 vpe_ring_emit_pred_exec(ring, 0, 6);541 542 /* wait for idle */543 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM,544 VPE_POLL_REGMEM_SUBOP_REGMEM) |545 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */546 VPE_CMD_POLL_REGMEM_HEADER_MEM(1));547 amdgpu_ring_write(ring, addr & 0xfffffffc);548 amdgpu_ring_write(ring, upper_32_bits(addr));549 amdgpu_ring_write(ring, seq); /* reference */550 amdgpu_ring_write(ring, 0xffffffff); /* mask */551 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |552 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(4));553}554 555static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)556{557 vpe_ring_emit_pred_exec(ring, 0, 3);558 559 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_REG_WRITE, 0));560 amdgpu_ring_write(ring, reg << 2);561 amdgpu_ring_write(ring, val);562}563 564static void vpe_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,565 uint32_t val, uint32_t mask)566{567 vpe_ring_emit_pred_exec(ring, 0, 6);568 569 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM,570 VPE_POLL_REGMEM_SUBOP_REGMEM) |571 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */572 VPE_CMD_POLL_REGMEM_HEADER_MEM(0));573 amdgpu_ring_write(ring, reg << 2);574 amdgpu_ring_write(ring, 0);575 amdgpu_ring_write(ring, val); /* reference */576 amdgpu_ring_write(ring, mask); /* mask */577 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |578 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(10));579}580 581static void vpe_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid,582 uint64_t pd_addr)583{584 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);585}586 587static unsigned int vpe_ring_init_cond_exec(struct amdgpu_ring *ring,588 uint64_t addr)589{590 unsigned int ret;591 592 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COND_EXE, 0));593 amdgpu_ring_write(ring, lower_32_bits(addr));594 amdgpu_ring_write(ring, upper_32_bits(addr));595 amdgpu_ring_write(ring, 1);596 ret = ring->wptr & ring->buf_mask;597 amdgpu_ring_write(ring, 0);598 599 return ret;600}601 602static int vpe_ring_preempt_ib(struct amdgpu_ring *ring)603{604 struct amdgpu_device *adev = ring->adev;605 struct amdgpu_vpe *vpe = &adev->vpe;606 uint32_t preempt_reg = vpe->regs.queue0_preempt;607 int i, r = 0;608 609 /* assert preemption condition */610 amdgpu_ring_set_preempt_cond_exec(ring, false);611 612 /* emit the trailing fence */613 ring->trail_seq += 1;614 amdgpu_ring_alloc(ring, 10);615 vpe_ring_emit_fence(ring, ring->trail_fence_gpu_addr, ring->trail_seq, 0);616 amdgpu_ring_commit(ring);617 618 /* assert IB preemption */619 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 1);620 621 /* poll the trailing fence */622 for (i = 0; i < adev->usec_timeout; i++) {623 if (ring->trail_seq ==624 le32_to_cpu(*(ring->trail_fence_cpu_addr)))625 break;626 udelay(1);627 }628 629 if (i >= adev->usec_timeout) {630 r = -EINVAL;631 dev_err(adev->dev, "ring %d failed to be preempted\n", ring->idx);632 }633 634 /* deassert IB preemption */635 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 0);636 637 /* deassert the preemption condition */638 amdgpu_ring_set_preempt_cond_exec(ring, true);639 640 return r;641}642 643static int vpe_set_clockgating_state(void *handle,644 enum amd_clockgating_state state)645{646 return 0;647}648 649static int vpe_set_powergating_state(void *handle,650 enum amd_powergating_state state)651{652 struct amdgpu_device *adev = (struct amdgpu_device *)handle;653 struct amdgpu_vpe *vpe = &adev->vpe;654 655 if (!adev->pm.dpm_enabled)656 dev_err(adev->dev, "Without PM, cannot support powergating\n");657 658 dev_dbg(adev->dev, "%s: %s!\n", __func__, (state == AMD_PG_STATE_GATE) ? "GATE":"UNGATE");659 660 if (state == AMD_PG_STATE_GATE) {661 amdgpu_dpm_enable_vpe(adev, false);662 vpe->context_started = false;663 } else {664 amdgpu_dpm_enable_vpe(adev, true);665 }666 667 return 0;668}669 670static uint64_t vpe_ring_get_rptr(struct amdgpu_ring *ring)671{672 struct amdgpu_device *adev = ring->adev;673 struct amdgpu_vpe *vpe = &adev->vpe;674 uint64_t rptr;675 676 if (ring->use_doorbell) {677 rptr = atomic64_read((atomic64_t *)ring->rptr_cpu_addr);678 dev_dbg(adev->dev, "rptr/doorbell before shift == 0x%016llx\n", rptr);679 } else {680 rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi));681 rptr = rptr << 32;682 rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo));683 dev_dbg(adev->dev, "rptr before shift [%i] == 0x%016llx\n", ring->me, rptr);684 }685 686 return (rptr >> 2);687}688 689static uint64_t vpe_ring_get_wptr(struct amdgpu_ring *ring)690{691 struct amdgpu_device *adev = ring->adev;692 struct amdgpu_vpe *vpe = &adev->vpe;693 uint64_t wptr;694 695 if (ring->use_doorbell) {696 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);697 dev_dbg(adev->dev, "wptr/doorbell before shift == 0x%016llx\n", wptr);698 } else {699 wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi));700 wptr = wptr << 32;701 wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo));702 dev_dbg(adev->dev, "wptr before shift [%i] == 0x%016llx\n", ring->me, wptr);703 }704 705 return (wptr >> 2);706}707 708static void vpe_ring_set_wptr(struct amdgpu_ring *ring)709{710 struct amdgpu_device *adev = ring->adev;711 struct amdgpu_vpe *vpe = &adev->vpe;712 713 if (ring->use_doorbell) {714 dev_dbg(adev->dev, "Using doorbell, \715 wptr_offs == 0x%08x, \716 lower_32_bits(ring->wptr) << 2 == 0x%08x, \717 upper_32_bits(ring->wptr) << 2 == 0x%08x\n",718 ring->wptr_offs,719 lower_32_bits(ring->wptr << 2),720 upper_32_bits(ring->wptr << 2));721 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr << 2);722 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);723 if (vpe->collaborate_mode)724 WDOORBELL64(ring->doorbell_index + 4, ring->wptr << 2);725 } else {726 int i;727 728 for (i = 0; i < vpe->num_instances; i++) {729 dev_dbg(adev->dev, "Not using doorbell, \730 regVPEC_QUEUE0_RB_WPTR == 0x%08x, \731 regVPEC_QUEUE0_RB_WPTR_HI == 0x%08x\n",732 lower_32_bits(ring->wptr << 2),733 upper_32_bits(ring->wptr << 2));734 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_lo),735 lower_32_bits(ring->wptr << 2));736 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_hi),737 upper_32_bits(ring->wptr << 2));738 }739 }740}741 742static int vpe_ring_test_ring(struct amdgpu_ring *ring)743{744 struct amdgpu_device *adev = ring->adev;745 const uint32_t test_pattern = 0xdeadbeef;746 uint32_t index, i;747 uint64_t wb_addr;748 int ret;749 750 ret = amdgpu_device_wb_get(adev, &index);751 if (ret) {752 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret);753 return ret;754 }755 756 adev->wb.wb[index] = 0;757 wb_addr = adev->wb.gpu_addr + (index * 4);758 759 ret = amdgpu_ring_alloc(ring, 4);760 if (ret) {761 dev_err(adev->dev, "amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, ret);762 goto out;763 }764 765 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0));766 amdgpu_ring_write(ring, lower_32_bits(wb_addr));767 amdgpu_ring_write(ring, upper_32_bits(wb_addr));768 amdgpu_ring_write(ring, test_pattern);769 amdgpu_ring_commit(ring);770 771 for (i = 0; i < adev->usec_timeout; i++) {772 if (le32_to_cpu(adev->wb.wb[index]) == test_pattern)773 goto out;774 udelay(1);775 }776 777 ret = -ETIMEDOUT;778out:779 amdgpu_device_wb_free(adev, index);780 781 return ret;782}783 784static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout)785{786 struct amdgpu_device *adev = ring->adev;787 const uint32_t test_pattern = 0xdeadbeef;788 struct amdgpu_ib ib = {};789 struct dma_fence *f = NULL;790 uint32_t index;791 uint64_t wb_addr;792 int ret;793 794 ret = amdgpu_device_wb_get(adev, &index);795 if (ret) {796 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret);797 return ret;798 }799 800 adev->wb.wb[index] = 0;801 wb_addr = adev->wb.gpu_addr + (index * 4);802 803 ret = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);804 if (ret)805 goto err0;806 807 ib.ptr[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0);808 ib.ptr[1] = lower_32_bits(wb_addr);809 ib.ptr[2] = upper_32_bits(wb_addr);810 ib.ptr[3] = test_pattern;811 ib.ptr[4] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);812 ib.ptr[5] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);813 ib.ptr[6] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);814 ib.ptr[7] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);815 ib.length_dw = 8;816 817 ret = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);818 if (ret)819 goto err1;820 821 ret = dma_fence_wait_timeout(f, false, timeout);822 if (ret <= 0) {823 ret = ret ? : -ETIMEDOUT;824 goto err1;825 }826 827 ret = (le32_to_cpu(adev->wb.wb[index]) == test_pattern) ? 0 : -EINVAL;828 829err1:830 amdgpu_ib_free(adev, &ib, NULL);831 dma_fence_put(f);832err0:833 amdgpu_device_wb_free(adev, index);834 835 return ret;836}837 838static void vpe_ring_begin_use(struct amdgpu_ring *ring)839{840 struct amdgpu_device *adev = ring->adev;841 struct amdgpu_vpe *vpe = &adev->vpe;842 843 cancel_delayed_work_sync(&adev->vpe.idle_work);844 845 /* Power on VPE and notify VPE of new context */846 if (!vpe->context_started) {847 uint32_t context_notify;848 849 /* Power on VPE */850 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE);851 852 /* Indicates that a job from a new context has been submitted. */853 context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator));854 if ((context_notify & 0x1) == 0)855 context_notify |= 0x1;856 else857 context_notify &= ~(0x1);858 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify);859 vpe->context_started = true;860 }861}862 863static void vpe_ring_end_use(struct amdgpu_ring *ring)864{865 struct amdgpu_device *adev = ring->adev;866 867 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);868}869 870static const struct amdgpu_ring_funcs vpe_ring_funcs = {871 .type = AMDGPU_RING_TYPE_VPE,872 .align_mask = 0xf,873 .nop = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0),874 .support_64bit_ptrs = true,875 .get_rptr = vpe_ring_get_rptr,876 .get_wptr = vpe_ring_get_wptr,877 .set_wptr = vpe_ring_set_wptr,878 .emit_frame_size =879 5 + /* vpe_ring_init_cond_exec */880 6 + /* vpe_ring_emit_pipeline_sync */881 10 + 10 + 10 + /* vpe_ring_emit_fence */882 /* vpe_ring_emit_vm_flush */883 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +884 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6,885 .emit_ib_size = 7 + 6,886 .emit_ib = vpe_ring_emit_ib,887 .emit_pipeline_sync = vpe_ring_emit_pipeline_sync,888 .emit_fence = vpe_ring_emit_fence,889 .emit_vm_flush = vpe_ring_emit_vm_flush,890 .emit_wreg = vpe_ring_emit_wreg,891 .emit_reg_wait = vpe_ring_emit_reg_wait,892 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,893 .insert_nop = vpe_ring_insert_nop,894 .pad_ib = amdgpu_ring_generic_pad_ib,895 .test_ring = vpe_ring_test_ring,896 .test_ib = vpe_ring_test_ib,897 .init_cond_exec = vpe_ring_init_cond_exec,898 .preempt_ib = vpe_ring_preempt_ib,899 .begin_use = vpe_ring_begin_use,900 .end_use = vpe_ring_end_use,901};902 903static void vpe_set_ring_funcs(struct amdgpu_device *adev)904{905 adev->vpe.ring.funcs = &vpe_ring_funcs;906}907 908const struct amd_ip_funcs vpe_ip_funcs = {909 .name = "vpe_v6_1",910 .early_init = vpe_early_init,911 .late_init = NULL,912 .sw_init = vpe_sw_init,913 .sw_fini = vpe_sw_fini,914 .hw_init = vpe_hw_init,915 .hw_fini = vpe_hw_fini,916 .suspend = vpe_suspend,917 .resume = vpe_resume,918 .soft_reset = NULL,919 .set_clockgating_state = vpe_set_clockgating_state,920 .set_powergating_state = vpe_set_powergating_state,921};922 923const struct amdgpu_ip_block_version vpe_v6_1_ip_block = {924 .type = AMD_IP_BLOCK_TYPE_VPE,925 .major = 6,926 .minor = 1,927 .rev = 0,928 .funcs = &vpe_ip_funcs,929};930