109 lines · c
1/*2 * Copyright 2022 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22 23#ifndef __AMDGPU_VPE_H__24#define __AMDGPU_VPE_H__25 26#include "amdgpu_ring.h"27#include "amdgpu_irq.h"28#include "vpe_6_1_fw_if.h"29 30#define AMDGPU_MAX_VPE_INSTANCES 231 32struct amdgpu_vpe;33 34struct vpe_funcs {35 uint32_t (*get_reg_offset)(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset);36 int (*set_regs)(struct amdgpu_vpe *vpe);37 int (*irq_init)(struct amdgpu_vpe *vpe);38 int (*init_microcode)(struct amdgpu_vpe *vpe);39 int (*load_microcode)(struct amdgpu_vpe *vpe);40 int (*ring_init)(struct amdgpu_vpe *vpe);41 int (*ring_start)(struct amdgpu_vpe *vpe);42 int (*ring_stop)(struct amdgpu_vpe *vpe);43 int (*ring_fini)(struct amdgpu_vpe *vpe);44};45 46struct vpe_regs {47 uint32_t queue0_rb_rptr_lo;48 uint32_t queue0_rb_rptr_hi;49 uint32_t queue0_rb_wptr_lo;50 uint32_t queue0_rb_wptr_hi;51 uint32_t queue0_preempt;52 53 uint32_t dpm_enable;54 uint32_t dpm_pratio;55 uint32_t dpm_request_interval;56 uint32_t dpm_decision_threshold;57 uint32_t dpm_busy_clamp_threshold;58 uint32_t dpm_idle_clamp_threshold;59 uint32_t dpm_request_lv;60 uint32_t context_indicator;61};62 63struct amdgpu_vpe {64 struct amdgpu_ring ring;65 struct amdgpu_irq_src trap_irq;66 67 const struct vpe_funcs *funcs;68 struct vpe_regs regs;69 70 const struct firmware *fw;71 uint32_t fw_version;72 uint32_t feature_version;73 74 struct amdgpu_bo *cmdbuf_obj;75 uint64_t cmdbuf_gpu_addr;76 uint32_t *cmdbuf_cpu_addr;77 struct delayed_work idle_work;78 bool context_started;79 80 uint32_t num_instances;81 bool collaborate_mode;82};83 84int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev);85int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe);86int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe);87int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe);88int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe);89 90#define vpe_ring_init(vpe) ((vpe)->funcs->ring_init ? (vpe)->funcs->ring_init((vpe)) : 0)91#define vpe_ring_start(vpe) ((vpe)->funcs->ring_start ? (vpe)->funcs->ring_start((vpe)) : 0)92#define vpe_ring_stop(vpe) ((vpe)->funcs->ring_stop ? (vpe)->funcs->ring_stop((vpe)) : 0)93#define vpe_ring_fini(vpe) ((vpe)->funcs->ring_fini ? (vpe)->funcs->ring_fini((vpe)) : 0)94 95#define vpe_get_reg_offset(vpe, inst, offset) \96 ((vpe)->funcs->get_reg_offset ? (vpe)->funcs->get_reg_offset((vpe), (inst), (offset)) : 0)97#define vpe_set_regs(vpe) \98 ((vpe)->funcs->set_regs ? (vpe)->funcs->set_regs((vpe)) : 0)99#define vpe_irq_init(vpe) \100 ((vpe)->funcs->irq_init ? (vpe)->funcs->irq_init((vpe)) : 0)101#define vpe_init_microcode(vpe) \102 ((vpe)->funcs->init_microcode ? (vpe)->funcs->init_microcode((vpe)) : 0)103#define vpe_load_microcode(vpe) \104 ((vpe)->funcs->load_microcode ? (vpe)->funcs->load_microcode((vpe)) : 0)105 106extern const struct amdgpu_ip_block_version vpe_v6_1_ip_block;107 108#endif109