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1/*2 * Copyright 2016 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22#ifndef __AMDGPU_XGMI_H__23#define __AMDGPU_XGMI_H__24 25#include <drm/task_barrier.h>26#include "amdgpu_psp.h"27#include "amdgpu_ras.h"28 29struct amdgpu_hive_info {30 struct kobject kobj;31 uint64_t hive_id;32 struct list_head device_list;33 struct list_head node;34 atomic_t number_devices;35 struct mutex hive_lock;36 int hi_req_count;37 struct amdgpu_device *hi_req_gpu;38 struct task_barrier tb;39 enum {40 AMDGPU_XGMI_PSTATE_MIN,41 AMDGPU_XGMI_PSTATE_MAX_VEGA20,42 AMDGPU_XGMI_PSTATE_UNKNOWN43 } pstate;44 45 struct amdgpu_reset_domain *reset_domain;46 atomic_t ras_recovery;47 struct ras_event_manager event_mgr;48};49 50struct amdgpu_pcs_ras_field {51 const char *err_name;52 uint32_t pcs_err_mask;53 uint32_t pcs_err_shift;54};55 56extern struct amdgpu_xgmi_ras xgmi_ras;57struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);58void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive);59int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);60int amdgpu_xgmi_add_device(struct amdgpu_device *adev);61int amdgpu_xgmi_remove_device(struct amdgpu_device *adev);62int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);63int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,64 struct amdgpu_device *peer_adev);65int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,66 struct amdgpu_device *peer_adev);67uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,68 uint64_t addr);69static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,70 struct amdgpu_device *bo_adev)71{72 return (amdgpu_use_xgmi_p2p &&73 adev != bo_adev &&74 adev->gmc.xgmi.hive_id &&75 adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id);76}77int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev);78 79#endif80