609 lines · c
1/*2 * Copyright 2012 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: Alex Deucher23 */24#ifndef CIK_H25#define CIK_H26 27#define MC_SEQ_MISC0__MT__MASK 0xf000000028#define MC_SEQ_MISC0__MT__GDDR1 0x1000000029#define MC_SEQ_MISC0__MT__DDR2 0x2000000030#define MC_SEQ_MISC0__MT__GDDR3 0x3000000031#define MC_SEQ_MISC0__MT__GDDR4 0x4000000032#define MC_SEQ_MISC0__MT__GDDR5 0x5000000033#define MC_SEQ_MISC0__MT__HBM 0x6000000034#define MC_SEQ_MISC0__MT__DDR3 0xB000000035 36#define CP_ME_TABLE_SIZE 9637 38/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */39#define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c)40#define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c)41#define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c)42#define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c)43#define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c)44#define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c)45 46/* hpd instance offsets */47#define HPD0_REGISTER_OFFSET (0x1807 - 0x1807)48#define HPD1_REGISTER_OFFSET (0x180a - 0x1807)49#define HPD2_REGISTER_OFFSET (0x180d - 0x1807)50#define HPD3_REGISTER_OFFSET (0x1810 - 0x1807)51#define HPD4_REGISTER_OFFSET (0x1813 - 0x1807)52#define HPD5_REGISTER_OFFSET (0x1816 - 0x1807)53 54#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x1201000155#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x1201100356 57#define PIPEID(x) ((x) << 0)58#define MEID(x) ((x) << 2)59#define VMID(x) ((x) << 4)60#define QUEUEID(x) ((x) << 8)61 62#define mmCC_DRM_ID_STRAPS 0x155963#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf000000064 65#define mmCHUB_CONTROL 0x61966#define BYPASS_VM (1 << 0)67 68#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)69 70#define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a0271#define LUT_10BIT_BYPASS_EN (1 << 8)72 73# define CURSOR_MONO 074# define CURSOR_24_1 175# define CURSOR_24_8_PRE_MULT 276# define CURSOR_24_8_UNPRE_MULT 377# define CURSOR_URGENT_ALWAYS 078# define CURSOR_URGENT_1_8 179# define CURSOR_URGENT_1_4 280# define CURSOR_URGENT_3_8 381# define CURSOR_URGENT_1_2 482 83# define GRPH_DEPTH_8BPP 084# define GRPH_DEPTH_16BPP 185# define GRPH_DEPTH_32BPP 286/* 8 BPP */87# define GRPH_FORMAT_INDEXED 088/* 16 BPP */89# define GRPH_FORMAT_ARGB1555 090# define GRPH_FORMAT_ARGB565 191# define GRPH_FORMAT_ARGB4444 292# define GRPH_FORMAT_AI88 393# define GRPH_FORMAT_MONO16 494# define GRPH_FORMAT_BGRA5551 595/* 32 BPP */96# define GRPH_FORMAT_ARGB8888 097# define GRPH_FORMAT_ARGB2101010 198# define GRPH_FORMAT_32BPP_DIG 299# define GRPH_FORMAT_8B_ARGB2101010 3100# define GRPH_FORMAT_BGRA1010102 4101# define GRPH_FORMAT_8B_BGRA1010102 5102# define GRPH_FORMAT_RGB111110 6103# define GRPH_FORMAT_BGR101111 7104# define ADDR_SURF_MACRO_TILE_ASPECT_1 0105# define ADDR_SURF_MACRO_TILE_ASPECT_2 1106# define ADDR_SURF_MACRO_TILE_ASPECT_4 2107# define ADDR_SURF_MACRO_TILE_ASPECT_8 3108# define GRPH_ARRAY_LINEAR_GENERAL 0109# define GRPH_ARRAY_LINEAR_ALIGNED 1110# define GRPH_ARRAY_1D_TILED_THIN1 2111# define GRPH_ARRAY_2D_TILED_THIN1 4112# define DISPLAY_MICRO_TILING 0113# define THIN_MICRO_TILING 1114# define DEPTH_MICRO_TILING 2115# define ROTATED_MICRO_TILING 4116# define GRPH_ENDIAN_NONE 0117# define GRPH_ENDIAN_8IN16 1118# define GRPH_ENDIAN_8IN32 2119# define GRPH_ENDIAN_8IN64 3120# define GRPH_RED_SEL_R 0121# define GRPH_RED_SEL_G 1122# define GRPH_RED_SEL_B 2123# define GRPH_RED_SEL_A 3124# define GRPH_GREEN_SEL_G 0125# define GRPH_GREEN_SEL_B 1126# define GRPH_GREEN_SEL_A 2127# define GRPH_GREEN_SEL_R 3128# define GRPH_BLUE_SEL_B 0129# define GRPH_BLUE_SEL_A 1130# define GRPH_BLUE_SEL_R 2131# define GRPH_BLUE_SEL_G 3132# define GRPH_ALPHA_SEL_A 0133# define GRPH_ALPHA_SEL_R 1134# define GRPH_ALPHA_SEL_G 2135# define GRPH_ALPHA_SEL_B 3136# define INPUT_GAMMA_USE_LUT 0137# define INPUT_GAMMA_BYPASS 1138# define INPUT_GAMMA_SRGB_24 2139# define INPUT_GAMMA_XVYCC_222 3140 141# define INPUT_CSC_BYPASS 0142# define INPUT_CSC_PROG_COEFF 1143# define INPUT_CSC_PROG_SHARED_MATRIXA 2144 145# define OUTPUT_CSC_BYPASS 0146# define OUTPUT_CSC_TV_RGB 1147# define OUTPUT_CSC_YCBCR_601 2148# define OUTPUT_CSC_YCBCR_709 3149# define OUTPUT_CSC_PROG_COEFF 4150# define OUTPUT_CSC_PROG_SHARED_MATRIXB 5151 152# define DEGAMMA_BYPASS 0153# define DEGAMMA_SRGB_24 1154# define DEGAMMA_XVYCC_222 2155# define GAMUT_REMAP_BYPASS 0156# define GAMUT_REMAP_PROG_COEFF 1157# define GAMUT_REMAP_PROG_SHARED_MATRIXA 2158# define GAMUT_REMAP_PROG_SHARED_MATRIXB 3159 160# define REGAMMA_BYPASS 0161# define REGAMMA_SRGB_24 1162# define REGAMMA_XVYCC_222 2163# define REGAMMA_PROG_A 3164# define REGAMMA_PROG_B 4165 166# define FMT_CLAMP_6BPC 0167# define FMT_CLAMP_8BPC 1168# define FMT_CLAMP_10BPC 2169 170# define HDMI_24BIT_DEEP_COLOR 0171# define HDMI_30BIT_DEEP_COLOR 1172# define HDMI_36BIT_DEEP_COLOR 2173# define HDMI_ACR_HW 0174# define HDMI_ACR_32 1175# define HDMI_ACR_44 2176# define HDMI_ACR_48 3177# define HDMI_ACR_X1 1178# define HDMI_ACR_X2 2179# define HDMI_ACR_X4 4180# define AFMT_AVI_INFO_Y_RGB 0181# define AFMT_AVI_INFO_Y_YCBCR422 1182# define AFMT_AVI_INFO_Y_YCBCR444 2183 184#define NO_AUTO 0185#define ES_AUTO 1186#define GS_AUTO 2187#define ES_AND_GS_AUTO 3188 189# define ARRAY_MODE(x) ((x) << 2)190# define PIPE_CONFIG(x) ((x) << 6)191# define TILE_SPLIT(x) ((x) << 11)192# define MICRO_TILE_MODE_NEW(x) ((x) << 22)193# define SAMPLE_SPLIT(x) ((x) << 25)194# define BANK_WIDTH(x) ((x) << 0)195# define BANK_HEIGHT(x) ((x) << 2)196# define MACRO_TILE_ASPECT(x) ((x) << 4)197# define NUM_BANKS(x) ((x) << 6)198 199#define MSG_ENTER_RLC_SAFE_MODE 1200#define MSG_EXIT_RLC_SAFE_MODE 0201 202/*203 * PM4204 */205#define PACKET_TYPE0 0206#define PACKET_TYPE1 1207#define PACKET_TYPE2 2208#define PACKET_TYPE3 3209 210#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)211#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)212#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)213#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)214#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \215 ((reg) & 0xFFFF) | \216 ((n) & 0x3FFF) << 16)217#define CP_PACKET2 0x80000000218#define PACKET2_PAD_SHIFT 0219#define PACKET2_PAD_MASK (0x3fffffff << 0)220 221#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))222 223#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \224 (((op) & 0xFF) << 8) | \225 ((n) & 0x3FFF) << 16)226 227#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)228 229/* Packet 3 types */230#define PACKET3_NOP 0x10231#define PACKET3_SET_BASE 0x11232#define PACKET3_BASE_INDEX(x) ((x) << 0)233#define CE_PARTITION_BASE 3234#define PACKET3_CLEAR_STATE 0x12235#define PACKET3_INDEX_BUFFER_SIZE 0x13236#define PACKET3_DISPATCH_DIRECT 0x15237#define PACKET3_DISPATCH_INDIRECT 0x16238#define PACKET3_ATOMIC_GDS 0x1D239#define PACKET3_ATOMIC_MEM 0x1E240#define PACKET3_OCCLUSION_QUERY 0x1F241#define PACKET3_SET_PREDICATION 0x20242#define PACKET3_REG_RMW 0x21243#define PACKET3_COND_EXEC 0x22244#define PACKET3_PRED_EXEC 0x23245#define PACKET3_DRAW_INDIRECT 0x24246#define PACKET3_DRAW_INDEX_INDIRECT 0x25247#define PACKET3_INDEX_BASE 0x26248#define PACKET3_DRAW_INDEX_2 0x27249#define PACKET3_CONTEXT_CONTROL 0x28250#define PACKET3_INDEX_TYPE 0x2A251#define PACKET3_DRAW_INDIRECT_MULTI 0x2C252#define PACKET3_DRAW_INDEX_AUTO 0x2D253#define PACKET3_NUM_INSTANCES 0x2F254#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30255#define PACKET3_INDIRECT_BUFFER_CONST 0x33256#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34257#define PACKET3_DRAW_INDEX_OFFSET_2 0x35258#define PACKET3_DRAW_PREAMBLE 0x36259#define PACKET3_WRITE_DATA 0x37260#define WRITE_DATA_DST_SEL(x) ((x) << 8)261 /* 0 - register262 * 1 - memory (sync - via GRBM)263 * 2 - gl2264 * 3 - gds265 * 4 - reserved266 * 5 - memory (async - direct)267 */268#define WR_ONE_ADDR (1 << 16)269#define WR_CONFIRM (1 << 20)270#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)271 /* 0 - LRU272 * 1 - Stream273 */274#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)275 /* 0 - me276 * 1 - pfp277 * 2 - ce278 */279#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38280#define PACKET3_MEM_SEMAPHORE 0x39281# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)282# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */283# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */284# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)285# define PACKET3_SEM_SEL_WAIT (0x7 << 29)286#define PACKET3_COPY_DW 0x3B287#define PACKET3_WAIT_REG_MEM 0x3C288#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)289 /* 0 - always290 * 1 - <291 * 2 - <=292 * 3 - ==293 * 4 - !=294 * 5 - >=295 * 6 - >296 */297#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)298 /* 0 - reg299 * 1 - mem300 */301#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)302 /* 0 - wait_reg_mem303 * 1 - wr_wait_wr_reg304 */305#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)306 /* 0 - me307 * 1 - pfp308 */309#define PACKET3_INDIRECT_BUFFER 0x3F310#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)311#define INDIRECT_BUFFER_VALID (1 << 23)312#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)313 /* 0 - LRU314 * 1 - Stream315 * 2 - Bypass316 */317#define PACKET3_COPY_DATA 0x40318#define PACKET3_PFP_SYNC_ME 0x42319#define PACKET3_SURFACE_SYNC 0x43320# define PACKET3_DEST_BASE_0_ENA (1 << 0)321# define PACKET3_DEST_BASE_1_ENA (1 << 1)322# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)323# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)324# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)325# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)326# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)327# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)328# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)329# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)330# define PACKET3_DB_DEST_BASE_ENA (1 << 14)331# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)332# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */333# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */334# define PACKET3_DEST_BASE_2_ENA (1 << 19)335# define PACKET3_DEST_BASE_3_ENA (1 << 21)336# define PACKET3_TCL1_ACTION_ENA (1 << 22)337# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */338# define PACKET3_CB_ACTION_ENA (1 << 25)339# define PACKET3_DB_ACTION_ENA (1 << 26)340# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)341# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)342# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)343#define PACKET3_COND_WRITE 0x45344#define PACKET3_EVENT_WRITE 0x46345#define EVENT_TYPE(x) ((x) << 0)346#define EVENT_INDEX(x) ((x) << 8)347 /* 0 - any non-TS event348 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*349 * 2 - SAMPLE_PIPELINESTAT350 * 3 - SAMPLE_STREAMOUTSTAT*351 * 4 - *S_PARTIAL_FLUSH352 * 5 - EOP events353 * 6 - EOS events354 */355#define PACKET3_EVENT_WRITE_EOP 0x47356#define EOP_TCL1_VOL_ACTION_EN (1 << 12)357#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */358#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */359#define EOP_TCL1_ACTION_EN (1 << 16)360#define EOP_TC_ACTION_EN (1 << 17) /* L2 */361#define EOP_TCL2_VOLATILE (1 << 24)362#define EOP_CACHE_POLICY(x) ((x) << 25)363 /* 0 - LRU364 * 1 - Stream365 * 2 - Bypass366 */367#define EOP_EXEC (1 << 28) /* For Trailing Fence */368#define DATA_SEL(x) ((x) << 29)369 /* 0 - discard370 * 1 - send low 32bit data371 * 2 - send 64bit data372 * 3 - send 64bit GPU counter value373 * 4 - send 64bit sys counter value374 */375#define INT_SEL(x) ((x) << 24)376 /* 0 - none377 * 1 - interrupt only (DATA_SEL = 0)378 * 2 - interrupt when data write is confirmed379 */380#define DST_SEL(x) ((x) << 16)381 /* 0 - MC382 * 1 - TC/L2383 */384#define PACKET3_EVENT_WRITE_EOS 0x48385#define PACKET3_RELEASE_MEM 0x49386#define PACKET3_PREAMBLE_CNTL 0x4A387# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)388# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)389#define PACKET3_DMA_DATA 0x50390/* 1. header391 * 2. CONTROL392 * 3. SRC_ADDR_LO or DATA [31:0]393 * 4. SRC_ADDR_HI [31:0]394 * 5. DST_ADDR_LO [31:0]395 * 6. DST_ADDR_HI [7:0]396 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]397 */398/* CONTROL */399# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)400 /* 0 - ME401 * 1 - PFP402 */403# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)404 /* 0 - LRU405 * 1 - Stream406 * 2 - Bypass407 */408# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)409# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)410 /* 0 - DST_ADDR using DAS411 * 1 - GDS412 * 3 - DST_ADDR using L2413 */414# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)415 /* 0 - LRU416 * 1 - Stream417 * 2 - Bypass418 */419# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)420# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)421 /* 0 - SRC_ADDR using SAS422 * 1 - GDS423 * 2 - DATA424 * 3 - SRC_ADDR using L2425 */426# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)427/* COMMAND */428# define PACKET3_DMA_DATA_DIS_WC (1 << 21)429# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)430 /* 0 - none431 * 1 - 8 in 16432 * 2 - 8 in 32433 * 3 - 8 in 64434 */435# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)436 /* 0 - none437 * 1 - 8 in 16438 * 2 - 8 in 32439 * 3 - 8 in 64440 */441# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)442 /* 0 - memory443 * 1 - register444 */445# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)446 /* 0 - memory447 * 1 - register448 */449# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)450# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)451# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)452#define PACKET3_ACQUIRE_MEM 0x58453#define PACKET3_REWIND 0x59454#define PACKET3_LOAD_UCONFIG_REG 0x5E455#define PACKET3_LOAD_SH_REG 0x5F456#define PACKET3_LOAD_CONFIG_REG 0x60457#define PACKET3_LOAD_CONTEXT_REG 0x61458#define PACKET3_SET_CONFIG_REG 0x68459#define PACKET3_SET_CONFIG_REG_START 0x00002000460#define PACKET3_SET_CONFIG_REG_END 0x00002c00461#define PACKET3_SET_CONTEXT_REG 0x69462#define PACKET3_SET_CONTEXT_REG_START 0x0000a000463#define PACKET3_SET_CONTEXT_REG_END 0x0000a400464#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73465#define PACKET3_SET_SH_REG 0x76466#define PACKET3_SET_SH_REG_START 0x00002c00467#define PACKET3_SET_SH_REG_END 0x00003000468#define PACKET3_SET_SH_REG_OFFSET 0x77469#define PACKET3_SET_QUEUE_REG 0x78470#define PACKET3_SET_UCONFIG_REG 0x79471#define PACKET3_SET_UCONFIG_REG_START 0x0000c000472#define PACKET3_SET_UCONFIG_REG_END 0x0000c400473#define PACKET3_SCRATCH_RAM_WRITE 0x7D474#define PACKET3_SCRATCH_RAM_READ 0x7E475#define PACKET3_LOAD_CONST_RAM 0x80476#define PACKET3_WRITE_CONST_RAM 0x81477#define PACKET3_DUMP_CONST_RAM 0x83478#define PACKET3_INCREMENT_CE_COUNTER 0x84479#define PACKET3_INCREMENT_DE_COUNTER 0x85480#define PACKET3_WAIT_ON_CE_COUNTER 0x86481#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88482#define PACKET3_SWITCH_BUFFER 0x8B483 484/* SDMA - first instance at 0xd000, second at 0xd800 */485#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */486#define SDMA1_REGISTER_OFFSET 0x200 /* not a register */487#define SDMA_MAX_INSTANCE 2488 489#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \490 (((sub_op) & 0xFF) << 8) | \491 (((op) & 0xFF) << 0))492/* sDMA opcodes */493#define SDMA_OPCODE_NOP 0494# define SDMA_NOP_COUNT(x) (((x) & 0x3FFF) << 16)495#define SDMA_OPCODE_COPY 1496# define SDMA_COPY_SUB_OPCODE_LINEAR 0497# define SDMA_COPY_SUB_OPCODE_TILED 1498# define SDMA_COPY_SUB_OPCODE_SOA 3499# define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4500# define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5501# define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6502#define SDMA_OPCODE_WRITE 2503# define SDMA_WRITE_SUB_OPCODE_LINEAR 0504# define SDMA_WRITE_SUB_OPCODE_TILED 1505#define SDMA_OPCODE_INDIRECT_BUFFER 4506#define SDMA_OPCODE_FENCE 5507#define SDMA_OPCODE_TRAP 6508#define SDMA_OPCODE_SEMAPHORE 7509# define SDMA_SEMAPHORE_EXTRA_O (1 << 13)510 /* 0 - increment511 * 1 - write 1512 */513# define SDMA_SEMAPHORE_EXTRA_S (1 << 14)514 /* 0 - wait515 * 1 - signal516 */517# define SDMA_SEMAPHORE_EXTRA_M (1 << 15)518 /* mailbox */519#define SDMA_OPCODE_POLL_REG_MEM 8520# define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10)521 /* 0 - wait_reg_mem522 * 1 - wr_wait_wr_reg523 */524# define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12)525 /* 0 - always526 * 1 - <527 * 2 - <=528 * 3 - ==529 * 4 - !=530 * 5 - >=531 * 6 - >532 */533# define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)534 /* 0 = register535 * 1 = memory536 */537#define SDMA_OPCODE_COND_EXEC 9538#define SDMA_OPCODE_CONSTANT_FILL 11539# define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14)540 /* 0 = byte fill541 * 2 = DW fill542 */543#define SDMA_OPCODE_GENERATE_PTE_PDE 12544#define SDMA_OPCODE_TIMESTAMP 13545# define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0546# define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1547# define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2548#define SDMA_OPCODE_SRBM_WRITE 14549# define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12)550 /* byte mask */551 552#define VCE_CMD_NO_OP 0x00000000553#define VCE_CMD_END 0x00000001554#define VCE_CMD_IB 0x00000002555#define VCE_CMD_FENCE 0x00000003556#define VCE_CMD_TRAP 0x00000004557#define VCE_CMD_IB_AUTO 0x00000005558#define VCE_CMD_SEMAPHORE 0x00000006559 560/* if PTR32, these are the bases for scratch and lds */561#define PRIVATE_BASE(x) ((x) << 0) /* scratch */562#define SHARED_BASE(x) ((x) << 16) /* LDS */563 564#define KFD_CIK_SDMA_QUEUE_OFFSET (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL)565 566/* valid for both DEFAULT_MTYPE and APE1_MTYPE */567enum {568 MTYPE_CACHED = 0,569 MTYPE_NONCACHED = 3570};571 572/* mmPA_SC_RASTER_CONFIG mask */573#define RB_MAP_PKR0(x) ((x) << 0)574#define RB_MAP_PKR0_MASK (0x3 << 0)575#define RB_MAP_PKR1(x) ((x) << 2)576#define RB_MAP_PKR1_MASK (0x3 << 2)577#define RB_XSEL2(x) ((x) << 4)578#define RB_XSEL2_MASK (0x3 << 4)579#define RB_XSEL (1 << 6)580#define RB_YSEL (1 << 7)581#define PKR_MAP(x) ((x) << 8)582#define PKR_MAP_MASK (0x3 << 8)583#define PKR_XSEL(x) ((x) << 10)584#define PKR_XSEL_MASK (0x3 << 10)585#define PKR_YSEL(x) ((x) << 12)586#define PKR_YSEL_MASK (0x3 << 12)587#define SC_MAP(x) ((x) << 16)588#define SC_MAP_MASK (0x3 << 16)589#define SC_XSEL(x) ((x) << 18)590#define SC_XSEL_MASK (0x3 << 18)591#define SC_YSEL(x) ((x) << 20)592#define SC_YSEL_MASK (0x3 << 20)593#define SE_MAP(x) ((x) << 24)594#define SE_MAP_MASK (0x3 << 24)595#define SE_XSEL(x) ((x) << 26)596#define SE_XSEL_MASK (0x3 << 26)597#define SE_YSEL(x) ((x) << 28)598#define SE_YSEL_MASK (0x3 << 28)599 600/* mmPA_SC_RASTER_CONFIG_1 mask */601#define SE_PAIR_MAP(x) ((x) << 0)602#define SE_PAIR_MAP_MASK (0x3 << 0)603#define SE_PAIR_XSEL(x) ((x) << 2)604#define SE_PAIR_XSEL_MASK (0x3 << 2)605#define SE_PAIR_YSEL(x) ((x) << 4)606#define SE_PAIR_YSEL_MASK (0x3 << 4)607 608#endif609