10135 lines · c
1/*2 * Copyright 2019 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include <linux/delay.h>25#include <linux/kernel.h>26#include <linux/firmware.h>27#include <linux/module.h>28#include <linux/pci.h>29#include "amdgpu.h"30#include "amdgpu_gfx.h"31#include "amdgpu_psp.h"32#include "nv.h"33#include "nvd.h"34 35#include "gc/gc_10_1_0_offset.h"36#include "gc/gc_10_1_0_sh_mask.h"37#include "smuio/smuio_11_0_0_offset.h"38#include "smuio/smuio_11_0_0_sh_mask.h"39#include "navi10_enum.h"40#include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"41 42#include "soc15.h"43#include "soc15d.h"44#include "soc15_common.h"45#include "clearstate_gfx10.h"46#include "v10_structs.h"47#include "gfx_v10_0.h"48#include "nbio_v2_3.h"49 50/*51 * Navi10 has two graphic rings to share each graphic pipe.52 * 1. Primary ring53 * 2. Async ring54 */55#define GFX10_NUM_GFX_RINGS_NV1X 156#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 257#define GFX10_MEC_HPD_SIZE 204858 59#define F32_CE_PROGRAM_RAM_SIZE 6553660#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L61 62#define mmCGTT_GS_NGG_CLK_CTRL 0x508763#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 164#define mmCGTT_SPI_RA0_CLK_CTRL 0x507a65#define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 166#define mmCGTT_SPI_RA1_CLK_CTRL 0x507b67#define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 168 69#define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x870#define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L71 72#define mmCGTS_TCC_DISABLE_gc_10_3 0x500673#define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 174#define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x500775#define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 176 77#define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f5578#define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 079#define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca080#define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 181#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca182#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 183#define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec84#define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 085#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc186#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 087#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc288#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 089#define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc390#define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 091#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc492#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 093#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc594#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 095#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc696#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 097#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a98#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L99#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL100#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2101#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL102#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580103#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0104 105#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105106#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1107#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106108#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1109 110#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025111#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1112#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026113#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1114 115#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d116#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1117#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e118#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1119 120#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441121#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1122#define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261123#define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1124#define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f125#define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1126#define mmVGT_TF_RING_SIZE_Vangogh 0x224e127#define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1128#define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241129#define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1130#define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250131#define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1132#define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240133#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1134#define mmSPI_CONFIG_CNTL_Vangogh 0x2440135#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1136#define mmGCR_GENERAL_CNTL_Vangogh 0x1580137#define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0138#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL139 140#define mmCP_HYP_PFP_UCODE_ADDR 0x5814141#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1142#define mmCP_HYP_PFP_UCODE_DATA 0x5815143#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1144#define mmCP_HYP_CE_UCODE_ADDR 0x5818145#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1146#define mmCP_HYP_CE_UCODE_DATA 0x5819147#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1148#define mmCP_HYP_ME_UCODE_ADDR 0x5816149#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1150#define mmCP_HYP_ME_UCODE_DATA 0x5817151#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1152 153#define mmCPG_PSP_DEBUG 0x5c10154#define mmCPG_PSP_DEBUG_BASE_IDX 1155#define mmCPC_PSP_DEBUG 0x5c11156#define mmCPC_PSP_DEBUG_BASE_IDX 1157#define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L158#define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L159 160//CC_GC_SA_UNIT_DISABLE161#define mmCC_GC_SA_UNIT_DISABLE 0x0fe9162#define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0163#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8164#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L165//GC_USER_SA_UNIT_DISABLE166#define mmGC_USER_SA_UNIT_DISABLE 0x0fea167#define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0168#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8169#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L170//PA_SC_ENHANCE_3171#define mmPA_SC_ENHANCE_3 0x1085172#define mmPA_SC_ENHANCE_3_BASE_IDX 0173#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3174#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L175 176#define mmCGTT_SPI_CS_CLK_CTRL 0x507c177#define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1178 179#define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3180#define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0181#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db182#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0183 184#define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030185#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0186 187#define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5188#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1189 190MODULE_FIRMWARE("amdgpu/navi10_ce.bin");191MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");192MODULE_FIRMWARE("amdgpu/navi10_me.bin");193MODULE_FIRMWARE("amdgpu/navi10_mec.bin");194MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");195MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");196 197MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");198MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");199MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");200MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");201MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");202MODULE_FIRMWARE("amdgpu/navi14_ce.bin");203MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");204MODULE_FIRMWARE("amdgpu/navi14_me.bin");205MODULE_FIRMWARE("amdgpu/navi14_mec.bin");206MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");207MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");208 209MODULE_FIRMWARE("amdgpu/navi12_ce.bin");210MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");211MODULE_FIRMWARE("amdgpu/navi12_me.bin");212MODULE_FIRMWARE("amdgpu/navi12_mec.bin");213MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");214MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");215 216MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");217MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");218MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");219MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");220MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");221MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");222 223MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");224MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");225MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");226MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");227MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");228MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");229 230MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");231MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");232MODULE_FIRMWARE("amdgpu/vangogh_me.bin");233MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");234MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");235MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");236 237MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");238MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");239MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");240MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");241MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");242MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");243 244MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");245MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");246MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");247MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");248MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");249MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");250 251MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");252MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");253MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");254MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");255MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");256MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");257 258MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");259MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");260MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");261MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");262MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");263MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");264 265MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");266MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");267MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");268MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");269MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");270MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");271 272MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");273MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");274MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");275MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");276MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");277MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");278 279static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),323 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),324 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),326 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),328 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),330 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),331 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),332 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),333 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),335 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),336 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),358 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),359 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),370 /* cp header registers */371 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),372 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),373 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),374 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),375 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),376 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),377 /* SE status registers */378 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),379 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),380 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),381 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)382};383 384static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {385 /* compute registers */386 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),387 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),388 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),389 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),390 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),391 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),392 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),393 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),394 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),395 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),396 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),397 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),398 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),399 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),400 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),401 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),402 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),403 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),404 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),405 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),406 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),407 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),408 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),409 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),410 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),411 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),412 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),413 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),414 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),415 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),416 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),417 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),418 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),419 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),420 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),421 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),422 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),423 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),424 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)425};426 427static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {428 /* gfx queue registers */429 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),430 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),431 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),432 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),433 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),434 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),435 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),436 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),437 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),438 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),439 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),440 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),441 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),442 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),443 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),444 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),445 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),446 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),447 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),448 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),449 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),450 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),451 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)452};453 454static const struct soc15_reg_golden golden_settings_gc_10_1[] = {455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)495};496 497static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {498 /* Pending on emulation bring up */499};500 501static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)1554};1555 1556static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),1595};1596 1597static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)1640};1641 1642static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {1643 /* Pending on emulation bring up */1644};1645 1646static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)2267};2268 2269static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {2270 /* Pending on emulation bring up */2271};2272 2273static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)3326};3327 3328static const struct soc15_reg_golden golden_settings_gc_10_3[] = {3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)3372};3373 3374static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {3375 /* Pending on emulation bring up */3376};3377 3378static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),3420 3421 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),3423};3424 3425static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),3450 3451 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),3453};3454 3455static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)3476};3477 3478static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {3479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),3480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),3482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),3483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),3484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),3505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),3506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),3507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020)3515};3516 3517static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),3544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),3545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),3546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)3550};3551 3552static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),3558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),3559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),3560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),3561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),3562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),3563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),3564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),3565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),3566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),3567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),3568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),3569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),3570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),3571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),3572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),3573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),3574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),3575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),3576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),3577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),3578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),3579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),3580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),3581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),3582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),3583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),3584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),3585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),3586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)3587};3588 3589static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {3590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),3591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),3592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),3593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),3594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),3595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),3596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),3597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),3598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),3599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),3600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),3601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),3602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),3603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),3604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),3605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),3606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),3607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),3608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),3609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),3610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),3611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)3612};3613 3614static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {3615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),3616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),3617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),3618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),3619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),3620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),3621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),3622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),3623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),3624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),3625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),3626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),3627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),3628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),3629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),3630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),3631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),3632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),3633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),3634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),3635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),3636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)3637};3638 3639#define DEFAULT_SH_MEM_CONFIG \3640 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \3641 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \3642 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \3643 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))3644 3645/* TODO: pending on golden setting value of gb address config */3646#define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x001000443647 3648static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);3649static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);3650static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);3651static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);3652static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);3653static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,3654 struct amdgpu_cu_info *cu_info);3655static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);3656static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,3657 u32 sh_num, u32 instance, int xcc_id);3658static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);3659 3660static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);3661static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);3662static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);3663static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);3664static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);3665static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);3666static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);3667static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);3668static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);3669static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);3670static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,3671 uint16_t pasid, uint32_t flush_type,3672 bool all_hub, uint8_t dst_sel);3673static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,3674 unsigned int vmid);3675 3676static int gfx_v10_0_set_powergating_state(void *handle,3677 enum amd_powergating_state state);3678static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)3679{3680 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));3681 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |3682 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */3683 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */3684 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */3685 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */3686 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */3687 amdgpu_ring_write(kiq_ring, 0); /* oac mask */3688 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */3689}3690 3691static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,3692 struct amdgpu_ring *ring)3693{3694 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);3695 uint64_t wptr_addr = ring->wptr_gpu_addr;3696 uint32_t eng_sel = 0;3697 3698 switch (ring->funcs->type) {3699 case AMDGPU_RING_TYPE_COMPUTE:3700 eng_sel = 0;3701 break;3702 case AMDGPU_RING_TYPE_GFX:3703 eng_sel = 4;3704 break;3705 case AMDGPU_RING_TYPE_MES:3706 eng_sel = 5;3707 break;3708 default:3709 WARN_ON(1);3710 }3711 3712 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));3713 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/3714 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */3715 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */3716 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */3717 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |3718 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |3719 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |3720 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */3721 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */3722 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |3723 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */3724 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));3725 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));3726 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));3727 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));3728 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));3729}3730 3731static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,3732 struct amdgpu_ring *ring,3733 enum amdgpu_unmap_queues_action action,3734 u64 gpu_addr, u64 seq)3735{3736 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;3737 3738 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));3739 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */3740 PACKET3_UNMAP_QUEUES_ACTION(action) |3741 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |3742 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |3743 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));3744 amdgpu_ring_write(kiq_ring,3745 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));3746 3747 if (action == PREEMPT_QUEUES_NO_UNMAP) {3748 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));3749 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));3750 amdgpu_ring_write(kiq_ring, seq);3751 } else {3752 amdgpu_ring_write(kiq_ring, 0);3753 amdgpu_ring_write(kiq_ring, 0);3754 amdgpu_ring_write(kiq_ring, 0);3755 }3756}3757 3758static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,3759 struct amdgpu_ring *ring,3760 u64 addr,3761 u64 seq)3762{3763 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;3764 3765 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));3766 amdgpu_ring_write(kiq_ring,3767 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |3768 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |3769 PACKET3_QUERY_STATUS_COMMAND(2));3770 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */3771 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |3772 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));3773 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));3774 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));3775 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));3776 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));3777}3778 3779static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,3780 uint16_t pasid, uint32_t flush_type,3781 bool all_hub)3782{3783 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);3784}3785 3786static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {3787 .kiq_set_resources = gfx10_kiq_set_resources,3788 .kiq_map_queues = gfx10_kiq_map_queues,3789 .kiq_unmap_queues = gfx10_kiq_unmap_queues,3790 .kiq_query_status = gfx10_kiq_query_status,3791 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,3792 .set_resources_size = 8,3793 .map_queues_size = 7,3794 .unmap_queues_size = 6,3795 .query_status_size = 7,3796 .invalidate_tlbs_size = 2,3797};3798 3799static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)3800{3801 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;3802}3803 3804static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)3805{3806 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {3807 case IP_VERSION(10, 1, 10):3808 soc15_program_register_sequence(adev,3809 golden_settings_gc_rlc_spm_10_0_nv10,3810 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));3811 break;3812 case IP_VERSION(10, 1, 1):3813 soc15_program_register_sequence(adev,3814 golden_settings_gc_rlc_spm_10_1_nv14,3815 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));3816 break;3817 case IP_VERSION(10, 1, 2):3818 soc15_program_register_sequence(adev,3819 golden_settings_gc_rlc_spm_10_1_2_nv12,3820 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));3821 break;3822 default:3823 break;3824 }3825}3826 3827static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)3828{3829 if (amdgpu_sriov_vf(adev))3830 return;3831 3832 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {3833 case IP_VERSION(10, 1, 10):3834 soc15_program_register_sequence(adev,3835 golden_settings_gc_10_1,3836 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));3837 soc15_program_register_sequence(adev,3838 golden_settings_gc_10_0_nv10,3839 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));3840 break;3841 case IP_VERSION(10, 1, 1):3842 soc15_program_register_sequence(adev,3843 golden_settings_gc_10_1_1,3844 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));3845 soc15_program_register_sequence(adev,3846 golden_settings_gc_10_1_nv14,3847 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));3848 break;3849 case IP_VERSION(10, 1, 2):3850 soc15_program_register_sequence(adev,3851 golden_settings_gc_10_1_2,3852 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));3853 soc15_program_register_sequence(adev,3854 golden_settings_gc_10_1_2_nv12,3855 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));3856 break;3857 case IP_VERSION(10, 3, 0):3858 soc15_program_register_sequence(adev,3859 golden_settings_gc_10_3,3860 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));3861 soc15_program_register_sequence(adev,3862 golden_settings_gc_10_3_sienna_cichlid,3863 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));3864 break;3865 case IP_VERSION(10, 3, 2):3866 soc15_program_register_sequence(adev,3867 golden_settings_gc_10_3_2,3868 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));3869 break;3870 case IP_VERSION(10, 3, 1):3871 soc15_program_register_sequence(adev,3872 golden_settings_gc_10_3_vangogh,3873 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));3874 break;3875 case IP_VERSION(10, 3, 3):3876 soc15_program_register_sequence(adev,3877 golden_settings_gc_10_3_3,3878 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));3879 break;3880 case IP_VERSION(10, 3, 4):3881 soc15_program_register_sequence(adev,3882 golden_settings_gc_10_3_4,3883 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));3884 break;3885 case IP_VERSION(10, 3, 5):3886 soc15_program_register_sequence(adev,3887 golden_settings_gc_10_3_5,3888 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));3889 break;3890 case IP_VERSION(10, 1, 3):3891 case IP_VERSION(10, 1, 4):3892 soc15_program_register_sequence(adev,3893 golden_settings_gc_10_0_cyan_skillfish,3894 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));3895 break;3896 case IP_VERSION(10, 3, 6):3897 soc15_program_register_sequence(adev,3898 golden_settings_gc_10_3_6,3899 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));3900 break;3901 case IP_VERSION(10, 3, 7):3902 soc15_program_register_sequence(adev,3903 golden_settings_gc_10_3_7,3904 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));3905 break;3906 default:3907 break;3908 }3909 gfx_v10_0_init_spm_golden_registers(adev);3910}3911 3912static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,3913 bool wc, uint32_t reg, uint32_t val)3914{3915 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));3916 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |3917 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));3918 amdgpu_ring_write(ring, reg);3919 amdgpu_ring_write(ring, 0);3920 amdgpu_ring_write(ring, val);3921}3922 3923static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,3924 int mem_space, int opt, uint32_t addr0,3925 uint32_t addr1, uint32_t ref, uint32_t mask,3926 uint32_t inv)3927{3928 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));3929 amdgpu_ring_write(ring,3930 /* memory (1) or register (0) */3931 (WAIT_REG_MEM_MEM_SPACE(mem_space) |3932 WAIT_REG_MEM_OPERATION(opt) | /* wait */3933 WAIT_REG_MEM_FUNCTION(3) | /* equal */3934 WAIT_REG_MEM_ENGINE(eng_sel)));3935 3936 if (mem_space)3937 BUG_ON(addr0 & 0x3); /* Dword align */3938 amdgpu_ring_write(ring, addr0);3939 amdgpu_ring_write(ring, addr1);3940 amdgpu_ring_write(ring, ref);3941 amdgpu_ring_write(ring, mask);3942 amdgpu_ring_write(ring, inv); /* poll interval */3943}3944 3945static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)3946{3947 struct amdgpu_device *adev = ring->adev;3948 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);3949 uint32_t tmp = 0;3950 unsigned int i;3951 int r;3952 3953 WREG32(scratch, 0xCAFEDEAD);3954 r = amdgpu_ring_alloc(ring, 3);3955 if (r) {3956 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",3957 ring->idx, r);3958 return r;3959 }3960 3961 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));3962 amdgpu_ring_write(ring, scratch -3963 PACKET3_SET_UCONFIG_REG_START);3964 amdgpu_ring_write(ring, 0xDEADBEEF);3965 amdgpu_ring_commit(ring);3966 3967 for (i = 0; i < adev->usec_timeout; i++) {3968 tmp = RREG32(scratch);3969 if (tmp == 0xDEADBEEF)3970 break;3971 if (amdgpu_emu_mode == 1)3972 msleep(1);3973 else3974 udelay(1);3975 }3976 3977 if (i >= adev->usec_timeout)3978 r = -ETIMEDOUT;3979 3980 return r;3981}3982 3983static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)3984{3985 struct amdgpu_device *adev = ring->adev;3986 struct amdgpu_ib ib;3987 struct dma_fence *f = NULL;3988 unsigned int index;3989 uint64_t gpu_addr;3990 volatile uint32_t *cpu_ptr;3991 long r;3992 3993 memset(&ib, 0, sizeof(ib));3994 3995 r = amdgpu_device_wb_get(adev, &index);3996 if (r)3997 return r;3998 3999 gpu_addr = adev->wb.gpu_addr + (index * 4);4000 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);4001 cpu_ptr = &adev->wb.wb[index];4002 4003 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);4004 if (r) {4005 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);4006 goto err1;4007 }4008 4009 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);4010 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;4011 ib.ptr[2] = lower_32_bits(gpu_addr);4012 ib.ptr[3] = upper_32_bits(gpu_addr);4013 ib.ptr[4] = 0xDEADBEEF;4014 ib.length_dw = 5;4015 4016 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);4017 if (r)4018 goto err2;4019 4020 r = dma_fence_wait_timeout(f, false, timeout);4021 if (r == 0) {4022 r = -ETIMEDOUT;4023 goto err2;4024 } else if (r < 0) {4025 goto err2;4026 }4027 4028 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)4029 r = 0;4030 else4031 r = -EINVAL;4032err2:4033 amdgpu_ib_free(adev, &ib, NULL);4034 dma_fence_put(f);4035err1:4036 amdgpu_device_wb_free(adev, index);4037 return r;4038}4039 4040static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)4041{4042 amdgpu_ucode_release(&adev->gfx.pfp_fw);4043 amdgpu_ucode_release(&adev->gfx.me_fw);4044 amdgpu_ucode_release(&adev->gfx.ce_fw);4045 amdgpu_ucode_release(&adev->gfx.rlc_fw);4046 amdgpu_ucode_release(&adev->gfx.mec_fw);4047 amdgpu_ucode_release(&adev->gfx.mec2_fw);4048 4049 kfree(adev->gfx.rlc.register_list_format);4050}4051 4052static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)4053{4054 adev->gfx.cp_fw_write_wait = false;4055 4056 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {4057 case IP_VERSION(10, 1, 10):4058 case IP_VERSION(10, 1, 2):4059 case IP_VERSION(10, 1, 1):4060 case IP_VERSION(10, 1, 3):4061 case IP_VERSION(10, 1, 4):4062 if ((adev->gfx.me_fw_version >= 0x00000046) &&4063 (adev->gfx.me_feature_version >= 27) &&4064 (adev->gfx.pfp_fw_version >= 0x00000068) &&4065 (adev->gfx.pfp_feature_version >= 27) &&4066 (adev->gfx.mec_fw_version >= 0x0000005b) &&4067 (adev->gfx.mec_feature_version >= 27))4068 adev->gfx.cp_fw_write_wait = true;4069 break;4070 case IP_VERSION(10, 3, 0):4071 case IP_VERSION(10, 3, 2):4072 case IP_VERSION(10, 3, 1):4073 case IP_VERSION(10, 3, 4):4074 case IP_VERSION(10, 3, 5):4075 case IP_VERSION(10, 3, 6):4076 case IP_VERSION(10, 3, 3):4077 case IP_VERSION(10, 3, 7):4078 adev->gfx.cp_fw_write_wait = true;4079 break;4080 default:4081 break;4082 }4083 4084 if (!adev->gfx.cp_fw_write_wait)4085 DRM_WARN_ONCE("CP firmware version too old, please update!");4086}4087 4088static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)4089{4090 bool ret = false;4091 4092 switch (adev->pdev->revision) {4093 case 0xc2:4094 case 0xc3:4095 ret = true;4096 break;4097 default:4098 ret = false;4099 break;4100 }4101 4102 return ret;4103}4104 4105static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)4106{4107 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {4108 case IP_VERSION(10, 1, 10):4109 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))4110 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;4111 break;4112 default:4113 break;4114 }4115}4116 4117static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)4118{4119 char fw_name[53];4120 char ucode_prefix[30];4121 const char *wks = "";4122 int err;4123 const struct rlc_firmware_header_v2_0 *rlc_hdr;4124 uint16_t version_major;4125 uint16_t version_minor;4126 4127 DRM_DEBUG("\n");4128 4129 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&4130 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))4131 wks = "_wks";4132 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));4133 4134 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,4135 "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);4136 if (err)4137 goto out;4138 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);4139 4140 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,4141 "amdgpu/%s_me%s.bin", ucode_prefix, wks);4142 if (err)4143 goto out;4144 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);4145 4146 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,4147 "amdgpu/%s_ce%s.bin", ucode_prefix, wks);4148 if (err)4149 goto out;4150 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);4151 4152 if (!amdgpu_sriov_vf(adev)) {4153 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);4154 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);4155 if (err)4156 goto out;4157 4158 /* don't validate this firmware. There are apparently firmwares4159 * in the wild with incorrect size in the header4160 */4161 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;4162 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);4163 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);4164 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);4165 if (err)4166 goto out;4167 }4168 4169 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,4170 "amdgpu/%s_mec%s.bin", ucode_prefix, wks);4171 if (err)4172 goto out;4173 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);4174 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);4175 4176 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,4177 "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);4178 if (!err) {4179 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);4180 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);4181 } else {4182 err = 0;4183 adev->gfx.mec2_fw = NULL;4184 }4185 4186 gfx_v10_0_check_fw_write_wait(adev);4187out:4188 if (err) {4189 amdgpu_ucode_release(&adev->gfx.pfp_fw);4190 amdgpu_ucode_release(&adev->gfx.me_fw);4191 amdgpu_ucode_release(&adev->gfx.ce_fw);4192 amdgpu_ucode_release(&adev->gfx.rlc_fw);4193 amdgpu_ucode_release(&adev->gfx.mec_fw);4194 amdgpu_ucode_release(&adev->gfx.mec2_fw);4195 }4196 4197 gfx_v10_0_check_gfxoff_flag(adev);4198 4199 return err;4200}4201 4202static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)4203{4204 u32 count = 0;4205 const struct cs_section_def *sect = NULL;4206 const struct cs_extent_def *ext = NULL;4207 4208 /* begin clear state */4209 count += 2;4210 /* context control state */4211 count += 3;4212 4213 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {4214 for (ext = sect->section; ext->extent != NULL; ++ext) {4215 if (sect->id == SECT_CONTEXT)4216 count += 2 + ext->reg_count;4217 else4218 return 0;4219 }4220 }4221 4222 /* set PA_SC_TILE_STEERING_OVERRIDE */4223 count += 3;4224 /* end clear state */4225 count += 2;4226 /* clear state */4227 count += 2;4228 4229 return count;4230}4231 4232static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,4233 volatile u32 *buffer)4234{4235 u32 count = 0, i;4236 const struct cs_section_def *sect = NULL;4237 const struct cs_extent_def *ext = NULL;4238 int ctx_reg_offset;4239 4240 if (adev->gfx.rlc.cs_data == NULL)4241 return;4242 if (buffer == NULL)4243 return;4244 4245 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));4246 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);4247 4248 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));4249 buffer[count++] = cpu_to_le32(0x80000000);4250 buffer[count++] = cpu_to_le32(0x80000000);4251 4252 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {4253 for (ext = sect->section; ext->extent != NULL; ++ext) {4254 if (sect->id == SECT_CONTEXT) {4255 buffer[count++] =4256 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));4257 buffer[count++] = cpu_to_le32(ext->reg_index -4258 PACKET3_SET_CONTEXT_REG_START);4259 for (i = 0; i < ext->reg_count; i++)4260 buffer[count++] = cpu_to_le32(ext->extent[i]);4261 } else {4262 return;4263 }4264 }4265 }4266 4267 ctx_reg_offset =4268 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;4269 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));4270 buffer[count++] = cpu_to_le32(ctx_reg_offset);4271 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);4272 4273 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));4274 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);4275 4276 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));4277 buffer[count++] = cpu_to_le32(0);4278}4279 4280static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)4281{4282 /* clear state block */4283 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,4284 &adev->gfx.rlc.clear_state_gpu_addr,4285 (void **)&adev->gfx.rlc.cs_ptr);4286 4287 /* jump table block */4288 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,4289 &adev->gfx.rlc.cp_table_gpu_addr,4290 (void **)&adev->gfx.rlc.cp_table_ptr);4291}4292 4293static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)4294{4295 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;4296 4297 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];4298 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);4299 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);4300 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);4301 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);4302 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);4303 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);4304 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {4305 case IP_VERSION(10, 3, 0):4306 reg_access_ctrl->spare_int =4307 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);4308 break;4309 default:4310 reg_access_ctrl->spare_int =4311 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);4312 break;4313 }4314 adev->gfx.rlc.rlcg_reg_access_supported = true;4315}4316 4317static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)4318{4319 const struct cs_section_def *cs_data;4320 int r;4321 4322 adev->gfx.rlc.cs_data = gfx10_cs_data;4323 4324 cs_data = adev->gfx.rlc.cs_data;4325 4326 if (cs_data) {4327 /* init clear state block */4328 r = amdgpu_gfx_rlc_init_csb(adev);4329 if (r)4330 return r;4331 }4332 4333 return 0;4334}4335 4336static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)4337{4338 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);4339 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);4340}4341 4342static void gfx_v10_0_me_init(struct amdgpu_device *adev)4343{4344 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);4345 4346 amdgpu_gfx_graphics_queue_acquire(adev);4347}4348 4349static int gfx_v10_0_mec_init(struct amdgpu_device *adev)4350{4351 int r;4352 u32 *hpd;4353 const __le32 *fw_data = NULL;4354 unsigned int fw_size;4355 u32 *fw = NULL;4356 size_t mec_hpd_size;4357 4358 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;4359 4360 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);4361 4362 /* take ownership of the relevant compute queues */4363 amdgpu_gfx_compute_queue_acquire(adev);4364 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;4365 4366 if (mec_hpd_size) {4367 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,4368 AMDGPU_GEM_DOMAIN_GTT,4369 &adev->gfx.mec.hpd_eop_obj,4370 &adev->gfx.mec.hpd_eop_gpu_addr,4371 (void **)&hpd);4372 if (r) {4373 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);4374 gfx_v10_0_mec_fini(adev);4375 return r;4376 }4377 4378 memset(hpd, 0, mec_hpd_size);4379 4380 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);4381 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);4382 }4383 4384 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {4385 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;4386 4387 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +4388 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));4389 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);4390 4391 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,4392 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,4393 &adev->gfx.mec.mec_fw_obj,4394 &adev->gfx.mec.mec_fw_gpu_addr,4395 (void **)&fw);4396 if (r) {4397 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);4398 gfx_v10_0_mec_fini(adev);4399 return r;4400 }4401 4402 memcpy(fw, fw_data, fw_size);4403 4404 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);4405 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);4406 }4407 4408 return 0;4409}4410 4411static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)4412{4413 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,4414 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |4415 (address << SQ_IND_INDEX__INDEX__SHIFT));4416 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);4417}4418 4419static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,4420 uint32_t thread, uint32_t regno,4421 uint32_t num, uint32_t *out)4422{4423 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,4424 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |4425 (regno << SQ_IND_INDEX__INDEX__SHIFT) |4426 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |4427 (SQ_IND_INDEX__AUTO_INCR_MASK));4428 while (num--)4429 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);4430}4431 4432static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)4433{4434 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE4435 * field when performing a select_se_sh so it should be4436 * zero here4437 */4438 WARN_ON(simd != 0);4439 4440 /* type 2 wave data */4441 dst[(*no_fields)++] = 2;4442 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);4443 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);4444 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);4445 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);4446 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);4447 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);4448 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);4449 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);4450 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);4451 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);4452 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);4453 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);4454 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);4455 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);4456 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);4457 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);4458}4459 4460static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,4461 uint32_t wave, uint32_t start,4462 uint32_t size, uint32_t *dst)4463{4464 WARN_ON(simd != 0);4465 4466 wave_read_regs(4467 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,4468 dst);4469}4470 4471static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,4472 uint32_t wave, uint32_t thread,4473 uint32_t start, uint32_t size,4474 uint32_t *dst)4475{4476 wave_read_regs(4477 adev, wave, thread,4478 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);4479}4480 4481static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,4482 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)4483{4484 nv_grbm_select(adev, me, pipe, q, vm);4485}4486 4487static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,4488 bool enable)4489{4490 uint32_t data, def;4491 4492 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);4493 4494 if (enable)4495 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;4496 else4497 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;4498 4499 if (data != def)4500 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);4501}4502 4503static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {4504 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,4505 .select_se_sh = &gfx_v10_0_select_se_sh,4506 .read_wave_data = &gfx_v10_0_read_wave_data,4507 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,4508 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,4509 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,4510 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,4511 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,4512};4513 4514static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)4515{4516 u32 gb_addr_config;4517 4518 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {4519 case IP_VERSION(10, 1, 10):4520 case IP_VERSION(10, 1, 1):4521 case IP_VERSION(10, 1, 2):4522 adev->gfx.config.max_hw_contexts = 8;4523 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;4524 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;4525 adev->gfx.config.sc_hiz_tile_fifo_size = 0;4526 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;4527 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);4528 break;4529 case IP_VERSION(10, 3, 0):4530 case IP_VERSION(10, 3, 2):4531 case IP_VERSION(10, 3, 1):4532 case IP_VERSION(10, 3, 4):4533 case IP_VERSION(10, 3, 5):4534 case IP_VERSION(10, 3, 6):4535 case IP_VERSION(10, 3, 3):4536 case IP_VERSION(10, 3, 7):4537 adev->gfx.config.max_hw_contexts = 8;4538 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;4539 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;4540 adev->gfx.config.sc_hiz_tile_fifo_size = 0;4541 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;4542 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);4543 adev->gfx.config.gb_addr_config_fields.num_pkrs =4544 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);4545 break;4546 case IP_VERSION(10, 1, 3):4547 case IP_VERSION(10, 1, 4):4548 adev->gfx.config.max_hw_contexts = 8;4549 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;4550 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;4551 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;4552 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;4553 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;4554 break;4555 default:4556 BUG();4557 break;4558 }4559 4560 adev->gfx.config.gb_addr_config = gb_addr_config;4561 4562 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<4563 REG_GET_FIELD(adev->gfx.config.gb_addr_config,4564 GB_ADDR_CONFIG, NUM_PIPES);4565 4566 adev->gfx.config.max_tile_pipes =4567 adev->gfx.config.gb_addr_config_fields.num_pipes;4568 4569 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<4570 REG_GET_FIELD(adev->gfx.config.gb_addr_config,4571 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);4572 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<4573 REG_GET_FIELD(adev->gfx.config.gb_addr_config,4574 GB_ADDR_CONFIG, NUM_RB_PER_SE);4575 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<4576 REG_GET_FIELD(adev->gfx.config.gb_addr_config,4577 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);4578 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +4579 REG_GET_FIELD(adev->gfx.config.gb_addr_config,4580 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));4581}4582 4583static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,4584 int me, int pipe, int queue)4585{4586 struct amdgpu_ring *ring;4587 unsigned int irq_type;4588 unsigned int hw_prio;4589 4590 ring = &adev->gfx.gfx_ring[ring_id];4591 4592 ring->me = me;4593 ring->pipe = pipe;4594 ring->queue = queue;4595 4596 ring->ring_obj = NULL;4597 ring->use_doorbell = true;4598 4599 if (!ring_id)4600 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;4601 else4602 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;4603 ring->vm_hub = AMDGPU_GFXHUB(0);4604 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);4605 4606 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;4607 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?4608 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;4609 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,4610 hw_prio, NULL);4611}4612 4613static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,4614 int mec, int pipe, int queue)4615{4616 unsigned int irq_type;4617 struct amdgpu_ring *ring;4618 unsigned int hw_prio;4619 4620 ring = &adev->gfx.compute_ring[ring_id];4621 4622 /* mec0 is me1 */4623 ring->me = mec + 1;4624 ring->pipe = pipe;4625 ring->queue = queue;4626 4627 ring->ring_obj = NULL;4628 ring->use_doorbell = true;4629 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;4630 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr4631 + (ring_id * GFX10_MEC_HPD_SIZE);4632 ring->vm_hub = AMDGPU_GFXHUB(0);4633 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);4634 4635 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP4636 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)4637 + ring->pipe;4638 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?4639 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;4640 /* type-2 packets are deprecated on MEC, use type-3 instead */4641 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,4642 hw_prio, NULL);4643}4644 4645static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)4646{4647 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);4648 uint32_t *ptr;4649 uint32_t inst;4650 4651 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);4652 if (!ptr) {4653 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");4654 adev->gfx.ip_dump_core = NULL;4655 } else {4656 adev->gfx.ip_dump_core = ptr;4657 }4658 4659 /* Allocate memory for compute queue registers for all the instances */4660 reg_count = ARRAY_SIZE(gc_cp_reg_list_10);4661 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *4662 adev->gfx.mec.num_queue_per_pipe;4663 4664 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);4665 if (!ptr) {4666 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");4667 adev->gfx.ip_dump_compute_queues = NULL;4668 } else {4669 adev->gfx.ip_dump_compute_queues = ptr;4670 }4671 4672 /* Allocate memory for gfx queue registers for all the instances */4673 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);4674 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *4675 adev->gfx.me.num_queue_per_pipe;4676 4677 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);4678 if (!ptr) {4679 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");4680 adev->gfx.ip_dump_gfx_queues = NULL;4681 } else {4682 adev->gfx.ip_dump_gfx_queues = ptr;4683 }4684}4685 4686static int gfx_v10_0_sw_init(void *handle)4687{4688 int i, j, k, r, ring_id = 0;4689 int xcc_id = 0;4690 struct amdgpu_device *adev = (struct amdgpu_device *)handle;4691 4692 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {4693 case IP_VERSION(10, 1, 10):4694 case IP_VERSION(10, 1, 1):4695 case IP_VERSION(10, 1, 2):4696 case IP_VERSION(10, 1, 3):4697 case IP_VERSION(10, 1, 4):4698 adev->gfx.me.num_me = 1;4699 adev->gfx.me.num_pipe_per_me = 1;4700 adev->gfx.me.num_queue_per_pipe = 1;4701 adev->gfx.mec.num_mec = 2;4702 adev->gfx.mec.num_pipe_per_mec = 4;4703 adev->gfx.mec.num_queue_per_pipe = 8;4704 break;4705 case IP_VERSION(10, 3, 0):4706 case IP_VERSION(10, 3, 2):4707 case IP_VERSION(10, 3, 1):4708 case IP_VERSION(10, 3, 4):4709 case IP_VERSION(10, 3, 5):4710 case IP_VERSION(10, 3, 6):4711 case IP_VERSION(10, 3, 3):4712 case IP_VERSION(10, 3, 7):4713 adev->gfx.me.num_me = 1;4714 adev->gfx.me.num_pipe_per_me = 2;4715 adev->gfx.me.num_queue_per_pipe = 1;4716 adev->gfx.mec.num_mec = 2;4717 adev->gfx.mec.num_pipe_per_mec = 4;4718 adev->gfx.mec.num_queue_per_pipe = 4;4719 break;4720 default:4721 adev->gfx.me.num_me = 1;4722 adev->gfx.me.num_pipe_per_me = 1;4723 adev->gfx.me.num_queue_per_pipe = 1;4724 adev->gfx.mec.num_mec = 1;4725 adev->gfx.mec.num_pipe_per_mec = 4;4726 adev->gfx.mec.num_queue_per_pipe = 8;4727 break;4728 }4729 4730 /* KIQ event */4731 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,4732 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,4733 &adev->gfx.kiq[0].irq);4734 if (r)4735 return r;4736 4737 /* EOP Event */4738 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,4739 GFX_10_1__SRCID__CP_EOP_INTERRUPT,4740 &adev->gfx.eop_irq);4741 if (r)4742 return r;4743 4744 /* Bad opcode Event */4745 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,4746 GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR,4747 &adev->gfx.bad_op_irq);4748 if (r)4749 return r;4750 4751 /* Privileged reg */4752 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,4753 &adev->gfx.priv_reg_irq);4754 if (r)4755 return r;4756 4757 /* Privileged inst */4758 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,4759 &adev->gfx.priv_inst_irq);4760 if (r)4761 return r;4762 4763 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;4764 4765 gfx_v10_0_me_init(adev);4766 4767 if (adev->gfx.rlc.funcs) {4768 if (adev->gfx.rlc.funcs->init) {4769 r = adev->gfx.rlc.funcs->init(adev);4770 if (r) {4771 dev_err(adev->dev, "Failed to init rlc BOs!\n");4772 return r;4773 }4774 }4775 }4776 4777 r = gfx_v10_0_mec_init(adev);4778 if (r) {4779 DRM_ERROR("Failed to init MEC BOs!\n");4780 return r;4781 }4782 4783 /* set up the gfx ring */4784 for (i = 0; i < adev->gfx.me.num_me; i++) {4785 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {4786 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {4787 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))4788 continue;4789 4790 r = gfx_v10_0_gfx_ring_init(adev, ring_id,4791 i, k, j);4792 if (r)4793 return r;4794 ring_id++;4795 }4796 }4797 }4798 4799 ring_id = 0;4800 /* set up the compute queues - allocate horizontally across pipes */4801 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {4802 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {4803 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {4804 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,4805 k, j))4806 continue;4807 4808 r = gfx_v10_0_compute_ring_init(adev, ring_id,4809 i, k, j);4810 if (r)4811 return r;4812 4813 ring_id++;4814 }4815 }4816 }4817 4818 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);4819 if (r) {4820 DRM_ERROR("Failed to init KIQ BOs!\n");4821 return r;4822 }4823 4824 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);4825 if (r)4826 return r;4827 4828 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);4829 if (r)4830 return r;4831 4832 /* allocate visible FB for rlc auto-loading fw */4833 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {4834 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);4835 if (r)4836 return r;4837 }4838 4839 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;4840 4841 gfx_v10_0_gpu_early_init(adev);4842 4843 gfx_v10_0_alloc_ip_dump(adev);4844 4845 return 0;4846}4847 4848static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)4849{4850 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,4851 &adev->gfx.pfp.pfp_fw_gpu_addr,4852 (void **)&adev->gfx.pfp.pfp_fw_ptr);4853}4854 4855static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)4856{4857 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,4858 &adev->gfx.ce.ce_fw_gpu_addr,4859 (void **)&adev->gfx.ce.ce_fw_ptr);4860}4861 4862static void gfx_v10_0_me_fini(struct amdgpu_device *adev)4863{4864 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,4865 &adev->gfx.me.me_fw_gpu_addr,4866 (void **)&adev->gfx.me.me_fw_ptr);4867}4868 4869static int gfx_v10_0_sw_fini(void *handle)4870{4871 int i;4872 struct amdgpu_device *adev = (struct amdgpu_device *)handle;4873 4874 for (i = 0; i < adev->gfx.num_gfx_rings; i++)4875 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);4876 for (i = 0; i < adev->gfx.num_compute_rings; i++)4877 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);4878 4879 amdgpu_gfx_mqd_sw_fini(adev, 0);4880 4881 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);4882 amdgpu_gfx_kiq_fini(adev, 0);4883 4884 gfx_v10_0_pfp_fini(adev);4885 gfx_v10_0_ce_fini(adev);4886 gfx_v10_0_me_fini(adev);4887 gfx_v10_0_rlc_fini(adev);4888 gfx_v10_0_mec_fini(adev);4889 4890 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)4891 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);4892 4893 gfx_v10_0_free_microcode(adev);4894 4895 kfree(adev->gfx.ip_dump_core);4896 kfree(adev->gfx.ip_dump_compute_queues);4897 kfree(adev->gfx.ip_dump_gfx_queues);4898 4899 return 0;4900}4901 4902static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,4903 u32 sh_num, u32 instance, int xcc_id)4904{4905 u32 data;4906 4907 if (instance == 0xffffffff)4908 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,4909 INSTANCE_BROADCAST_WRITES, 1);4910 else4911 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,4912 instance);4913 4914 if (se_num == 0xffffffff)4915 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,4916 1);4917 else4918 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);4919 4920 if (sh_num == 0xffffffff)4921 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,4922 1);4923 else4924 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);4925 4926 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);4927}4928 4929static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)4930{4931 u32 data, mask;4932 4933 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);4934 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);4935 4936 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;4937 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;4938 4939 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /4940 adev->gfx.config.max_sh_per_se);4941 4942 return (~data) & mask;4943}4944 4945static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)4946{4947 int i, j;4948 u32 data;4949 u32 active_rbs = 0;4950 u32 bitmap;4951 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /4952 adev->gfx.config.max_sh_per_se;4953 4954 mutex_lock(&adev->grbm_idx_mutex);4955 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {4956 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {4957 bitmap = i * adev->gfx.config.max_sh_per_se + j;4958 if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==4959 IP_VERSION(10, 3, 0)) ||4960 (amdgpu_ip_version(adev, GC_HWIP, 0) ==4961 IP_VERSION(10, 3, 3)) ||4962 (amdgpu_ip_version(adev, GC_HWIP, 0) ==4963 IP_VERSION(10, 3, 6))) &&4964 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))4965 continue;4966 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);4967 data = gfx_v10_0_get_rb_active_bitmap(adev);4968 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *4969 rb_bitmap_width_per_sh);4970 }4971 }4972 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);4973 mutex_unlock(&adev->grbm_idx_mutex);4974 4975 adev->gfx.config.backend_enable_mask = active_rbs;4976 adev->gfx.config.num_rbs = hweight32(active_rbs);4977}4978 4979static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)4980{4981 uint32_t num_sc;4982 uint32_t enabled_rb_per_sh;4983 uint32_t active_rb_bitmap;4984 uint32_t num_rb_per_sc;4985 uint32_t num_packer_per_sc;4986 uint32_t pa_sc_tile_steering_override;4987 4988 /* for ASICs that integrates GFX v10.34989 * pa_sc_tile_steering_override should be set to 04990 */4991 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))4992 return 0;4993 4994 /* init num_sc */4995 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *4996 adev->gfx.config.num_sc_per_sh;4997 /* init num_rb_per_sc */4998 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);4999 enabled_rb_per_sh = hweight32(active_rb_bitmap);5000 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;5001 /* init num_packer_per_sc */5002 num_packer_per_sc = adev->gfx.config.num_packer_per_sc;5003 5004 pa_sc_tile_steering_override = 0;5005 pa_sc_tile_steering_override |=5006 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &5007 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;5008 pa_sc_tile_steering_override |=5009 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &5010 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;5011 pa_sc_tile_steering_override |=5012 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &5013 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;5014 5015 return pa_sc_tile_steering_override;5016}5017 5018#define DEFAULT_SH_MEM_BASES (0x6000)5019 5020static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,5021 uint32_t first_vmid,5022 uint32_t last_vmid)5023{5024 uint32_t data;5025 uint32_t trap_config_vmid_mask = 0;5026 int i;5027 5028 /* Calculate trap config vmid mask */5029 for (i = first_vmid; i < last_vmid; i++)5030 trap_config_vmid_mask |= (1 << i);5031 5032 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,5033 VMID_SEL, trap_config_vmid_mask);5034 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,5035 TRAP_EN, 1);5036 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);5037 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);5038 5039 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);5040 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);5041}5042 5043static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)5044{5045 int i;5046 uint32_t sh_mem_bases;5047 5048 /*5049 * Configure apertures:5050 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)5051 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)5052 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)5053 */5054 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);5055 5056 mutex_lock(&adev->srbm_mutex);5057 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {5058 nv_grbm_select(adev, 0, 0, 0, i);5059 /* CP and shaders */5060 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);5061 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);5062 }5063 nv_grbm_select(adev, 0, 0, 0, 0);5064 mutex_unlock(&adev->srbm_mutex);5065 5066 /*5067 * Initialize all compute VMIDs to have no GDS, GWS, or OA5068 * access. These should be enabled by FW for target VMIDs.5069 */5070 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {5071 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);5072 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);5073 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);5074 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);5075 }5076 5077 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,5078 AMDGPU_NUM_VMID);5079}5080 5081static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)5082{5083 int vmid;5084 5085 /*5086 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA5087 * access. Compute VMIDs should be enabled by FW for target VMIDs,5088 * the driver can enable them for graphics. VMID0 should maintain5089 * access so that HWS firmware can save/restore entries.5090 */5091 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {5092 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);5093 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);5094 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);5095 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);5096 }5097}5098 5099 5100static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)5101{5102 int i, j, k;5103 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;5104 u32 tmp, wgp_active_bitmap = 0;5105 u32 gcrd_targets_disable_tcp = 0;5106 u32 utcl_invreq_disable = 0;5107 /*5108 * GCRD_TARGETS_DISABLE field contains5109 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]5110 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]5111 */5112 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(5113 2 * max_wgp_per_sh + /* TCP */5114 max_wgp_per_sh + /* SQC */5115 4); /* GL1C */5116 /*5117 * UTCL1_UTCL0_INVREQ_DISABLE field contains5118 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]5119 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]5120 */5121 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(5122 2 * max_wgp_per_sh + /* TCP */5123 2 * max_wgp_per_sh + /* SQC */5124 4 + /* RMI */5125 1); /* SQG */5126 5127 mutex_lock(&adev->grbm_idx_mutex);5128 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {5129 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {5130 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);5131 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);5132 /*5133 * Set corresponding TCP bits for the inactive WGPs in5134 * GCRD_SA_TARGETS_DISABLE5135 */5136 gcrd_targets_disable_tcp = 0;5137 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */5138 utcl_invreq_disable = 0;5139 5140 for (k = 0; k < max_wgp_per_sh; k++) {5141 if (!(wgp_active_bitmap & (1 << k))) {5142 gcrd_targets_disable_tcp |= 3 << (2 * k);5143 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));5144 utcl_invreq_disable |= (3 << (2 * k)) |5145 (3 << (2 * (max_wgp_per_sh + k)));5146 }5147 }5148 5149 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);5150 /* only override TCP & SQC bits */5151 tmp &= (0xffffffffU << (4 * max_wgp_per_sh));5152 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);5153 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);5154 5155 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);5156 /* only override TCP & SQC bits */5157 tmp &= (0xffffffffU << (3 * max_wgp_per_sh));5158 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);5159 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);5160 }5161 }5162 5163 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);5164 mutex_unlock(&adev->grbm_idx_mutex);5165}5166 5167static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)5168{5169 /* TCCs are global (not instanced). */5170 uint32_t tcc_disable;5171 5172 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {5173 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |5174 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);5175 } else {5176 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |5177 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);5178 }5179 5180 adev->gfx.config.tcc_disabled_mask =5181 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |5182 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);5183}5184 5185static void gfx_v10_0_constants_init(struct amdgpu_device *adev)5186{5187 u32 tmp;5188 int i;5189 5190 if (!amdgpu_sriov_vf(adev))5191 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);5192 5193 gfx_v10_0_setup_rb(adev);5194 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);5195 gfx_v10_0_get_tcc_info(adev);5196 adev->gfx.config.pa_sc_tile_steering_override =5197 gfx_v10_0_init_pa_sc_tile_steering_override(adev);5198 5199 /* XXX SH_MEM regs */5200 /* where to put LDS, scratch, GPUVM in FSA64 space */5201 mutex_lock(&adev->srbm_mutex);5202 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {5203 nv_grbm_select(adev, 0, 0, 0, i);5204 /* CP and shaders */5205 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);5206 if (i != 0) {5207 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,5208 (adev->gmc.private_aperture_start >> 48));5209 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,5210 (adev->gmc.shared_aperture_start >> 48));5211 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);5212 }5213 }5214 nv_grbm_select(adev, 0, 0, 0, 0);5215 5216 mutex_unlock(&adev->srbm_mutex);5217 5218 gfx_v10_0_init_compute_vmid(adev);5219 gfx_v10_0_init_gds_vmid(adev);5220 5221}5222 5223static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev,5224 int me, int pipe)5225{5226 if (me != 0)5227 return 0;5228 5229 switch (pipe) {5230 case 0:5231 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);5232 case 1:5233 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);5234 default:5235 return 0;5236 }5237}5238 5239static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev,5240 int me, int pipe)5241{5242 /*5243 * amdgpu controls only the first MEC. That's why this function only5244 * handles the setting of interrupts for this specific MEC. All other5245 * pipes' interrupts are set by amdkfd.5246 */5247 if (me != 1)5248 return 0;5249 5250 switch (pipe) {5251 case 0:5252 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);5253 case 1:5254 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);5255 case 2:5256 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);5257 case 3:5258 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);5259 default:5260 return 0;5261 }5262}5263 5264static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,5265 bool enable)5266{5267 u32 tmp, cp_int_cntl_reg;5268 int i, j;5269 5270 if (amdgpu_sriov_vf(adev))5271 return;5272 5273 for (i = 0; i < adev->gfx.me.num_me; i++) {5274 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {5275 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);5276 5277 if (cp_int_cntl_reg) {5278 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);5279 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,5280 enable ? 1 : 0);5281 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,5282 enable ? 1 : 0);5283 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,5284 enable ? 1 : 0);5285 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,5286 enable ? 1 : 0);5287 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);5288 }5289 }5290 }5291}5292 5293static int gfx_v10_0_init_csb(struct amdgpu_device *adev)5294{5295 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);5296 5297 /* csib */5298 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {5299 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,5300 adev->gfx.rlc.clear_state_gpu_addr >> 32);5301 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,5302 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);5303 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);5304 } else {5305 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,5306 adev->gfx.rlc.clear_state_gpu_addr >> 32);5307 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,5308 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);5309 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);5310 }5311 return 0;5312}5313 5314static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)5315{5316 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);5317 5318 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);5319 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);5320}5321 5322static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)5323{5324 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);5325 udelay(50);5326 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);5327 udelay(50);5328}5329 5330static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,5331 bool enable)5332{5333 uint32_t rlc_pg_cntl;5334 5335 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);5336 5337 if (!enable) {5338 /* RLC_PG_CNTL[23] = 0 (default)5339 * RLC will wait for handshake acks with SMU5340 * GFXOFF will be enabled5341 * RLC_PG_CNTL[23] = 15342 * RLC will not issue any message to SMU5343 * hence no handshake between SMU & RLC5344 * GFXOFF will be disabled5345 */5346 rlc_pg_cntl |= 0x800000;5347 } else5348 rlc_pg_cntl &= ~0x800000;5349 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);5350}5351 5352static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)5353{5354 /*5355 * TODO: enable rlc & smu handshake until smu5356 * and gfxoff feature works as expected5357 */5358 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))5359 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);5360 5361 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);5362 udelay(50);5363}5364 5365static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)5366{5367 uint32_t tmp;5368 5369 /* enable Save Restore Machine */5370 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);5371 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;5372 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;5373 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);5374}5375 5376static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)5377{5378 const struct rlc_firmware_header_v2_0 *hdr;5379 const __le32 *fw_data;5380 unsigned int i, fw_size;5381 5382 if (!adev->gfx.rlc_fw)5383 return -EINVAL;5384 5385 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;5386 amdgpu_ucode_print_rlc_hdr(&hdr->header);5387 5388 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +5389 le32_to_cpu(hdr->header.ucode_array_offset_bytes));5390 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;5391 5392 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,5393 RLCG_UCODE_LOADING_START_ADDRESS);5394 5395 for (i = 0; i < fw_size; i++)5396 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,5397 le32_to_cpup(fw_data++));5398 5399 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);5400 5401 return 0;5402}5403 5404static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)5405{5406 int r;5407 5408 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&5409 adev->psp.autoload_supported) {5410 5411 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);5412 if (r)5413 return r;5414 5415 gfx_v10_0_init_csb(adev);5416 5417 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);5418 5419 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */5420 gfx_v10_0_rlc_enable_srm(adev);5421 } else {5422 if (amdgpu_sriov_vf(adev)) {5423 gfx_v10_0_init_csb(adev);5424 return 0;5425 }5426 5427 adev->gfx.rlc.funcs->stop(adev);5428 5429 /* disable CG */5430 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);5431 5432 /* disable PG */5433 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);5434 5435 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {5436 /* legacy rlc firmware loading */5437 r = gfx_v10_0_rlc_load_microcode(adev);5438 if (r)5439 return r;5440 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {5441 /* rlc backdoor autoload firmware */5442 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);5443 if (r)5444 return r;5445 }5446 5447 gfx_v10_0_init_csb(adev);5448 5449 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);5450 5451 adev->gfx.rlc.funcs->start(adev);5452 5453 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {5454 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);5455 if (r)5456 return r;5457 }5458 }5459 5460 return 0;5461}5462 5463static struct {5464 FIRMWARE_ID id;5465 unsigned int offset;5466 unsigned int size;5467} rlc_autoload_info[FIRMWARE_ID_MAX];5468 5469static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)5470{5471 int ret;5472 RLC_TABLE_OF_CONTENT *rlc_toc;5473 5474 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,5475 AMDGPU_GEM_DOMAIN_GTT,5476 &adev->gfx.rlc.rlc_toc_bo,5477 &adev->gfx.rlc.rlc_toc_gpu_addr,5478 (void **)&adev->gfx.rlc.rlc_toc_buf);5479 if (ret) {5480 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);5481 return ret;5482 }5483 5484 /* Copy toc from psp sos fw to rlc toc buffer */5485 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);5486 5487 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;5488 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&5489 (rlc_toc->id < FIRMWARE_ID_MAX)) {5490 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&5491 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {5492 /* Offset needs 4KB alignment */5493 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);5494 }5495 5496 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;5497 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;5498 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;5499 5500 rlc_toc++;5501 }5502 5503 return 0;5504}5505 5506static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)5507{5508 uint32_t total_size = 0;5509 FIRMWARE_ID id;5510 int ret;5511 5512 ret = gfx_v10_0_parse_rlc_toc(adev);5513 if (ret) {5514 dev_err(adev->dev, "failed to parse rlc toc\n");5515 return 0;5516 }5517 5518 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)5519 total_size += rlc_autoload_info[id].size;5520 5521 /* In case the offset in rlc toc ucode is aligned */5522 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)5523 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +5524 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;5525 5526 return total_size;5527}5528 5529static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)5530{5531 int r;5532 uint32_t total_size;5533 5534 total_size = gfx_v10_0_calc_toc_total_size(adev);5535 5536 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,5537 AMDGPU_GEM_DOMAIN_GTT,5538 &adev->gfx.rlc.rlc_autoload_bo,5539 &adev->gfx.rlc.rlc_autoload_gpu_addr,5540 (void **)&adev->gfx.rlc.rlc_autoload_ptr);5541 if (r) {5542 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);5543 return r;5544 }5545 5546 return 0;5547}5548 5549static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)5550{5551 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,5552 &adev->gfx.rlc.rlc_toc_gpu_addr,5553 (void **)&adev->gfx.rlc.rlc_toc_buf);5554 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,5555 &adev->gfx.rlc.rlc_autoload_gpu_addr,5556 (void **)&adev->gfx.rlc.rlc_autoload_ptr);5557}5558 5559static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,5560 FIRMWARE_ID id,5561 const void *fw_data,5562 uint32_t fw_size)5563{5564 uint32_t toc_offset;5565 uint32_t toc_fw_size;5566 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;5567 5568 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)5569 return;5570 5571 toc_offset = rlc_autoload_info[id].offset;5572 toc_fw_size = rlc_autoload_info[id].size;5573 5574 if (fw_size == 0)5575 fw_size = toc_fw_size;5576 5577 if (fw_size > toc_fw_size)5578 fw_size = toc_fw_size;5579 5580 memcpy(ptr + toc_offset, fw_data, fw_size);5581 5582 if (fw_size < toc_fw_size)5583 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);5584}5585 5586static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)5587{5588 void *data;5589 uint32_t size;5590 5591 data = adev->gfx.rlc.rlc_toc_buf;5592 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;5593 5594 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,5595 FIRMWARE_ID_RLC_TOC,5596 data, size);5597}5598 5599static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)5600{5601 const __le32 *fw_data;5602 uint32_t fw_size;5603 const struct gfx_firmware_header_v1_0 *cp_hdr;5604 const struct rlc_firmware_header_v2_0 *rlc_hdr;5605 5606 /* pfp ucode */5607 cp_hdr = (const struct gfx_firmware_header_v1_0 *)5608 adev->gfx.pfp_fw->data;5609 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +5610 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));5611 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);5612 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,5613 FIRMWARE_ID_CP_PFP,5614 fw_data, fw_size);5615 5616 /* ce ucode */5617 cp_hdr = (const struct gfx_firmware_header_v1_0 *)5618 adev->gfx.ce_fw->data;5619 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +5620 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));5621 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);5622 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,5623 FIRMWARE_ID_CP_CE,5624 fw_data, fw_size);5625 5626 /* me ucode */5627 cp_hdr = (const struct gfx_firmware_header_v1_0 *)5628 adev->gfx.me_fw->data;5629 fw_data = (const __le32 *)(adev->gfx.me_fw->data +5630 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));5631 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);5632 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,5633 FIRMWARE_ID_CP_ME,5634 fw_data, fw_size);5635 5636 /* rlc ucode */5637 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)5638 adev->gfx.rlc_fw->data;5639 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +5640 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));5641 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);5642 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,5643 FIRMWARE_ID_RLC_G_UCODE,5644 fw_data, fw_size);5645 5646 /* mec1 ucode */5647 cp_hdr = (const struct gfx_firmware_header_v1_0 *)5648 adev->gfx.mec_fw->data;5649 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +5650 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));5651 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -5652 cp_hdr->jt_size * 4;5653 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,5654 FIRMWARE_ID_CP_MEC,5655 fw_data, fw_size);5656 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */5657}5658 5659/* Temporarily put sdma part here */5660static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)5661{5662 const __le32 *fw_data;5663 uint32_t fw_size;5664 const struct sdma_firmware_header_v1_0 *sdma_hdr;5665 int i;5666 5667 for (i = 0; i < adev->sdma.num_instances; i++) {5668 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)5669 adev->sdma.instance[i].fw->data;5670 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +5671 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));5672 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);5673 5674 if (i == 0) {5675 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,5676 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);5677 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,5678 FIRMWARE_ID_SDMA0_JT,5679 (uint32_t *)fw_data +5680 sdma_hdr->jt_offset,5681 sdma_hdr->jt_size * 4);5682 } else if (i == 1) {5683 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,5684 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);5685 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,5686 FIRMWARE_ID_SDMA1_JT,5687 (uint32_t *)fw_data +5688 sdma_hdr->jt_offset,5689 sdma_hdr->jt_size * 4);5690 }5691 }5692}5693 5694static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)5695{5696 uint32_t rlc_g_offset, rlc_g_size, tmp;5697 uint64_t gpu_addr;5698 5699 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);5700 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);5701 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);5702 5703 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;5704 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;5705 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;5706 5707 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));5708 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));5709 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);5710 5711 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);5712 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |5713 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {5714 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");5715 return -EINVAL;5716 }5717 5718 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);5719 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {5720 DRM_ERROR("RLC ROM should halt itself\n");5721 return -EINVAL;5722 }5723 5724 return 0;5725}5726 5727static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)5728{5729 uint32_t usec_timeout = 50000; /* wait for 50ms */5730 uint32_t tmp;5731 int i;5732 uint64_t addr;5733 5734 /* Trigger an invalidation of the L1 instruction caches */5735 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);5736 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);5737 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);5738 5739 /* Wait for invalidation complete */5740 for (i = 0; i < usec_timeout; i++) {5741 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);5742 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,5743 INVALIDATE_CACHE_COMPLETE))5744 break;5745 udelay(1);5746 }5747 5748 if (i >= usec_timeout) {5749 dev_err(adev->dev, "failed to invalidate instruction cache\n");5750 return -EINVAL;5751 }5752 5753 /* Program me ucode address into intruction cache address register */5754 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +5755 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;5756 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,5757 lower_32_bits(addr) & 0xFFFFF000);5758 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,5759 upper_32_bits(addr));5760 5761 return 0;5762}5763 5764static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)5765{5766 uint32_t usec_timeout = 50000; /* wait for 50ms */5767 uint32_t tmp;5768 int i;5769 uint64_t addr;5770 5771 /* Trigger an invalidation of the L1 instruction caches */5772 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);5773 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);5774 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);5775 5776 /* Wait for invalidation complete */5777 for (i = 0; i < usec_timeout; i++) {5778 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);5779 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,5780 INVALIDATE_CACHE_COMPLETE))5781 break;5782 udelay(1);5783 }5784 5785 if (i >= usec_timeout) {5786 dev_err(adev->dev, "failed to invalidate instruction cache\n");5787 return -EINVAL;5788 }5789 5790 /* Program ce ucode address into intruction cache address register */5791 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +5792 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;5793 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,5794 lower_32_bits(addr) & 0xFFFFF000);5795 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,5796 upper_32_bits(addr));5797 5798 return 0;5799}5800 5801static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)5802{5803 uint32_t usec_timeout = 50000; /* wait for 50ms */5804 uint32_t tmp;5805 int i;5806 uint64_t addr;5807 5808 /* Trigger an invalidation of the L1 instruction caches */5809 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);5810 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);5811 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);5812 5813 /* Wait for invalidation complete */5814 for (i = 0; i < usec_timeout; i++) {5815 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);5816 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,5817 INVALIDATE_CACHE_COMPLETE))5818 break;5819 udelay(1);5820 }5821 5822 if (i >= usec_timeout) {5823 dev_err(adev->dev, "failed to invalidate instruction cache\n");5824 return -EINVAL;5825 }5826 5827 /* Program pfp ucode address into intruction cache address register */5828 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +5829 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;5830 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,5831 lower_32_bits(addr) & 0xFFFFF000);5832 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,5833 upper_32_bits(addr));5834 5835 return 0;5836}5837 5838static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)5839{5840 uint32_t usec_timeout = 50000; /* wait for 50ms */5841 uint32_t tmp;5842 int i;5843 uint64_t addr;5844 5845 /* Trigger an invalidation of the L1 instruction caches */5846 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);5847 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);5848 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);5849 5850 /* Wait for invalidation complete */5851 for (i = 0; i < usec_timeout; i++) {5852 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);5853 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,5854 INVALIDATE_CACHE_COMPLETE))5855 break;5856 udelay(1);5857 }5858 5859 if (i >= usec_timeout) {5860 dev_err(adev->dev, "failed to invalidate instruction cache\n");5861 return -EINVAL;5862 }5863 5864 /* Program mec1 ucode address into intruction cache address register */5865 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +5866 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;5867 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,5868 lower_32_bits(addr) & 0xFFFFF000);5869 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,5870 upper_32_bits(addr));5871 5872 return 0;5873}5874 5875static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)5876{5877 uint32_t cp_status;5878 uint32_t bootload_status;5879 int i, r;5880 5881 for (i = 0; i < adev->usec_timeout; i++) {5882 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);5883 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);5884 if ((cp_status == 0) &&5885 (REG_GET_FIELD(bootload_status,5886 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {5887 break;5888 }5889 udelay(1);5890 }5891 5892 if (i >= adev->usec_timeout) {5893 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");5894 return -ETIMEDOUT;5895 }5896 5897 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {5898 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);5899 if (r)5900 return r;5901 5902 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);5903 if (r)5904 return r;5905 5906 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);5907 if (r)5908 return r;5909 5910 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);5911 if (r)5912 return r;5913 }5914 5915 return 0;5916}5917 5918static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)5919{5920 int i;5921 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);5922 5923 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);5924 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);5925 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);5926 5927 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))5928 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);5929 else5930 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);5931 5932 if (adev->job_hang && !enable)5933 return 0;5934 5935 for (i = 0; i < adev->usec_timeout; i++) {5936 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)5937 break;5938 udelay(1);5939 }5940 5941 if (i >= adev->usec_timeout)5942 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");5943 5944 return 0;5945}5946 5947static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)5948{5949 int r;5950 const struct gfx_firmware_header_v1_0 *pfp_hdr;5951 const __le32 *fw_data;5952 unsigned int i, fw_size;5953 uint32_t tmp;5954 uint32_t usec_timeout = 50000; /* wait for 50ms */5955 5956 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)5957 adev->gfx.pfp_fw->data;5958 5959 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);5960 5961 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +5962 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));5963 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);5964 5965 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,5966 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,5967 &adev->gfx.pfp.pfp_fw_obj,5968 &adev->gfx.pfp.pfp_fw_gpu_addr,5969 (void **)&adev->gfx.pfp.pfp_fw_ptr);5970 if (r) {5971 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);5972 gfx_v10_0_pfp_fini(adev);5973 return r;5974 }5975 5976 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);5977 5978 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);5979 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);5980 5981 /* Trigger an invalidation of the L1 instruction caches */5982 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);5983 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);5984 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);5985 5986 /* Wait for invalidation complete */5987 for (i = 0; i < usec_timeout; i++) {5988 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);5989 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,5990 INVALIDATE_CACHE_COMPLETE))5991 break;5992 udelay(1);5993 }5994 5995 if (i >= usec_timeout) {5996 dev_err(adev->dev, "failed to invalidate instruction cache\n");5997 return -EINVAL;5998 }5999 6000 if (amdgpu_emu_mode == 1)6001 adev->hdp.funcs->flush_hdp(adev, NULL);6002 6003 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);6004 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);6005 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);6006 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);6007 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);6008 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);6009 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,6010 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);6011 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,6012 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));6013 6014 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);6015 6016 for (i = 0; i < pfp_hdr->jt_size; i++)6017 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,6018 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));6019 6020 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);6021 6022 return 0;6023}6024 6025static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)6026{6027 int r;6028 const struct gfx_firmware_header_v1_0 *ce_hdr;6029 const __le32 *fw_data;6030 unsigned int i, fw_size;6031 uint32_t tmp;6032 uint32_t usec_timeout = 50000; /* wait for 50ms */6033 6034 ce_hdr = (const struct gfx_firmware_header_v1_0 *)6035 adev->gfx.ce_fw->data;6036 6037 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);6038 6039 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +6040 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));6041 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);6042 6043 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,6044 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,6045 &adev->gfx.ce.ce_fw_obj,6046 &adev->gfx.ce.ce_fw_gpu_addr,6047 (void **)&adev->gfx.ce.ce_fw_ptr);6048 if (r) {6049 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);6050 gfx_v10_0_ce_fini(adev);6051 return r;6052 }6053 6054 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);6055 6056 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);6057 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);6058 6059 /* Trigger an invalidation of the L1 instruction caches */6060 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);6061 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);6062 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);6063 6064 /* Wait for invalidation complete */6065 for (i = 0; i < usec_timeout; i++) {6066 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);6067 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,6068 INVALIDATE_CACHE_COMPLETE))6069 break;6070 udelay(1);6071 }6072 6073 if (i >= usec_timeout) {6074 dev_err(adev->dev, "failed to invalidate instruction cache\n");6075 return -EINVAL;6076 }6077 6078 if (amdgpu_emu_mode == 1)6079 adev->hdp.funcs->flush_hdp(adev, NULL);6080 6081 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);6082 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);6083 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);6084 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);6085 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);6086 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,6087 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);6088 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,6089 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));6090 6091 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);6092 6093 for (i = 0; i < ce_hdr->jt_size; i++)6094 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,6095 le32_to_cpup(fw_data + ce_hdr->jt_offset + i));6096 6097 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);6098 6099 return 0;6100}6101 6102static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)6103{6104 int r;6105 const struct gfx_firmware_header_v1_0 *me_hdr;6106 const __le32 *fw_data;6107 unsigned int i, fw_size;6108 uint32_t tmp;6109 uint32_t usec_timeout = 50000; /* wait for 50ms */6110 6111 me_hdr = (const struct gfx_firmware_header_v1_0 *)6112 adev->gfx.me_fw->data;6113 6114 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);6115 6116 fw_data = (const __le32 *)(adev->gfx.me_fw->data +6117 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));6118 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);6119 6120 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,6121 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,6122 &adev->gfx.me.me_fw_obj,6123 &adev->gfx.me.me_fw_gpu_addr,6124 (void **)&adev->gfx.me.me_fw_ptr);6125 if (r) {6126 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);6127 gfx_v10_0_me_fini(adev);6128 return r;6129 }6130 6131 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);6132 6133 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);6134 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);6135 6136 /* Trigger an invalidation of the L1 instruction caches */6137 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);6138 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);6139 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);6140 6141 /* Wait for invalidation complete */6142 for (i = 0; i < usec_timeout; i++) {6143 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);6144 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,6145 INVALIDATE_CACHE_COMPLETE))6146 break;6147 udelay(1);6148 }6149 6150 if (i >= usec_timeout) {6151 dev_err(adev->dev, "failed to invalidate instruction cache\n");6152 return -EINVAL;6153 }6154 6155 if (amdgpu_emu_mode == 1)6156 adev->hdp.funcs->flush_hdp(adev, NULL);6157 6158 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);6159 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);6160 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);6161 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);6162 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);6163 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,6164 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);6165 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,6166 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));6167 6168 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);6169 6170 for (i = 0; i < me_hdr->jt_size; i++)6171 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,6172 le32_to_cpup(fw_data + me_hdr->jt_offset + i));6173 6174 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);6175 6176 return 0;6177}6178 6179static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)6180{6181 int r;6182 6183 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)6184 return -EINVAL;6185 6186 gfx_v10_0_cp_gfx_enable(adev, false);6187 6188 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);6189 if (r) {6190 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);6191 return r;6192 }6193 6194 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);6195 if (r) {6196 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);6197 return r;6198 }6199 6200 r = gfx_v10_0_cp_gfx_load_me_microcode(adev);6201 if (r) {6202 dev_err(adev->dev, "(%d) failed to load me fw\n", r);6203 return r;6204 }6205 6206 return 0;6207}6208 6209static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)6210{6211 struct amdgpu_ring *ring;6212 const struct cs_section_def *sect = NULL;6213 const struct cs_extent_def *ext = NULL;6214 int r, i;6215 int ctx_reg_offset;6216 6217 /* init the CP */6218 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,6219 adev->gfx.config.max_hw_contexts - 1);6220 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);6221 6222 gfx_v10_0_cp_gfx_enable(adev, true);6223 6224 ring = &adev->gfx.gfx_ring[0];6225 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);6226 if (r) {6227 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);6228 return r;6229 }6230 6231 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));6232 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);6233 6234 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));6235 amdgpu_ring_write(ring, 0x80000000);6236 amdgpu_ring_write(ring, 0x80000000);6237 6238 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {6239 for (ext = sect->section; ext->extent != NULL; ++ext) {6240 if (sect->id == SECT_CONTEXT) {6241 amdgpu_ring_write(ring,6242 PACKET3(PACKET3_SET_CONTEXT_REG,6243 ext->reg_count));6244 amdgpu_ring_write(ring, ext->reg_index -6245 PACKET3_SET_CONTEXT_REG_START);6246 for (i = 0; i < ext->reg_count; i++)6247 amdgpu_ring_write(ring, ext->extent[i]);6248 }6249 }6250 }6251 6252 ctx_reg_offset =6253 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;6254 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));6255 amdgpu_ring_write(ring, ctx_reg_offset);6256 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);6257 6258 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));6259 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);6260 6261 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));6262 amdgpu_ring_write(ring, 0);6263 6264 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));6265 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));6266 amdgpu_ring_write(ring, 0x8000);6267 amdgpu_ring_write(ring, 0x8000);6268 6269 amdgpu_ring_commit(ring);6270 6271 /* submit cs packet to copy state 0 to next available state */6272 if (adev->gfx.num_gfx_rings > 1) {6273 /* maximum supported gfx ring is 2 */6274 ring = &adev->gfx.gfx_ring[1];6275 r = amdgpu_ring_alloc(ring, 2);6276 if (r) {6277 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);6278 return r;6279 }6280 6281 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));6282 amdgpu_ring_write(ring, 0);6283 6284 amdgpu_ring_commit(ring);6285 }6286 return 0;6287}6288 6289static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,6290 CP_PIPE_ID pipe)6291{6292 u32 tmp;6293 6294 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);6295 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);6296 6297 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);6298}6299 6300static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,6301 struct amdgpu_ring *ring)6302{6303 u32 tmp;6304 6305 if (!amdgpu_async_gfx_ring) {6306 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);6307 if (ring->use_doorbell) {6308 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,6309 DOORBELL_OFFSET, ring->doorbell_index);6310 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,6311 DOORBELL_EN, 1);6312 } else {6313 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,6314 DOORBELL_EN, 0);6315 }6316 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);6317 }6318 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {6319 case IP_VERSION(10, 3, 0):6320 case IP_VERSION(10, 3, 2):6321 case IP_VERSION(10, 3, 1):6322 case IP_VERSION(10, 3, 4):6323 case IP_VERSION(10, 3, 5):6324 case IP_VERSION(10, 3, 6):6325 case IP_VERSION(10, 3, 3):6326 case IP_VERSION(10, 3, 7):6327 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,6328 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);6329 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);6330 6331 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,6332 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);6333 break;6334 default:6335 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,6336 DOORBELL_RANGE_LOWER, ring->doorbell_index);6337 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);6338 6339 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,6340 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);6341 break;6342 }6343}6344 6345static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)6346{6347 struct amdgpu_ring *ring;6348 u32 tmp;6349 u32 rb_bufsz;6350 u64 rb_addr, rptr_addr, wptr_gpu_addr;6351 6352 /* Set the write pointer delay */6353 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);6354 6355 /* set the RB to use vmid 0 */6356 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);6357 6358 /* Init gfx ring 0 for pipe 0 */6359 mutex_lock(&adev->srbm_mutex);6360 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);6361 6362 /* Set ring buffer size */6363 ring = &adev->gfx.gfx_ring[0];6364 rb_bufsz = order_base_2(ring->ring_size / 8);6365 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);6366 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);6367#ifdef __BIG_ENDIAN6368 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);6369#endif6370 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);6371 6372 /* Initialize the ring buffer's write pointers */6373 ring->wptr = 0;6374 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));6375 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));6376 6377 /* set the wb address wether it's enabled or not */6378 rptr_addr = ring->rptr_gpu_addr;6379 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));6380 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &6381 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);6382 6383 wptr_gpu_addr = ring->wptr_gpu_addr;6384 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,6385 lower_32_bits(wptr_gpu_addr));6386 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,6387 upper_32_bits(wptr_gpu_addr));6388 6389 mdelay(1);6390 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);6391 6392 rb_addr = ring->gpu_addr >> 8;6393 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);6394 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));6395 6396 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);6397 6398 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);6399 mutex_unlock(&adev->srbm_mutex);6400 6401 /* Init gfx ring 1 for pipe 1 */6402 if (adev->gfx.num_gfx_rings > 1) {6403 mutex_lock(&adev->srbm_mutex);6404 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);6405 /* maximum supported gfx ring is 2 */6406 ring = &adev->gfx.gfx_ring[1];6407 rb_bufsz = order_base_2(ring->ring_size / 8);6408 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);6409 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);6410 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);6411 /* Initialize the ring buffer's write pointers */6412 ring->wptr = 0;6413 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));6414 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));6415 /* Set the wb address wether it's enabled or not */6416 rptr_addr = ring->rptr_gpu_addr;6417 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));6418 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &6419 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);6420 wptr_gpu_addr = ring->wptr_gpu_addr;6421 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,6422 lower_32_bits(wptr_gpu_addr));6423 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,6424 upper_32_bits(wptr_gpu_addr));6425 6426 mdelay(1);6427 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);6428 6429 rb_addr = ring->gpu_addr >> 8;6430 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);6431 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));6432 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);6433 6434 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);6435 mutex_unlock(&adev->srbm_mutex);6436 }6437 /* Switch to pipe 0 */6438 mutex_lock(&adev->srbm_mutex);6439 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);6440 mutex_unlock(&adev->srbm_mutex);6441 6442 /* start the ring */6443 gfx_v10_0_cp_gfx_start(adev);6444 6445 return 0;6446}6447 6448static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)6449{6450 if (enable) {6451 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {6452 case IP_VERSION(10, 3, 0):6453 case IP_VERSION(10, 3, 2):6454 case IP_VERSION(10, 3, 1):6455 case IP_VERSION(10, 3, 4):6456 case IP_VERSION(10, 3, 5):6457 case IP_VERSION(10, 3, 6):6458 case IP_VERSION(10, 3, 3):6459 case IP_VERSION(10, 3, 7):6460 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);6461 break;6462 default:6463 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);6464 break;6465 }6466 } else {6467 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {6468 case IP_VERSION(10, 3, 0):6469 case IP_VERSION(10, 3, 2):6470 case IP_VERSION(10, 3, 1):6471 case IP_VERSION(10, 3, 4):6472 case IP_VERSION(10, 3, 5):6473 case IP_VERSION(10, 3, 6):6474 case IP_VERSION(10, 3, 3):6475 case IP_VERSION(10, 3, 7):6476 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,6477 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |6478 CP_MEC_CNTL__MEC_ME2_HALT_MASK));6479 break;6480 default:6481 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,6482 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |6483 CP_MEC_CNTL__MEC_ME2_HALT_MASK));6484 break;6485 }6486 adev->gfx.kiq[0].ring.sched.ready = false;6487 }6488 udelay(50);6489}6490 6491static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)6492{6493 const struct gfx_firmware_header_v1_0 *mec_hdr;6494 const __le32 *fw_data;6495 unsigned int i;6496 u32 tmp;6497 u32 usec_timeout = 50000; /* Wait for 50 ms */6498 6499 if (!adev->gfx.mec_fw)6500 return -EINVAL;6501 6502 gfx_v10_0_cp_compute_enable(adev, false);6503 6504 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;6505 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);6506 6507 fw_data = (const __le32 *)6508 (adev->gfx.mec_fw->data +6509 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));6510 6511 /* Trigger an invalidation of the L1 instruction caches */6512 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);6513 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);6514 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);6515 6516 /* Wait for invalidation complete */6517 for (i = 0; i < usec_timeout; i++) {6518 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);6519 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,6520 INVALIDATE_CACHE_COMPLETE))6521 break;6522 udelay(1);6523 }6524 6525 if (i >= usec_timeout) {6526 dev_err(adev->dev, "failed to invalidate instruction cache\n");6527 return -EINVAL;6528 }6529 6530 if (amdgpu_emu_mode == 1)6531 adev->hdp.funcs->flush_hdp(adev, NULL);6532 6533 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);6534 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);6535 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);6536 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);6537 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);6538 6539 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &6540 0xFFFFF000);6541 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,6542 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));6543 6544 /* MEC1 */6545 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);6546 6547 for (i = 0; i < mec_hdr->jt_size; i++)6548 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,6549 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));6550 6551 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);6552 6553 /*6554 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run6555 * different microcode than MEC1.6556 */6557 6558 return 0;6559}6560 6561static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)6562{6563 uint32_t tmp;6564 struct amdgpu_device *adev = ring->adev;6565 6566 /* tell RLC which is KIQ queue */6567 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {6568 case IP_VERSION(10, 3, 0):6569 case IP_VERSION(10, 3, 2):6570 case IP_VERSION(10, 3, 1):6571 case IP_VERSION(10, 3, 4):6572 case IP_VERSION(10, 3, 5):6573 case IP_VERSION(10, 3, 6):6574 case IP_VERSION(10, 3, 3):6575 case IP_VERSION(10, 3, 7):6576 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);6577 tmp &= 0xffffff00;6578 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);6579 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);6580 tmp |= 0x80;6581 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);6582 break;6583 default:6584 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);6585 tmp &= 0xffffff00;6586 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);6587 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);6588 tmp |= 0x80;6589 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);6590 break;6591 }6592}6593 6594static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,6595 struct v10_gfx_mqd *mqd,6596 struct amdgpu_mqd_prop *prop)6597{6598 bool priority = 0;6599 u32 tmp;6600 6601 /* set up default queue priority level6602 * 0x0 = low priority, 0x1 = high priority6603 */6604 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)6605 priority = 1;6606 6607 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);6608 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);6609 mqd->cp_gfx_hqd_queue_priority = tmp;6610}6611 6612static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,6613 struct amdgpu_mqd_prop *prop)6614{6615 struct v10_gfx_mqd *mqd = m;6616 uint64_t hqd_gpu_addr, wb_gpu_addr;6617 uint32_t tmp;6618 uint32_t rb_bufsz;6619 6620 /* set up gfx hqd wptr */6621 mqd->cp_gfx_hqd_wptr = 0;6622 mqd->cp_gfx_hqd_wptr_hi = 0;6623 6624 /* set the pointer to the MQD */6625 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;6626 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);6627 6628 /* set up mqd control */6629 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);6630 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);6631 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);6632 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);6633 mqd->cp_gfx_mqd_control = tmp;6634 6635 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */6636 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);6637 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);6638 mqd->cp_gfx_hqd_vmid = 0;6639 6640 /* set up gfx queue priority */6641 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);6642 6643 /* set up time quantum */6644 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);6645 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);6646 mqd->cp_gfx_hqd_quantum = tmp;6647 6648 /* set up gfx hqd base. this is similar as CP_RB_BASE */6649 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;6650 mqd->cp_gfx_hqd_base = hqd_gpu_addr;6651 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);6652 6653 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */6654 wb_gpu_addr = prop->rptr_gpu_addr;6655 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;6656 mqd->cp_gfx_hqd_rptr_addr_hi =6657 upper_32_bits(wb_gpu_addr) & 0xffff;6658 6659 /* set up rb_wptr_poll addr */6660 wb_gpu_addr = prop->wptr_gpu_addr;6661 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;6662 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;6663 6664 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */6665 rb_bufsz = order_base_2(prop->queue_size / 4) - 1;6666 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);6667 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);6668 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);6669#ifdef __BIG_ENDIAN6670 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);6671#endif6672 mqd->cp_gfx_hqd_cntl = tmp;6673 6674 /* set up cp_doorbell_control */6675 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);6676 if (prop->use_doorbell) {6677 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,6678 DOORBELL_OFFSET, prop->doorbell_index);6679 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,6680 DOORBELL_EN, 1);6681 } else6682 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,6683 DOORBELL_EN, 0);6684 mqd->cp_rb_doorbell_control = tmp;6685 6686 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */6687 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);6688 6689 /* active the queue */6690 mqd->cp_gfx_hqd_active = 1;6691 6692 return 0;6693}6694 6695static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)6696{6697 struct amdgpu_device *adev = ring->adev;6698 struct v10_gfx_mqd *mqd = ring->mqd_ptr;6699 int mqd_idx = ring - &adev->gfx.gfx_ring[0];6700 6701 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {6702 memset((void *)mqd, 0, sizeof(*mqd));6703 mutex_lock(&adev->srbm_mutex);6704 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);6705 amdgpu_ring_init_mqd(ring);6706 6707 /*6708 * if there are 2 gfx rings, set the lower doorbell6709 * range of the first ring, otherwise the range of6710 * the second ring will override the first ring6711 */6712 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)6713 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);6714 6715 nv_grbm_select(adev, 0, 0, 0, 0);6716 mutex_unlock(&adev->srbm_mutex);6717 if (adev->gfx.me.mqd_backup[mqd_idx])6718 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));6719 } else {6720 mutex_lock(&adev->srbm_mutex);6721 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);6722 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)6723 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);6724 6725 nv_grbm_select(adev, 0, 0, 0, 0);6726 mutex_unlock(&adev->srbm_mutex);6727 /* restore mqd with the backup copy */6728 if (adev->gfx.me.mqd_backup[mqd_idx])6729 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));6730 /* reset the ring */6731 ring->wptr = 0;6732 *ring->wptr_cpu_addr = 0;6733 amdgpu_ring_clear_ring(ring);6734 }6735 6736 return 0;6737}6738 6739static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)6740{6741 int r, i;6742 struct amdgpu_ring *ring;6743 6744 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {6745 ring = &adev->gfx.gfx_ring[i];6746 6747 r = amdgpu_bo_reserve(ring->mqd_obj, false);6748 if (unlikely(r != 0))6749 return r;6750 6751 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);6752 if (!r) {6753 r = gfx_v10_0_kgq_init_queue(ring, false);6754 amdgpu_bo_kunmap(ring->mqd_obj);6755 ring->mqd_ptr = NULL;6756 }6757 amdgpu_bo_unreserve(ring->mqd_obj);6758 if (r)6759 return r;6760 }6761 6762 r = amdgpu_gfx_enable_kgq(adev, 0);6763 if (r)6764 return r;6765 6766 return gfx_v10_0_cp_gfx_start(adev);6767}6768 6769static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,6770 struct amdgpu_mqd_prop *prop)6771{6772 struct v10_compute_mqd *mqd = m;6773 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;6774 uint32_t tmp;6775 6776 mqd->header = 0xC0310800;6777 mqd->compute_pipelinestat_enable = 0x00000001;6778 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;6779 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;6780 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;6781 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;6782 mqd->compute_misc_reserved = 0x00000003;6783 6784 eop_base_addr = prop->eop_gpu_addr >> 8;6785 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;6786 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);6787 6788 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */6789 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);6790 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,6791 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));6792 6793 mqd->cp_hqd_eop_control = tmp;6794 6795 /* enable doorbell? */6796 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);6797 6798 if (prop->use_doorbell) {6799 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,6800 DOORBELL_OFFSET, prop->doorbell_index);6801 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,6802 DOORBELL_EN, 1);6803 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,6804 DOORBELL_SOURCE, 0);6805 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,6806 DOORBELL_HIT, 0);6807 } else {6808 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,6809 DOORBELL_EN, 0);6810 }6811 6812 mqd->cp_hqd_pq_doorbell_control = tmp;6813 6814 /* disable the queue if it's active */6815 mqd->cp_hqd_dequeue_request = 0;6816 mqd->cp_hqd_pq_rptr = 0;6817 mqd->cp_hqd_pq_wptr_lo = 0;6818 mqd->cp_hqd_pq_wptr_hi = 0;6819 6820 /* set the pointer to the MQD */6821 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;6822 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);6823 6824 /* set MQD vmid to 0 */6825 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);6826 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);6827 mqd->cp_mqd_control = tmp;6828 6829 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */6830 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;6831 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;6832 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);6833 6834 /* set up the HQD, this is similar to CP_RB0_CNTL */6835 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);6836 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,6837 (order_base_2(prop->queue_size / 4) - 1));6838 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,6839 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));6840#ifdef __BIG_ENDIAN6841 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);6842#endif6843 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);6844 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,6845 prop->allow_tunneling);6846 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);6847 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);6848 mqd->cp_hqd_pq_control = tmp;6849 6850 /* set the wb address whether it's enabled or not */6851 wb_gpu_addr = prop->rptr_gpu_addr;6852 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;6853 mqd->cp_hqd_pq_rptr_report_addr_hi =6854 upper_32_bits(wb_gpu_addr) & 0xffff;6855 6856 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */6857 wb_gpu_addr = prop->wptr_gpu_addr;6858 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;6859 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;6860 6861 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */6862 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);6863 6864 /* set the vmid for the queue */6865 mqd->cp_hqd_vmid = 0;6866 6867 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);6868 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);6869 mqd->cp_hqd_persistent_state = tmp;6870 6871 /* set MIN_IB_AVAIL_SIZE */6872 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);6873 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);6874 mqd->cp_hqd_ib_control = tmp;6875 6876 /* set static priority for a compute queue/ring */6877 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;6878 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;6879 6880 mqd->cp_hqd_active = prop->hqd_active;6881 6882 return 0;6883}6884 6885static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)6886{6887 struct amdgpu_device *adev = ring->adev;6888 struct v10_compute_mqd *mqd = ring->mqd_ptr;6889 int j;6890 6891 /* inactivate the queue */6892 if (amdgpu_sriov_vf(adev))6893 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);6894 6895 /* disable wptr polling */6896 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);6897 6898 /* disable the queue if it's active */6899 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {6900 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);6901 for (j = 0; j < adev->usec_timeout; j++) {6902 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))6903 break;6904 udelay(1);6905 }6906 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,6907 mqd->cp_hqd_dequeue_request);6908 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,6909 mqd->cp_hqd_pq_rptr);6910 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,6911 mqd->cp_hqd_pq_wptr_lo);6912 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,6913 mqd->cp_hqd_pq_wptr_hi);6914 }6915 6916 /* disable doorbells */6917 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);6918 6919 /* write the EOP addr */6920 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,6921 mqd->cp_hqd_eop_base_addr_lo);6922 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,6923 mqd->cp_hqd_eop_base_addr_hi);6924 6925 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */6926 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,6927 mqd->cp_hqd_eop_control);6928 6929 /* set the pointer to the MQD */6930 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,6931 mqd->cp_mqd_base_addr_lo);6932 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,6933 mqd->cp_mqd_base_addr_hi);6934 6935 /* set MQD vmid to 0 */6936 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,6937 mqd->cp_mqd_control);6938 6939 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */6940 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,6941 mqd->cp_hqd_pq_base_lo);6942 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,6943 mqd->cp_hqd_pq_base_hi);6944 6945 /* set up the HQD, this is similar to CP_RB0_CNTL */6946 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,6947 mqd->cp_hqd_pq_control);6948 6949 /* set the wb address whether it's enabled or not */6950 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,6951 mqd->cp_hqd_pq_rptr_report_addr_lo);6952 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,6953 mqd->cp_hqd_pq_rptr_report_addr_hi);6954 6955 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */6956 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,6957 mqd->cp_hqd_pq_wptr_poll_addr_lo);6958 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,6959 mqd->cp_hqd_pq_wptr_poll_addr_hi);6960 6961 /* enable the doorbell if requested */6962 if (ring->use_doorbell) {6963 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,6964 (adev->doorbell_index.kiq * 2) << 2);6965 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,6966 (adev->doorbell_index.userqueue_end * 2) << 2);6967 }6968 6969 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,6970 mqd->cp_hqd_pq_doorbell_control);6971 6972 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */6973 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,6974 mqd->cp_hqd_pq_wptr_lo);6975 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,6976 mqd->cp_hqd_pq_wptr_hi);6977 6978 /* set the vmid for the queue */6979 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);6980 6981 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,6982 mqd->cp_hqd_persistent_state);6983 6984 /* activate the queue */6985 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,6986 mqd->cp_hqd_active);6987 6988 if (ring->use_doorbell)6989 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);6990 6991 return 0;6992}6993 6994static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)6995{6996 struct amdgpu_device *adev = ring->adev;6997 struct v10_compute_mqd *mqd = ring->mqd_ptr;6998 6999 gfx_v10_0_kiq_setting(ring);7000 7001 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */7002 /* reset MQD to a clean status */7003 if (adev->gfx.kiq[0].mqd_backup)7004 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));7005 7006 /* reset ring buffer */7007 ring->wptr = 0;7008 amdgpu_ring_clear_ring(ring);7009 7010 mutex_lock(&adev->srbm_mutex);7011 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);7012 gfx_v10_0_kiq_init_register(ring);7013 nv_grbm_select(adev, 0, 0, 0, 0);7014 mutex_unlock(&adev->srbm_mutex);7015 } else {7016 memset((void *)mqd, 0, sizeof(*mqd));7017 if (amdgpu_sriov_vf(adev) && adev->in_suspend)7018 amdgpu_ring_clear_ring(ring);7019 mutex_lock(&adev->srbm_mutex);7020 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);7021 amdgpu_ring_init_mqd(ring);7022 gfx_v10_0_kiq_init_register(ring);7023 nv_grbm_select(adev, 0, 0, 0, 0);7024 mutex_unlock(&adev->srbm_mutex);7025 7026 if (adev->gfx.kiq[0].mqd_backup)7027 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));7028 }7029 7030 return 0;7031}7032 7033static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore)7034{7035 struct amdgpu_device *adev = ring->adev;7036 struct v10_compute_mqd *mqd = ring->mqd_ptr;7037 int mqd_idx = ring - &adev->gfx.compute_ring[0];7038 7039 if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) {7040 memset((void *)mqd, 0, sizeof(*mqd));7041 mutex_lock(&adev->srbm_mutex);7042 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);7043 amdgpu_ring_init_mqd(ring);7044 nv_grbm_select(adev, 0, 0, 0, 0);7045 mutex_unlock(&adev->srbm_mutex);7046 7047 if (adev->gfx.mec.mqd_backup[mqd_idx])7048 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));7049 } else {7050 /* restore MQD to a clean status */7051 if (adev->gfx.mec.mqd_backup[mqd_idx])7052 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));7053 /* reset ring buffer */7054 ring->wptr = 0;7055 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);7056 amdgpu_ring_clear_ring(ring);7057 }7058 7059 return 0;7060}7061 7062static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)7063{7064 struct amdgpu_ring *ring;7065 int r;7066 7067 ring = &adev->gfx.kiq[0].ring;7068 7069 r = amdgpu_bo_reserve(ring->mqd_obj, false);7070 if (unlikely(r != 0))7071 return r;7072 7073 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);7074 if (unlikely(r != 0)) {7075 amdgpu_bo_unreserve(ring->mqd_obj);7076 return r;7077 }7078 7079 gfx_v10_0_kiq_init_queue(ring);7080 amdgpu_bo_kunmap(ring->mqd_obj);7081 ring->mqd_ptr = NULL;7082 amdgpu_bo_unreserve(ring->mqd_obj);7083 return 0;7084}7085 7086static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)7087{7088 struct amdgpu_ring *ring = NULL;7089 int r = 0, i;7090 7091 gfx_v10_0_cp_compute_enable(adev, true);7092 7093 for (i = 0; i < adev->gfx.num_compute_rings; i++) {7094 ring = &adev->gfx.compute_ring[i];7095 7096 r = amdgpu_bo_reserve(ring->mqd_obj, false);7097 if (unlikely(r != 0))7098 goto done;7099 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);7100 if (!r) {7101 r = gfx_v10_0_kcq_init_queue(ring, false);7102 amdgpu_bo_kunmap(ring->mqd_obj);7103 ring->mqd_ptr = NULL;7104 }7105 amdgpu_bo_unreserve(ring->mqd_obj);7106 if (r)7107 goto done;7108 }7109 7110 r = amdgpu_gfx_enable_kcq(adev, 0);7111done:7112 return r;7113}7114 7115static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)7116{7117 int r, i;7118 struct amdgpu_ring *ring;7119 7120 if (!(adev->flags & AMD_IS_APU))7121 gfx_v10_0_enable_gui_idle_interrupt(adev, false);7122 7123 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {7124 /* legacy firmware loading */7125 r = gfx_v10_0_cp_gfx_load_microcode(adev);7126 if (r)7127 return r;7128 7129 r = gfx_v10_0_cp_compute_load_microcode(adev);7130 if (r)7131 return r;7132 }7133 7134 r = gfx_v10_0_kiq_resume(adev);7135 if (r)7136 return r;7137 7138 r = gfx_v10_0_kcq_resume(adev);7139 if (r)7140 return r;7141 7142 if (!amdgpu_async_gfx_ring) {7143 r = gfx_v10_0_cp_gfx_resume(adev);7144 if (r)7145 return r;7146 } else {7147 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);7148 if (r)7149 return r;7150 }7151 7152 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {7153 ring = &adev->gfx.gfx_ring[i];7154 r = amdgpu_ring_test_helper(ring);7155 if (r)7156 return r;7157 }7158 7159 for (i = 0; i < adev->gfx.num_compute_rings; i++) {7160 ring = &adev->gfx.compute_ring[i];7161 r = amdgpu_ring_test_helper(ring);7162 if (r)7163 return r;7164 }7165 7166 return 0;7167}7168 7169static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)7170{7171 gfx_v10_0_cp_gfx_enable(adev, enable);7172 gfx_v10_0_cp_compute_enable(adev, enable);7173}7174 7175static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)7176{7177 uint32_t data, pattern = 0xDEADBEEF;7178 7179 /*7180 * check if mmVGT_ESGS_RING_SIZE_UMD7181 * has been remapped to mmVGT_ESGS_RING_SIZE7182 */7183 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {7184 case IP_VERSION(10, 3, 0):7185 case IP_VERSION(10, 3, 2):7186 case IP_VERSION(10, 3, 4):7187 case IP_VERSION(10, 3, 5):7188 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);7189 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);7190 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);7191 7192 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {7193 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);7194 return true;7195 }7196 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);7197 break;7198 case IP_VERSION(10, 3, 1):7199 case IP_VERSION(10, 3, 3):7200 case IP_VERSION(10, 3, 6):7201 case IP_VERSION(10, 3, 7):7202 return true;7203 default:7204 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);7205 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);7206 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);7207 7208 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {7209 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);7210 return true;7211 }7212 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);7213 break;7214 }7215 7216 return false;7217}7218 7219static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)7220{7221 uint32_t data;7222 7223 if (amdgpu_sriov_vf(adev))7224 return;7225 7226 /*7227 * Initialize cam_index to 07228 * index will auto-inc after each data writing7229 */7230 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);7231 7232 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {7233 case IP_VERSION(10, 3, 0):7234 case IP_VERSION(10, 3, 2):7235 case IP_VERSION(10, 3, 1):7236 case IP_VERSION(10, 3, 4):7237 case IP_VERSION(10, 3, 5):7238 case IP_VERSION(10, 3, 6):7239 case IP_VERSION(10, 3, 3):7240 case IP_VERSION(10, 3, 7):7241 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */7242 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<7243 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7244 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<7245 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7246 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7247 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7248 7249 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */7250 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<7251 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7252 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<7253 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7254 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7255 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7256 7257 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */7258 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<7259 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7260 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<7261 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7262 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7263 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7264 7265 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */7266 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<7267 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7268 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<7269 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7270 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7271 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7272 7273 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */7274 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<7275 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7276 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<7277 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7278 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7279 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7280 7281 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */7282 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<7283 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7284 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<7285 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7286 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7287 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7288 7289 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */7290 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<7291 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7292 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<7293 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7294 break;7295 default:7296 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */7297 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<7298 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7299 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<7300 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7301 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7302 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7303 7304 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */7305 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<7306 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7307 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<7308 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7309 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7310 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7311 7312 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */7313 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<7314 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7315 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<7316 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7317 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7318 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7319 7320 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */7321 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<7322 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7323 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<7324 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7325 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7326 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7327 7328 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */7329 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<7330 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7331 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<7332 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7333 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7334 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7335 7336 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */7337 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<7338 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7339 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<7340 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7341 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7342 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7343 7344 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */7345 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<7346 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |7347 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<7348 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);7349 break;7350 }7351 7352 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);7353 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);7354}7355 7356static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)7357{7358 uint32_t data;7359 7360 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);7361 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;7362 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);7363 7364 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);7365 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;7366 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);7367}7368 7369static int gfx_v10_0_hw_init(void *handle)7370{7371 int r;7372 struct amdgpu_device *adev = (struct amdgpu_device *)handle;7373 7374 if (!amdgpu_emu_mode)7375 gfx_v10_0_init_golden_registers(adev);7376 7377 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {7378 /**7379 * For gfx 10, rlc firmware loading relies on smu firmware is7380 * loaded firstly, so in direct type, it has to load smc ucode7381 * here before rlc.7382 */7383 r = amdgpu_pm_load_smu_firmware(adev, NULL);7384 if (r)7385 return r;7386 gfx_v10_0_disable_gpa_mode(adev);7387 }7388 7389 /* if GRBM CAM not remapped, set up the remapping */7390 if (!gfx_v10_0_check_grbm_cam_remapping(adev))7391 gfx_v10_0_setup_grbm_cam_remapping(adev);7392 7393 gfx_v10_0_constants_init(adev);7394 7395 r = gfx_v10_0_rlc_resume(adev);7396 if (r)7397 return r;7398 7399 /*7400 * init golden registers and rlc resume may override some registers,7401 * reconfig them here7402 */7403 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||7404 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||7405 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))7406 gfx_v10_0_tcp_harvest(adev);7407 7408 r = gfx_v10_0_cp_resume(adev);7409 if (r)7410 return r;7411 7412 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))7413 gfx_v10_3_program_pbb_mode(adev);7414 7415 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev))7416 gfx_v10_3_set_power_brake_sequence(adev);7417 7418 return r;7419}7420 7421static int gfx_v10_0_hw_fini(void *handle)7422{7423 struct amdgpu_device *adev = (struct amdgpu_device *)handle;7424 7425 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);7426 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);7427 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);7428 7429 /* WA added for Vangogh asic fixing the SMU suspend failure7430 * It needs to set power gating again during gfxoff control7431 * otherwise the gfxoff disallowing will be failed to set.7432 */7433 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))7434 gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE);7435 7436 if (!adev->no_hw_access) {7437 if (amdgpu_async_gfx_ring) {7438 if (amdgpu_gfx_disable_kgq(adev, 0))7439 DRM_ERROR("KGQ disable failed\n");7440 }7441 7442 if (amdgpu_gfx_disable_kcq(adev, 0))7443 DRM_ERROR("KCQ disable failed\n");7444 }7445 7446 if (amdgpu_sriov_vf(adev)) {7447 gfx_v10_0_cp_gfx_enable(adev, false);7448 /* Remove the steps of clearing KIQ position.7449 * It causes GFX hang when another Win guest is rendering.7450 */7451 return 0;7452 }7453 gfx_v10_0_cp_enable(adev, false);7454 gfx_v10_0_enable_gui_idle_interrupt(adev, false);7455 7456 return 0;7457}7458 7459static int gfx_v10_0_suspend(void *handle)7460{7461 return gfx_v10_0_hw_fini(handle);7462}7463 7464static int gfx_v10_0_resume(void *handle)7465{7466 return gfx_v10_0_hw_init(handle);7467}7468 7469static bool gfx_v10_0_is_idle(void *handle)7470{7471 struct amdgpu_device *adev = (struct amdgpu_device *)handle;7472 7473 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),7474 GRBM_STATUS, GUI_ACTIVE))7475 return false;7476 else7477 return true;7478}7479 7480static int gfx_v10_0_wait_for_idle(void *handle)7481{7482 unsigned int i;7483 u32 tmp;7484 struct amdgpu_device *adev = (struct amdgpu_device *)handle;7485 7486 for (i = 0; i < adev->usec_timeout; i++) {7487 /* read MC_STATUS */7488 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &7489 GRBM_STATUS__GUI_ACTIVE_MASK;7490 7491 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))7492 return 0;7493 udelay(1);7494 }7495 return -ETIMEDOUT;7496}7497 7498static int gfx_v10_0_soft_reset(void *handle)7499{7500 u32 grbm_soft_reset = 0;7501 u32 tmp;7502 struct amdgpu_device *adev = (struct amdgpu_device *)handle;7503 7504 /* GRBM_STATUS */7505 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);7506 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |7507 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |7508 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |7509 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |7510 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {7511 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,7512 GRBM_SOFT_RESET, SOFT_RESET_CP,7513 1);7514 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,7515 GRBM_SOFT_RESET, SOFT_RESET_GFX,7516 1);7517 }7518 7519 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {7520 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,7521 GRBM_SOFT_RESET, SOFT_RESET_CP,7522 1);7523 }7524 7525 /* GRBM_STATUS2 */7526 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);7527 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {7528 case IP_VERSION(10, 3, 0):7529 case IP_VERSION(10, 3, 2):7530 case IP_VERSION(10, 3, 1):7531 case IP_VERSION(10, 3, 4):7532 case IP_VERSION(10, 3, 5):7533 case IP_VERSION(10, 3, 6):7534 case IP_VERSION(10, 3, 3):7535 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))7536 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,7537 GRBM_SOFT_RESET,7538 SOFT_RESET_RLC,7539 1);7540 break;7541 default:7542 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))7543 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,7544 GRBM_SOFT_RESET,7545 SOFT_RESET_RLC,7546 1);7547 break;7548 }7549 7550 if (grbm_soft_reset) {7551 /* stop the rlc */7552 gfx_v10_0_rlc_stop(adev);7553 7554 /* Disable GFX parsing/prefetching */7555 gfx_v10_0_cp_gfx_enable(adev, false);7556 7557 /* Disable MEC parsing/prefetching */7558 gfx_v10_0_cp_compute_enable(adev, false);7559 7560 if (grbm_soft_reset) {7561 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);7562 tmp |= grbm_soft_reset;7563 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);7564 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);7565 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);7566 7567 udelay(50);7568 7569 tmp &= ~grbm_soft_reset;7570 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);7571 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);7572 }7573 7574 /* Wait a little for things to settle down */7575 udelay(50);7576 }7577 return 0;7578}7579 7580static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)7581{7582 uint64_t clock, clock_lo, clock_hi, hi_check;7583 7584 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {7585 case IP_VERSION(10, 1, 3):7586 case IP_VERSION(10, 1, 4):7587 preempt_disable();7588 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);7589 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);7590 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);7591 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over7592 * roughly every 42 seconds.7593 */7594 if (hi_check != clock_hi) {7595 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);7596 clock_hi = hi_check;7597 }7598 preempt_enable();7599 clock = clock_lo | (clock_hi << 32ULL);7600 break;7601 case IP_VERSION(10, 3, 1):7602 case IP_VERSION(10, 3, 3):7603 case IP_VERSION(10, 3, 7):7604 preempt_disable();7605 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);7606 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);7607 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);7608 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over7609 * roughly every 42 seconds.7610 */7611 if (hi_check != clock_hi) {7612 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);7613 clock_hi = hi_check;7614 }7615 preempt_enable();7616 clock = clock_lo | (clock_hi << 32ULL);7617 break;7618 case IP_VERSION(10, 3, 6):7619 preempt_disable();7620 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);7621 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);7622 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);7623 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over7624 * roughly every 42 seconds.7625 */7626 if (hi_check != clock_hi) {7627 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);7628 clock_hi = hi_check;7629 }7630 preempt_enable();7631 clock = clock_lo | (clock_hi << 32ULL);7632 break;7633 default:7634 preempt_disable();7635 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);7636 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);7637 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);7638 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over7639 * roughly every 42 seconds.7640 */7641 if (hi_check != clock_hi) {7642 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);7643 clock_hi = hi_check;7644 }7645 preempt_enable();7646 clock = clock_lo | (clock_hi << 32ULL);7647 break;7648 }7649 return clock;7650}7651 7652static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,7653 uint32_t vmid,7654 uint32_t gds_base, uint32_t gds_size,7655 uint32_t gws_base, uint32_t gws_size,7656 uint32_t oa_base, uint32_t oa_size)7657{7658 struct amdgpu_device *adev = ring->adev;7659 7660 /* GDS Base */7661 gfx_v10_0_write_data_to_reg(ring, 0, false,7662 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,7663 gds_base);7664 7665 /* GDS Size */7666 gfx_v10_0_write_data_to_reg(ring, 0, false,7667 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,7668 gds_size);7669 7670 /* GWS */7671 gfx_v10_0_write_data_to_reg(ring, 0, false,7672 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,7673 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);7674 7675 /* OA */7676 gfx_v10_0_write_data_to_reg(ring, 0, false,7677 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,7678 (1 << (oa_size + oa_base)) - (1 << oa_base));7679}7680 7681static int gfx_v10_0_early_init(void *handle)7682{7683 struct amdgpu_device *adev = (struct amdgpu_device *)handle;7684 7685 adev->gfx.funcs = &gfx_v10_0_gfx_funcs;7686 7687 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {7688 case IP_VERSION(10, 1, 10):7689 case IP_VERSION(10, 1, 1):7690 case IP_VERSION(10, 1, 2):7691 case IP_VERSION(10, 1, 3):7692 case IP_VERSION(10, 1, 4):7693 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;7694 break;7695 case IP_VERSION(10, 3, 0):7696 case IP_VERSION(10, 3, 2):7697 case IP_VERSION(10, 3, 1):7698 case IP_VERSION(10, 3, 4):7699 case IP_VERSION(10, 3, 5):7700 case IP_VERSION(10, 3, 6):7701 case IP_VERSION(10, 3, 3):7702 case IP_VERSION(10, 3, 7):7703 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;7704 break;7705 default:7706 break;7707 }7708 7709 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),7710 AMDGPU_MAX_COMPUTE_RINGS);7711 7712 gfx_v10_0_set_kiq_pm4_funcs(adev);7713 gfx_v10_0_set_ring_funcs(adev);7714 gfx_v10_0_set_irq_funcs(adev);7715 gfx_v10_0_set_gds_init(adev);7716 gfx_v10_0_set_rlc_funcs(adev);7717 gfx_v10_0_set_mqd_funcs(adev);7718 7719 /* init rlcg reg access ctrl */7720 gfx_v10_0_init_rlcg_reg_access_ctrl(adev);7721 7722 return gfx_v10_0_init_microcode(adev);7723}7724 7725static int gfx_v10_0_late_init(void *handle)7726{7727 struct amdgpu_device *adev = (struct amdgpu_device *)handle;7728 int r;7729 7730 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);7731 if (r)7732 return r;7733 7734 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);7735 if (r)7736 return r;7737 7738 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);7739 if (r)7740 return r;7741 7742 return 0;7743}7744 7745static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)7746{7747 uint32_t rlc_cntl;7748 7749 /* if RLC is not enabled, do nothing */7750 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);7751 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;7752}7753 7754static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)7755{7756 uint32_t data;7757 unsigned int i;7758 7759 data = RLC_SAFE_MODE__CMD_MASK;7760 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);7761 7762 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {7763 case IP_VERSION(10, 3, 0):7764 case IP_VERSION(10, 3, 2):7765 case IP_VERSION(10, 3, 1):7766 case IP_VERSION(10, 3, 4):7767 case IP_VERSION(10, 3, 5):7768 case IP_VERSION(10, 3, 6):7769 case IP_VERSION(10, 3, 3):7770 case IP_VERSION(10, 3, 7):7771 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);7772 7773 /* wait for RLC_SAFE_MODE */7774 for (i = 0; i < adev->usec_timeout; i++) {7775 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),7776 RLC_SAFE_MODE, CMD))7777 break;7778 udelay(1);7779 }7780 break;7781 default:7782 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);7783 7784 /* wait for RLC_SAFE_MODE */7785 for (i = 0; i < adev->usec_timeout; i++) {7786 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),7787 RLC_SAFE_MODE, CMD))7788 break;7789 udelay(1);7790 }7791 break;7792 }7793}7794 7795static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)7796{7797 uint32_t data;7798 7799 data = RLC_SAFE_MODE__CMD_MASK;7800 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {7801 case IP_VERSION(10, 3, 0):7802 case IP_VERSION(10, 3, 2):7803 case IP_VERSION(10, 3, 1):7804 case IP_VERSION(10, 3, 4):7805 case IP_VERSION(10, 3, 5):7806 case IP_VERSION(10, 3, 6):7807 case IP_VERSION(10, 3, 3):7808 case IP_VERSION(10, 3, 7):7809 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);7810 break;7811 default:7812 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);7813 break;7814 }7815}7816 7817static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,7818 bool enable)7819{7820 uint32_t data, def;7821 7822 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))7823 return;7824 7825 /* It is disabled by HW by default */7826 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {7827 /* 0 - Disable some blocks' MGCG */7828 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);7829 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);7830 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);7831 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);7832 7833 /* 1 - RLC_CGTT_MGCG_OVERRIDE */7834 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);7835 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |7836 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |7837 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |7838 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |7839 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |7840 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);7841 7842 if (def != data)7843 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);7844 7845 /* MGLS is a global flag to control all MGLS in GFX */7846 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {7847 /* 2 - RLC memory Light sleep */7848 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {7849 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);7850 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;7851 if (def != data)7852 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);7853 }7854 /* 3 - CP memory Light sleep */7855 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {7856 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);7857 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;7858 if (def != data)7859 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);7860 }7861 }7862 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {7863 /* 1 - MGCG_OVERRIDE */7864 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);7865 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |7866 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |7867 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |7868 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |7869 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |7870 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);7871 if (def != data)7872 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);7873 7874 /* 2 - disable MGLS in CP */7875 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);7876 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {7877 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;7878 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);7879 }7880 7881 /* 3 - disable MGLS in RLC */7882 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);7883 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {7884 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;7885 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);7886 }7887 7888 }7889}7890 7891static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,7892 bool enable)7893{7894 uint32_t data, def;7895 7896 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))7897 return;7898 7899 /* Enable 3D CGCG/CGLS */7900 if (enable) {7901 /* write cmd to clear cgcg/cgls ov */7902 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);7903 7904 /* unset CGCG override */7905 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)7906 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;7907 7908 /* update CGCG and CGLS override bits */7909 if (def != data)7910 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);7911 7912 /* enable 3Dcgcg FSM(0x0000363f) */7913 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);7914 data = 0;7915 7916 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)7917 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |7918 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;7919 7920 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)7921 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |7922 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;7923 7924 if (def != data)7925 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);7926 7927 /* set IDLE_POLL_COUNT(0x00900100) */7928 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);7929 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |7930 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);7931 if (def != data)7932 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);7933 } else {7934 /* Disable CGCG/CGLS */7935 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);7936 7937 /* disable cgcg, cgls should be disabled */7938 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)7939 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;7940 7941 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)7942 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;7943 7944 /* disable cgcg and cgls in FSM */7945 if (def != data)7946 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);7947 }7948}7949 7950static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,7951 bool enable)7952{7953 uint32_t def, data;7954 7955 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))7956 return;7957 7958 if (enable) {7959 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);7960 7961 /* unset CGCG override */7962 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)7963 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;7964 7965 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)7966 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;7967 7968 /* update CGCG and CGLS override bits */7969 if (def != data)7970 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);7971 7972 /* enable cgcg FSM(0x0000363F) */7973 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);7974 data = 0;7975 7976 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)7977 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |7978 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;7979 7980 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)7981 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |7982 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;7983 7984 if (def != data)7985 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);7986 7987 /* set IDLE_POLL_COUNT(0x00900100) */7988 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);7989 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |7990 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);7991 if (def != data)7992 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);7993 } else {7994 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);7995 7996 /* reset CGCG/CGLS bits */7997 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)7998 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;7999 8000 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)8001 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;8002 8003 /* disable cgcg and cgls in FSM */8004 if (def != data)8005 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);8006 }8007}8008 8009static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,8010 bool enable)8011{8012 uint32_t def, data;8013 8014 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))8015 return;8016 8017 if (enable) {8018 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);8019 /* unset FGCG override */8020 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;8021 /* update FGCG override bits */8022 if (def != data)8023 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);8024 8025 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);8026 /* unset RLC SRAM CLK GATER override */8027 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;8028 /* update RLC SRAM CLK GATER override bits */8029 if (def != data)8030 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);8031 } else {8032 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);8033 /* reset FGCG bits */8034 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;8035 /* disable FGCG*/8036 if (def != data)8037 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);8038 8039 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);8040 /* reset RLC SRAM CLK GATER bits */8041 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;8042 /* disable RLC SRAM CLK*/8043 if (def != data)8044 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);8045 }8046}8047 8048static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)8049{8050 uint32_t reg_data = 0;8051 uint32_t reg_idx = 0;8052 uint32_t i;8053 8054 const uint32_t tcp_ctrl_regs[] = {8055 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,8056 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,8057 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,8058 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,8059 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,8060 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,8061 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,8062 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,8063 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,8064 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,8065 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,8066 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,8067 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,8068 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,8069 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,8070 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,8071 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,8072 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,8073 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,8074 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,8075 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,8076 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,8077 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,8078 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG8079 };8080 8081 const uint32_t tcp_ctrl_regs_nv12[] = {8082 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,8083 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,8084 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,8085 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,8086 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,8087 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,8088 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,8089 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,8090 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,8091 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,8092 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,8093 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,8094 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,8095 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,8096 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,8097 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,8098 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,8099 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,8100 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,8101 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,8102 };8103 8104 const uint32_t sm_ctlr_regs[] = {8105 mmCGTS_SA0_QUAD0_SM_CTRL_REG,8106 mmCGTS_SA0_QUAD1_SM_CTRL_REG,8107 mmCGTS_SA1_QUAD0_SM_CTRL_REG,8108 mmCGTS_SA1_QUAD1_SM_CTRL_REG8109 };8110 8111 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {8112 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {8113 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +8114 tcp_ctrl_regs_nv12[i];8115 reg_data = RREG32(reg_idx);8116 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;8117 WREG32(reg_idx, reg_data);8118 }8119 } else {8120 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {8121 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +8122 tcp_ctrl_regs[i];8123 reg_data = RREG32(reg_idx);8124 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;8125 WREG32(reg_idx, reg_data);8126 }8127 }8128 8129 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {8130 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +8131 sm_ctlr_regs[i];8132 reg_data = RREG32(reg_idx);8133 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;8134 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;8135 WREG32(reg_idx, reg_data);8136 }8137}8138 8139static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,8140 bool enable)8141{8142 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);8143 8144 if (enable) {8145 /* enable FGCG firstly*/8146 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);8147 /* CGCG/CGLS should be enabled after MGCG/MGLS8148 * === MGCG + MGLS ===8149 */8150 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);8151 /* === CGCG /CGLS for GFX 3D Only === */8152 gfx_v10_0_update_3d_clock_gating(adev, enable);8153 /* === CGCG + CGLS === */8154 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);8155 8156 if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==8157 IP_VERSION(10, 1, 10)) ||8158 (amdgpu_ip_version(adev, GC_HWIP, 0) ==8159 IP_VERSION(10, 1, 1)) ||8160 (amdgpu_ip_version(adev, GC_HWIP, 0) ==8161 IP_VERSION(10, 1, 2)))8162 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);8163 } else {8164 /* CGCG/CGLS should be disabled before MGCG/MGLS8165 * === CGCG + CGLS ===8166 */8167 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);8168 /* === CGCG /CGLS for GFX 3D Only === */8169 gfx_v10_0_update_3d_clock_gating(adev, enable);8170 /* === MGCG + MGLS === */8171 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);8172 /* disable fgcg at last*/8173 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);8174 }8175 8176 if (adev->cg_flags &8177 (AMD_CG_SUPPORT_GFX_MGCG |8178 AMD_CG_SUPPORT_GFX_CGLS |8179 AMD_CG_SUPPORT_GFX_CGCG |8180 AMD_CG_SUPPORT_GFX_3D_CGCG |8181 AMD_CG_SUPPORT_GFX_3D_CGLS))8182 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);8183 8184 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);8185 8186 return 0;8187}8188 8189static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,8190 unsigned int vmid)8191{8192 u32 reg, pre_data, data;8193 8194 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);8195 /* not for *_SOC15 */8196 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))8197 pre_data = RREG32_NO_KIQ(reg);8198 else8199 pre_data = RREG32(reg);8200 8201 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);8202 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;8203 8204 if (pre_data != data) {8205 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {8206 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);8207 } else8208 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);8209 }8210}8211 8212static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)8213{8214 amdgpu_gfx_off_ctrl(adev, false);8215 8216 gfx_v10_0_update_spm_vmid_internal(adev, vmid);8217 8218 amdgpu_gfx_off_ctrl(adev, true);8219}8220 8221static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,8222 uint32_t offset,8223 struct soc15_reg_rlcg *entries, int arr_size)8224{8225 int i;8226 uint32_t reg;8227 8228 if (!entries)8229 return false;8230 8231 for (i = 0; i < arr_size; i++) {8232 const struct soc15_reg_rlcg *entry;8233 8234 entry = &entries[i];8235 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;8236 if (offset == reg)8237 return true;8238 }8239 8240 return false;8241}8242 8243static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)8244{8245 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);8246}8247 8248static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)8249{8250 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);8251 8252 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))8253 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;8254 else8255 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;8256 8257 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);8258 8259 /*8260 * CGPG enablement required and the register to program the hysteresis value8261 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value8262 * in refclk count. Note that RLC FW is modified to take 16 bits from8263 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.8264 *8265 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)8266 * of CGPG enablement starting point.8267 * Power/performance team will optimize it and might give a new value later.8268 */8269 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {8270 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {8271 case IP_VERSION(10, 3, 1):8272 case IP_VERSION(10, 3, 3):8273 case IP_VERSION(10, 3, 6):8274 case IP_VERSION(10, 3, 7):8275 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;8276 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);8277 break;8278 default:8279 break;8280 }8281 }8282}8283 8284static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)8285{8286 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);8287 8288 gfx_v10_cntl_power_gating(adev, enable);8289 8290 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);8291}8292 8293static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {8294 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,8295 .set_safe_mode = gfx_v10_0_set_safe_mode,8296 .unset_safe_mode = gfx_v10_0_unset_safe_mode,8297 .init = gfx_v10_0_rlc_init,8298 .get_csb_size = gfx_v10_0_get_csb_size,8299 .get_csb_buffer = gfx_v10_0_get_csb_buffer,8300 .resume = gfx_v10_0_rlc_resume,8301 .stop = gfx_v10_0_rlc_stop,8302 .reset = gfx_v10_0_rlc_reset,8303 .start = gfx_v10_0_rlc_start,8304 .update_spm_vmid = gfx_v10_0_update_spm_vmid,8305};8306 8307static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {8308 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,8309 .set_safe_mode = gfx_v10_0_set_safe_mode,8310 .unset_safe_mode = gfx_v10_0_unset_safe_mode,8311 .init = gfx_v10_0_rlc_init,8312 .get_csb_size = gfx_v10_0_get_csb_size,8313 .get_csb_buffer = gfx_v10_0_get_csb_buffer,8314 .resume = gfx_v10_0_rlc_resume,8315 .stop = gfx_v10_0_rlc_stop,8316 .reset = gfx_v10_0_rlc_reset,8317 .start = gfx_v10_0_rlc_start,8318 .update_spm_vmid = gfx_v10_0_update_spm_vmid,8319 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,8320};8321 8322static int gfx_v10_0_set_powergating_state(void *handle,8323 enum amd_powergating_state state)8324{8325 struct amdgpu_device *adev = (struct amdgpu_device *)handle;8326 bool enable = (state == AMD_PG_STATE_GATE);8327 8328 if (amdgpu_sriov_vf(adev))8329 return 0;8330 8331 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {8332 case IP_VERSION(10, 1, 10):8333 case IP_VERSION(10, 1, 1):8334 case IP_VERSION(10, 1, 2):8335 case IP_VERSION(10, 3, 0):8336 case IP_VERSION(10, 3, 2):8337 case IP_VERSION(10, 3, 4):8338 case IP_VERSION(10, 3, 5):8339 amdgpu_gfx_off_ctrl(adev, enable);8340 break;8341 case IP_VERSION(10, 3, 1):8342 case IP_VERSION(10, 3, 3):8343 case IP_VERSION(10, 3, 6):8344 case IP_VERSION(10, 3, 7):8345 if (!enable)8346 amdgpu_gfx_off_ctrl(adev, false);8347 8348 gfx_v10_cntl_pg(adev, enable);8349 8350 if (enable)8351 amdgpu_gfx_off_ctrl(adev, true);8352 8353 break;8354 default:8355 break;8356 }8357 return 0;8358}8359 8360static int gfx_v10_0_set_clockgating_state(void *handle,8361 enum amd_clockgating_state state)8362{8363 struct amdgpu_device *adev = (struct amdgpu_device *)handle;8364 8365 if (amdgpu_sriov_vf(adev))8366 return 0;8367 8368 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {8369 case IP_VERSION(10, 1, 10):8370 case IP_VERSION(10, 1, 1):8371 case IP_VERSION(10, 1, 2):8372 case IP_VERSION(10, 3, 0):8373 case IP_VERSION(10, 3, 2):8374 case IP_VERSION(10, 3, 1):8375 case IP_VERSION(10, 3, 4):8376 case IP_VERSION(10, 3, 5):8377 case IP_VERSION(10, 3, 6):8378 case IP_VERSION(10, 3, 3):8379 case IP_VERSION(10, 3, 7):8380 gfx_v10_0_update_gfx_clock_gating(adev,8381 state == AMD_CG_STATE_GATE);8382 break;8383 default:8384 break;8385 }8386 return 0;8387}8388 8389static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)8390{8391 struct amdgpu_device *adev = (struct amdgpu_device *)handle;8392 int data;8393 8394 /* AMD_CG_SUPPORT_GFX_FGCG */8395 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));8396 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))8397 *flags |= AMD_CG_SUPPORT_GFX_FGCG;8398 8399 /* AMD_CG_SUPPORT_GFX_MGCG */8400 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));8401 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))8402 *flags |= AMD_CG_SUPPORT_GFX_MGCG;8403 8404 /* AMD_CG_SUPPORT_GFX_CGCG */8405 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));8406 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)8407 *flags |= AMD_CG_SUPPORT_GFX_CGCG;8408 8409 /* AMD_CG_SUPPORT_GFX_CGLS */8410 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)8411 *flags |= AMD_CG_SUPPORT_GFX_CGLS;8412 8413 /* AMD_CG_SUPPORT_GFX_RLC_LS */8414 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));8415 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)8416 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;8417 8418 /* AMD_CG_SUPPORT_GFX_CP_LS */8419 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));8420 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)8421 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;8422 8423 /* AMD_CG_SUPPORT_GFX_3D_CGCG */8424 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));8425 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)8426 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;8427 8428 /* AMD_CG_SUPPORT_GFX_3D_CGLS */8429 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)8430 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;8431}8432 8433static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)8434{8435 /* gfx10 is 32bit rptr*/8436 return *(uint32_t *)ring->rptr_cpu_addr;8437}8438 8439static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)8440{8441 struct amdgpu_device *adev = ring->adev;8442 u64 wptr;8443 8444 /* XXX check if swapping is necessary on BE */8445 if (ring->use_doorbell) {8446 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);8447 } else {8448 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);8449 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;8450 }8451 8452 return wptr;8453}8454 8455static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)8456{8457 struct amdgpu_device *adev = ring->adev;8458 8459 if (ring->use_doorbell) {8460 /* XXX check if swapping is necessary on BE */8461 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,8462 ring->wptr);8463 WDOORBELL64(ring->doorbell_index, ring->wptr);8464 } else {8465 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,8466 lower_32_bits(ring->wptr));8467 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,8468 upper_32_bits(ring->wptr));8469 }8470}8471 8472static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)8473{8474 /* gfx10 hardware is 32bit rptr */8475 return *(uint32_t *)ring->rptr_cpu_addr;8476}8477 8478static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)8479{8480 u64 wptr;8481 8482 /* XXX check if swapping is necessary on BE */8483 if (ring->use_doorbell)8484 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);8485 else8486 BUG();8487 return wptr;8488}8489 8490static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)8491{8492 struct amdgpu_device *adev = ring->adev;8493 8494 if (ring->use_doorbell) {8495 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,8496 ring->wptr);8497 WDOORBELL64(ring->doorbell_index, ring->wptr);8498 } else {8499 BUG(); /* only DOORBELL method supported on gfx10 now */8500 }8501}8502 8503static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)8504{8505 struct amdgpu_device *adev = ring->adev;8506 u32 ref_and_mask, reg_mem_engine;8507 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;8508 8509 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {8510 switch (ring->me) {8511 case 1:8512 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;8513 break;8514 case 2:8515 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;8516 break;8517 default:8518 return;8519 }8520 reg_mem_engine = 0;8521 } else {8522 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;8523 reg_mem_engine = 1; /* pfp */8524 }8525 8526 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,8527 adev->nbio.funcs->get_hdp_flush_req_offset(adev),8528 adev->nbio.funcs->get_hdp_flush_done_offset(adev),8529 ref_and_mask, ref_and_mask, 0x20);8530}8531 8532static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,8533 struct amdgpu_job *job,8534 struct amdgpu_ib *ib,8535 uint32_t flags)8536{8537 unsigned int vmid = AMDGPU_JOB_GET_VMID(job);8538 u32 header, control = 0;8539 8540 if (ib->flags & AMDGPU_IB_FLAG_CE)8541 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);8542 else8543 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);8544 8545 control |= ib->length_dw | (vmid << 24);8546 8547 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {8548 control |= INDIRECT_BUFFER_PRE_ENB(1);8549 8550 if (flags & AMDGPU_IB_PREEMPTED)8551 control |= INDIRECT_BUFFER_PRE_RESUME(1);8552 8553 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)8554 gfx_v10_0_ring_emit_de_meta(ring,8555 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);8556 }8557 8558 amdgpu_ring_write(ring, header);8559 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */8560 amdgpu_ring_write(ring,8561#ifdef __BIG_ENDIAN8562 (2 << 0) |8563#endif8564 lower_32_bits(ib->gpu_addr));8565 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));8566 amdgpu_ring_write(ring, control);8567}8568 8569static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,8570 struct amdgpu_job *job,8571 struct amdgpu_ib *ib,8572 uint32_t flags)8573{8574 unsigned int vmid = AMDGPU_JOB_GET_VMID(job);8575 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);8576 8577 /* Currently, there is a high possibility to get wave ID mismatch8578 * between ME and GDS, leading to a hw deadlock, because ME generates8579 * different wave IDs than the GDS expects. This situation happens8580 * randomly when at least 5 compute pipes use GDS ordered append.8581 * The wave IDs generated by ME are also wrong after suspend/resume.8582 * Those are probably bugs somewhere else in the kernel driver.8583 *8584 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and8585 * GDS to 0 for this ring (me/pipe).8586 */8587 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {8588 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));8589 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);8590 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);8591 }8592 8593 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));8594 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */8595 amdgpu_ring_write(ring,8596#ifdef __BIG_ENDIAN8597 (2 << 0) |8598#endif8599 lower_32_bits(ib->gpu_addr));8600 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));8601 amdgpu_ring_write(ring, control);8602}8603 8604static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,8605 u64 seq, unsigned int flags)8606{8607 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;8608 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;8609 8610 /* RELEASE_MEM - flush caches, send int */8611 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));8612 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |8613 PACKET3_RELEASE_MEM_GCR_GL2_WB |8614 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */8615 PACKET3_RELEASE_MEM_GCR_GLM_WB |8616 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |8617 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |8618 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));8619 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |8620 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));8621 8622 /*8623 * the address should be Qword aligned if 64bit write, Dword8624 * aligned if only send 32bit data low (discard data high)8625 */8626 if (write64bit)8627 BUG_ON(addr & 0x7);8628 else8629 BUG_ON(addr & 0x3);8630 amdgpu_ring_write(ring, lower_32_bits(addr));8631 amdgpu_ring_write(ring, upper_32_bits(addr));8632 amdgpu_ring_write(ring, lower_32_bits(seq));8633 amdgpu_ring_write(ring, upper_32_bits(seq));8634 amdgpu_ring_write(ring, 0);8635}8636 8637static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)8638{8639 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);8640 uint32_t seq = ring->fence_drv.sync_seq;8641 uint64_t addr = ring->fence_drv.gpu_addr;8642 8643 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),8644 upper_32_bits(addr), seq, 0xffffffff, 4);8645}8646 8647static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,8648 uint16_t pasid, uint32_t flush_type,8649 bool all_hub, uint8_t dst_sel)8650{8651 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));8652 amdgpu_ring_write(ring,8653 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |8654 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |8655 PACKET3_INVALIDATE_TLBS_PASID(pasid) |8656 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));8657}8658 8659static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,8660 unsigned int vmid, uint64_t pd_addr)8661{8662 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);8663 8664 /* compute doesn't have PFP */8665 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {8666 /* sync PFP to ME, otherwise we might get invalid PFP reads */8667 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));8668 amdgpu_ring_write(ring, 0x0);8669 }8670}8671 8672static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,8673 u64 seq, unsigned int flags)8674{8675 struct amdgpu_device *adev = ring->adev;8676 8677 /* we only allocate 32bit for each seq wb address */8678 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);8679 8680 /* write fence seq to the "addr" */8681 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));8682 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |8683 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));8684 amdgpu_ring_write(ring, lower_32_bits(addr));8685 amdgpu_ring_write(ring, upper_32_bits(addr));8686 amdgpu_ring_write(ring, lower_32_bits(seq));8687 8688 if (flags & AMDGPU_FENCE_FLAG_INT) {8689 /* set register to trigger INT */8690 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));8691 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |8692 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));8693 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));8694 amdgpu_ring_write(ring, 0);8695 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */8696 }8697}8698 8699static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)8700{8701 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));8702 amdgpu_ring_write(ring, 0);8703}8704 8705static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,8706 uint32_t flags)8707{8708 uint32_t dw2 = 0;8709 8710 if (ring->adev->gfx.mcbp)8711 gfx_v10_0_ring_emit_ce_meta(ring,8712 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);8713 8714 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */8715 if (flags & AMDGPU_HAVE_CTX_SWITCH) {8716 /* set load_global_config & load_global_uconfig */8717 dw2 |= 0x8001;8718 /* set load_cs_sh_regs */8719 dw2 |= 0x01000000;8720 /* set load_per_context_state & load_gfx_sh_regs for GFX */8721 dw2 |= 0x10002;8722 8723 /* set load_ce_ram if preamble presented */8724 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)8725 dw2 |= 0x10000000;8726 } else {8727 /* still load_ce_ram if this is the first time preamble presented8728 * although there is no context switch happens.8729 */8730 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)8731 dw2 |= 0x10000000;8732 }8733 8734 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));8735 amdgpu_ring_write(ring, dw2);8736 amdgpu_ring_write(ring, 0);8737}8738 8739static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,8740 uint64_t addr)8741{8742 unsigned int ret;8743 8744 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));8745 amdgpu_ring_write(ring, lower_32_bits(addr));8746 amdgpu_ring_write(ring, upper_32_bits(addr));8747 /* discard following DWs if *cond_exec_gpu_addr==0 */8748 amdgpu_ring_write(ring, 0);8749 ret = ring->wptr & ring->buf_mask;8750 /* patch dummy value later */8751 amdgpu_ring_write(ring, 0);8752 8753 return ret;8754}8755 8756static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)8757{8758 int i, r = 0;8759 struct amdgpu_device *adev = ring->adev;8760 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];8761 struct amdgpu_ring *kiq_ring = &kiq->ring;8762 unsigned long flags;8763 8764 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)8765 return -EINVAL;8766 8767 spin_lock_irqsave(&kiq->ring_lock, flags);8768 8769 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {8770 spin_unlock_irqrestore(&kiq->ring_lock, flags);8771 return -ENOMEM;8772 }8773 8774 /* assert preemption condition */8775 amdgpu_ring_set_preempt_cond_exec(ring, false);8776 8777 /* assert IB preemption, emit the trailing fence */8778 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,8779 ring->trail_fence_gpu_addr,8780 ++ring->trail_seq);8781 amdgpu_ring_commit(kiq_ring);8782 8783 spin_unlock_irqrestore(&kiq->ring_lock, flags);8784 8785 /* poll the trailing fence */8786 for (i = 0; i < adev->usec_timeout; i++) {8787 if (ring->trail_seq ==8788 le32_to_cpu(*(ring->trail_fence_cpu_addr)))8789 break;8790 udelay(1);8791 }8792 8793 if (i >= adev->usec_timeout) {8794 r = -EINVAL;8795 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);8796 }8797 8798 /* deassert preemption condition */8799 amdgpu_ring_set_preempt_cond_exec(ring, true);8800 return r;8801}8802 8803static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)8804{8805 struct amdgpu_device *adev = ring->adev;8806 struct v10_ce_ib_state ce_payload = {0};8807 uint64_t offset, ce_payload_gpu_addr;8808 void *ce_payload_cpu_addr;8809 int cnt;8810 8811 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;8812 8813 offset = offsetof(struct v10_gfx_meta_data, ce_payload);8814 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;8815 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;8816 8817 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));8818 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |8819 WRITE_DATA_DST_SEL(8) |8820 WR_CONFIRM) |8821 WRITE_DATA_CACHE_POLICY(0));8822 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));8823 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));8824 8825 if (resume)8826 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,8827 sizeof(ce_payload) >> 2);8828 else8829 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,8830 sizeof(ce_payload) >> 2);8831}8832 8833static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)8834{8835 struct amdgpu_device *adev = ring->adev;8836 struct v10_de_ib_state de_payload = {0};8837 uint64_t offset, gds_addr, de_payload_gpu_addr;8838 void *de_payload_cpu_addr;8839 int cnt;8840 8841 offset = offsetof(struct v10_gfx_meta_data, de_payload);8842 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;8843 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;8844 8845 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +8846 AMDGPU_CSA_SIZE - adev->gds.gds_size,8847 PAGE_SIZE);8848 8849 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);8850 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);8851 8852 cnt = (sizeof(de_payload) >> 2) + 4 - 2;8853 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));8854 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |8855 WRITE_DATA_DST_SEL(8) |8856 WR_CONFIRM) |8857 WRITE_DATA_CACHE_POLICY(0));8858 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));8859 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));8860 8861 if (resume)8862 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,8863 sizeof(de_payload) >> 2);8864 else8865 amdgpu_ring_write_multiple(ring, (void *)&de_payload,8866 sizeof(de_payload) >> 2);8867}8868 8869static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,8870 bool secure)8871{8872 uint32_t v = secure ? FRAME_TMZ : 0;8873 8874 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));8875 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));8876}8877 8878static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,8879 uint32_t reg_val_offs)8880{8881 struct amdgpu_device *adev = ring->adev;8882 8883 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));8884 amdgpu_ring_write(ring, 0 | /* src: register*/8885 (5 << 8) | /* dst: memory */8886 (1 << 20)); /* write confirm */8887 amdgpu_ring_write(ring, reg);8888 amdgpu_ring_write(ring, 0);8889 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +8890 reg_val_offs * 4));8891 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +8892 reg_val_offs * 4));8893}8894 8895static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,8896 uint32_t val)8897{8898 uint32_t cmd = 0;8899 8900 switch (ring->funcs->type) {8901 case AMDGPU_RING_TYPE_GFX:8902 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;8903 break;8904 case AMDGPU_RING_TYPE_KIQ:8905 cmd = (1 << 16); /* no inc addr */8906 break;8907 default:8908 cmd = WR_CONFIRM;8909 break;8910 }8911 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));8912 amdgpu_ring_write(ring, cmd);8913 amdgpu_ring_write(ring, reg);8914 amdgpu_ring_write(ring, 0);8915 amdgpu_ring_write(ring, val);8916}8917 8918static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,8919 uint32_t val, uint32_t mask)8920{8921 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);8922}8923 8924static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,8925 uint32_t reg0, uint32_t reg1,8926 uint32_t ref, uint32_t mask)8927{8928 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);8929 struct amdgpu_device *adev = ring->adev;8930 bool fw_version_ok = false;8931 8932 fw_version_ok = adev->gfx.cp_fw_write_wait;8933 8934 if (fw_version_ok)8935 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,8936 ref, mask, 0x20);8937 else8938 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,8939 ref, mask);8940}8941 8942static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,8943 unsigned int vmid)8944{8945 struct amdgpu_device *adev = ring->adev;8946 uint32_t value = 0;8947 8948 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);8949 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);8950 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);8951 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);8952 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);8953 WREG32_SOC15(GC, 0, mmSQ_CMD, value);8954 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);8955}8956 8957static void8958gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,8959 uint32_t me, uint32_t pipe,8960 enum amdgpu_interrupt_state state)8961{8962 uint32_t cp_int_cntl, cp_int_cntl_reg;8963 8964 if (!me) {8965 switch (pipe) {8966 case 0:8967 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);8968 break;8969 case 1:8970 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);8971 break;8972 default:8973 DRM_DEBUG("invalid pipe %d\n", pipe);8974 return;8975 }8976 } else {8977 DRM_DEBUG("invalid me %d\n", me);8978 return;8979 }8980 8981 switch (state) {8982 case AMDGPU_IRQ_STATE_DISABLE:8983 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);8984 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,8985 TIME_STAMP_INT_ENABLE, 0);8986 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);8987 break;8988 case AMDGPU_IRQ_STATE_ENABLE:8989 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);8990 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,8991 TIME_STAMP_INT_ENABLE, 1);8992 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);8993 break;8994 default:8995 break;8996 }8997}8998 8999static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,9000 int me, int pipe,9001 enum amdgpu_interrupt_state state)9002{9003 u32 mec_int_cntl, mec_int_cntl_reg;9004 9005 /*9006 * amdgpu controls only the first MEC. That's why this function only9007 * handles the setting of interrupts for this specific MEC. All other9008 * pipes' interrupts are set by amdkfd.9009 */9010 9011 if (me == 1) {9012 switch (pipe) {9013 case 0:9014 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);9015 break;9016 case 1:9017 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);9018 break;9019 case 2:9020 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);9021 break;9022 case 3:9023 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);9024 break;9025 default:9026 DRM_DEBUG("invalid pipe %d\n", pipe);9027 return;9028 }9029 } else {9030 DRM_DEBUG("invalid me %d\n", me);9031 return;9032 }9033 9034 switch (state) {9035 case AMDGPU_IRQ_STATE_DISABLE:9036 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);9037 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,9038 TIME_STAMP_INT_ENABLE, 0);9039 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);9040 break;9041 case AMDGPU_IRQ_STATE_ENABLE:9042 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);9043 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,9044 TIME_STAMP_INT_ENABLE, 1);9045 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);9046 break;9047 default:9048 break;9049 }9050}9051 9052static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,9053 struct amdgpu_irq_src *src,9054 unsigned int type,9055 enum amdgpu_interrupt_state state)9056{9057 switch (type) {9058 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:9059 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);9060 break;9061 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:9062 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);9063 break;9064 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:9065 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);9066 break;9067 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:9068 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);9069 break;9070 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:9071 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);9072 break;9073 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:9074 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);9075 break;9076 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:9077 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);9078 break;9079 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:9080 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);9081 break;9082 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:9083 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);9084 break;9085 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:9086 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);9087 break;9088 default:9089 break;9090 }9091 return 0;9092}9093 9094static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,9095 struct amdgpu_irq_src *source,9096 struct amdgpu_iv_entry *entry)9097{9098 int i;9099 u8 me_id, pipe_id, queue_id;9100 struct amdgpu_ring *ring;9101 9102 DRM_DEBUG("IH: CP EOP\n");9103 9104 me_id = (entry->ring_id & 0x0c) >> 2;9105 pipe_id = (entry->ring_id & 0x03) >> 0;9106 queue_id = (entry->ring_id & 0x70) >> 4;9107 9108 switch (me_id) {9109 case 0:9110 if (pipe_id == 0)9111 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);9112 else9113 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);9114 break;9115 case 1:9116 case 2:9117 for (i = 0; i < adev->gfx.num_compute_rings; i++) {9118 ring = &adev->gfx.compute_ring[i];9119 /* Per-queue interrupt is supported for MEC starting from VI.9120 * The interrupt can only be enabled/disabled per pipe instead9121 * of per queue.9122 */9123 if ((ring->me == me_id) &&9124 (ring->pipe == pipe_id) &&9125 (ring->queue == queue_id))9126 amdgpu_fence_process(ring);9127 }9128 break;9129 }9130 9131 return 0;9132}9133 9134static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,9135 struct amdgpu_irq_src *source,9136 unsigned int type,9137 enum amdgpu_interrupt_state state)9138{9139 u32 cp_int_cntl_reg, cp_int_cntl;9140 int i, j;9141 9142 switch (state) {9143 case AMDGPU_IRQ_STATE_DISABLE:9144 case AMDGPU_IRQ_STATE_ENABLE:9145 for (i = 0; i < adev->gfx.me.num_me; i++) {9146 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {9147 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);9148 9149 if (cp_int_cntl_reg) {9150 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);9151 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,9152 PRIV_REG_INT_ENABLE,9153 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);9154 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);9155 }9156 }9157 }9158 for (i = 0; i < adev->gfx.mec.num_mec; i++) {9159 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {9160 /* MECs start at 1 */9161 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);9162 9163 if (cp_int_cntl_reg) {9164 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);9165 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,9166 PRIV_REG_INT_ENABLE,9167 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);9168 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);9169 }9170 }9171 }9172 break;9173 default:9174 break;9175 }9176 9177 return 0;9178}9179 9180static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev,9181 struct amdgpu_irq_src *source,9182 unsigned type,9183 enum amdgpu_interrupt_state state)9184{9185 u32 cp_int_cntl_reg, cp_int_cntl;9186 int i, j;9187 9188 switch (state) {9189 case AMDGPU_IRQ_STATE_DISABLE:9190 case AMDGPU_IRQ_STATE_ENABLE:9191 for (i = 0; i < adev->gfx.me.num_me; i++) {9192 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {9193 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);9194 9195 if (cp_int_cntl_reg) {9196 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);9197 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,9198 OPCODE_ERROR_INT_ENABLE,9199 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);9200 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);9201 }9202 }9203 }9204 for (i = 0; i < adev->gfx.mec.num_mec; i++) {9205 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {9206 /* MECs start at 1 */9207 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);9208 9209 if (cp_int_cntl_reg) {9210 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);9211 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,9212 OPCODE_ERROR_INT_ENABLE,9213 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);9214 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);9215 }9216 }9217 }9218 break;9219 default:9220 break;9221 }9222 return 0;9223}9224 9225static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,9226 struct amdgpu_irq_src *source,9227 unsigned int type,9228 enum amdgpu_interrupt_state state)9229{9230 u32 cp_int_cntl_reg, cp_int_cntl;9231 int i, j;9232 9233 switch (state) {9234 case AMDGPU_IRQ_STATE_DISABLE:9235 case AMDGPU_IRQ_STATE_ENABLE:9236 for (i = 0; i < adev->gfx.me.num_me; i++) {9237 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {9238 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);9239 9240 if (cp_int_cntl_reg) {9241 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);9242 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,9243 PRIV_INSTR_INT_ENABLE,9244 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);9245 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);9246 }9247 }9248 }9249 break;9250 default:9251 break;9252 }9253 9254 return 0;9255}9256 9257static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,9258 struct amdgpu_iv_entry *entry)9259{9260 u8 me_id, pipe_id, queue_id;9261 struct amdgpu_ring *ring;9262 int i;9263 9264 me_id = (entry->ring_id & 0x0c) >> 2;9265 pipe_id = (entry->ring_id & 0x03) >> 0;9266 queue_id = (entry->ring_id & 0x70) >> 4;9267 9268 switch (me_id) {9269 case 0:9270 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {9271 ring = &adev->gfx.gfx_ring[i];9272 if (ring->me == me_id && ring->pipe == pipe_id &&9273 ring->queue == queue_id)9274 drm_sched_fault(&ring->sched);9275 }9276 break;9277 case 1:9278 case 2:9279 for (i = 0; i < adev->gfx.num_compute_rings; i++) {9280 ring = &adev->gfx.compute_ring[i];9281 if (ring->me == me_id && ring->pipe == pipe_id &&9282 ring->queue == queue_id)9283 drm_sched_fault(&ring->sched);9284 }9285 break;9286 default:9287 BUG();9288 }9289}9290 9291static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,9292 struct amdgpu_irq_src *source,9293 struct amdgpu_iv_entry *entry)9294{9295 DRM_ERROR("Illegal register access in command stream\n");9296 gfx_v10_0_handle_priv_fault(adev, entry);9297 return 0;9298}9299 9300static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev,9301 struct amdgpu_irq_src *source,9302 struct amdgpu_iv_entry *entry)9303{9304 DRM_ERROR("Illegal opcode in command stream \n");9305 gfx_v10_0_handle_priv_fault(adev, entry);9306 return 0;9307}9308 9309static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,9310 struct amdgpu_irq_src *source,9311 struct amdgpu_iv_entry *entry)9312{9313 DRM_ERROR("Illegal instruction in command stream\n");9314 gfx_v10_0_handle_priv_fault(adev, entry);9315 return 0;9316}9317 9318static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,9319 struct amdgpu_irq_src *src,9320 unsigned int type,9321 enum amdgpu_interrupt_state state)9322{9323 uint32_t tmp, target;9324 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);9325 9326 if (ring->me == 1)9327 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);9328 else9329 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);9330 target += ring->pipe;9331 9332 switch (type) {9333 case AMDGPU_CP_KIQ_IRQ_DRIVER0:9334 if (state == AMDGPU_IRQ_STATE_DISABLE) {9335 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);9336 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,9337 GENERIC2_INT_ENABLE, 0);9338 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);9339 9340 tmp = RREG32_SOC15_IP(GC, target);9341 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,9342 GENERIC2_INT_ENABLE, 0);9343 WREG32_SOC15_IP(GC, target, tmp);9344 } else {9345 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);9346 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,9347 GENERIC2_INT_ENABLE, 1);9348 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);9349 9350 tmp = RREG32_SOC15_IP(GC, target);9351 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,9352 GENERIC2_INT_ENABLE, 1);9353 WREG32_SOC15_IP(GC, target, tmp);9354 }9355 break;9356 default:9357 BUG(); /* kiq only support GENERIC2_INT now */9358 break;9359 }9360 return 0;9361}9362 9363static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,9364 struct amdgpu_irq_src *source,9365 struct amdgpu_iv_entry *entry)9366{9367 u8 me_id, pipe_id, queue_id;9368 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);9369 9370 me_id = (entry->ring_id & 0x0c) >> 2;9371 pipe_id = (entry->ring_id & 0x03) >> 0;9372 queue_id = (entry->ring_id & 0x70) >> 4;9373 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",9374 me_id, pipe_id, queue_id);9375 9376 amdgpu_fence_process(ring);9377 return 0;9378}9379 9380static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)9381{9382 const unsigned int gcr_cntl =9383 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |9384 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |9385 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |9386 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |9387 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |9388 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |9389 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |9390 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);9391 9392 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */9393 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));9394 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */9395 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */9396 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */9397 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */9398 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */9399 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */9400 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */9401}9402 9403static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)9404{9405 int i;9406 9407 /* Header itself is a NOP packet */9408 if (num_nop == 1) {9409 amdgpu_ring_write(ring, ring->funcs->nop);9410 return;9411 }9412 9413 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/9414 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));9415 9416 /* Header is at index 0, followed by num_nops - 1 NOP packet's */9417 for (i = 1; i < num_nop; i++)9418 amdgpu_ring_write(ring, ring->funcs->nop);9419}9420 9421static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)9422{9423 struct amdgpu_device *adev = ring->adev;9424 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];9425 struct amdgpu_ring *kiq_ring = &kiq->ring;9426 unsigned long flags;9427 u32 tmp;9428 u64 addr;9429 int r;9430 9431 if (amdgpu_sriov_vf(adev))9432 return -EINVAL;9433 9434 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)9435 return -EINVAL;9436 9437 spin_lock_irqsave(&kiq->ring_lock, flags);9438 9439 if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) {9440 spin_unlock_irqrestore(&kiq->ring_lock, flags);9441 return -ENOMEM;9442 }9443 9444 addr = amdgpu_bo_gpu_offset(ring->mqd_obj) +9445 offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active);9446 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);9447 if (ring->pipe == 0)9448 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue);9449 else9450 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue);9451 9452 gfx_v10_0_ring_emit_wreg(kiq_ring,9453 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp);9454 gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0,9455 lower_32_bits(addr), upper_32_bits(addr),9456 0, 1, 0x20);9457 gfx_v10_0_ring_emit_reg_wait(kiq_ring,9458 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);9459 kiq->pmf->kiq_map_queues(kiq_ring, ring);9460 amdgpu_ring_commit(kiq_ring);9461 9462 spin_unlock_irqrestore(&kiq->ring_lock, flags);9463 9464 r = amdgpu_ring_test_ring(kiq_ring);9465 if (r)9466 return r;9467 9468 r = amdgpu_bo_reserve(ring->mqd_obj, false);9469 if (unlikely(r != 0)) {9470 DRM_ERROR("fail to resv mqd_obj\n");9471 return r;9472 }9473 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);9474 if (!r) {9475 r = gfx_v10_0_kgq_init_queue(ring, true);9476 amdgpu_bo_kunmap(ring->mqd_obj);9477 ring->mqd_ptr = NULL;9478 }9479 amdgpu_bo_unreserve(ring->mqd_obj);9480 if (r) {9481 DRM_ERROR("fail to unresv mqd_obj\n");9482 return r;9483 }9484 9485 return amdgpu_ring_test_ring(ring);9486}9487 9488static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,9489 unsigned int vmid)9490{9491 struct amdgpu_device *adev = ring->adev;9492 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];9493 struct amdgpu_ring *kiq_ring = &kiq->ring;9494 unsigned long flags;9495 int i, r;9496 9497 if (amdgpu_sriov_vf(adev))9498 return -EINVAL;9499 9500 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)9501 return -EINVAL;9502 9503 spin_lock_irqsave(&kiq->ring_lock, flags);9504 9505 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {9506 spin_unlock_irqrestore(&kiq->ring_lock, flags);9507 return -ENOMEM;9508 }9509 9510 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,9511 0, 0);9512 amdgpu_ring_commit(kiq_ring);9513 spin_unlock_irqrestore(&kiq->ring_lock, flags);9514 9515 r = amdgpu_ring_test_ring(kiq_ring);9516 if (r)9517 return r;9518 9519 /* make sure dequeue is complete*/9520 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);9521 mutex_lock(&adev->srbm_mutex);9522 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);9523 for (i = 0; i < adev->usec_timeout; i++) {9524 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))9525 break;9526 udelay(1);9527 }9528 if (i >= adev->usec_timeout)9529 r = -ETIMEDOUT;9530 nv_grbm_select(adev, 0, 0, 0, 0);9531 mutex_unlock(&adev->srbm_mutex);9532 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);9533 if (r) {9534 dev_err(adev->dev, "fail to wait on hqd deactivate\n");9535 return r;9536 }9537 9538 r = amdgpu_bo_reserve(ring->mqd_obj, false);9539 if (unlikely(r != 0)) {9540 dev_err(adev->dev, "fail to resv mqd_obj\n");9541 return r;9542 }9543 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);9544 if (!r) {9545 r = gfx_v10_0_kcq_init_queue(ring, true);9546 amdgpu_bo_kunmap(ring->mqd_obj);9547 ring->mqd_ptr = NULL;9548 }9549 amdgpu_bo_unreserve(ring->mqd_obj);9550 if (r) {9551 dev_err(adev->dev, "fail to unresv mqd_obj\n");9552 return r;9553 }9554 9555 spin_lock_irqsave(&kiq->ring_lock, flags);9556 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {9557 spin_unlock_irqrestore(&kiq->ring_lock, flags);9558 return -ENOMEM;9559 }9560 kiq->pmf->kiq_map_queues(kiq_ring, ring);9561 amdgpu_ring_commit(kiq_ring);9562 spin_unlock_irqrestore(&kiq->ring_lock, flags);9563 9564 r = amdgpu_ring_test_ring(kiq_ring);9565 if (r)9566 return r;9567 9568 return amdgpu_ring_test_ring(ring);9569}9570 9571static void gfx_v10_ip_print(void *handle, struct drm_printer *p)9572{9573 struct amdgpu_device *adev = (struct amdgpu_device *)handle;9574 uint32_t i, j, k, reg, index = 0;9575 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);9576 9577 if (!adev->gfx.ip_dump_core)9578 return;9579 9580 for (i = 0; i < reg_count; i++)9581 drm_printf(p, "%-50s \t 0x%08x\n",9582 gc_reg_list_10_1[i].reg_name,9583 adev->gfx.ip_dump_core[i]);9584 9585 /* print compute queue registers for all instances */9586 if (!adev->gfx.ip_dump_compute_queues)9587 return;9588 9589 reg_count = ARRAY_SIZE(gc_cp_reg_list_10);9590 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",9591 adev->gfx.mec.num_mec,9592 adev->gfx.mec.num_pipe_per_mec,9593 adev->gfx.mec.num_queue_per_pipe);9594 9595 for (i = 0; i < adev->gfx.mec.num_mec; i++) {9596 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {9597 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {9598 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);9599 for (reg = 0; reg < reg_count; reg++) {9600 drm_printf(p, "%-50s \t 0x%08x\n",9601 gc_cp_reg_list_10[reg].reg_name,9602 adev->gfx.ip_dump_compute_queues[index + reg]);9603 }9604 index += reg_count;9605 }9606 }9607 }9608 9609 /* print gfx queue registers for all instances */9610 if (!adev->gfx.ip_dump_gfx_queues)9611 return;9612 9613 index = 0;9614 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);9615 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",9616 adev->gfx.me.num_me,9617 adev->gfx.me.num_pipe_per_me,9618 adev->gfx.me.num_queue_per_pipe);9619 9620 for (i = 0; i < adev->gfx.me.num_me; i++) {9621 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {9622 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {9623 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);9624 for (reg = 0; reg < reg_count; reg++) {9625 drm_printf(p, "%-50s \t 0x%08x\n",9626 gc_gfx_queue_reg_list_10[reg].reg_name,9627 adev->gfx.ip_dump_gfx_queues[index + reg]);9628 }9629 index += reg_count;9630 }9631 }9632 }9633}9634 9635static void gfx_v10_ip_dump(void *handle)9636{9637 struct amdgpu_device *adev = (struct amdgpu_device *)handle;9638 uint32_t i, j, k, reg, index = 0;9639 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);9640 9641 if (!adev->gfx.ip_dump_core)9642 return;9643 9644 amdgpu_gfx_off_ctrl(adev, false);9645 for (i = 0; i < reg_count; i++)9646 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));9647 amdgpu_gfx_off_ctrl(adev, true);9648 9649 /* dump compute queue registers for all instances */9650 if (!adev->gfx.ip_dump_compute_queues)9651 return;9652 9653 reg_count = ARRAY_SIZE(gc_cp_reg_list_10);9654 amdgpu_gfx_off_ctrl(adev, false);9655 mutex_lock(&adev->srbm_mutex);9656 for (i = 0; i < adev->gfx.mec.num_mec; i++) {9657 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {9658 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {9659 /* ME0 is for GFX so start from 1 for CP */9660 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);9661 9662 for (reg = 0; reg < reg_count; reg++) {9663 adev->gfx.ip_dump_compute_queues[index + reg] =9664 RREG32(SOC15_REG_ENTRY_OFFSET(9665 gc_cp_reg_list_10[reg]));9666 }9667 index += reg_count;9668 }9669 }9670 }9671 nv_grbm_select(adev, 0, 0, 0, 0);9672 mutex_unlock(&adev->srbm_mutex);9673 amdgpu_gfx_off_ctrl(adev, true);9674 9675 /* dump gfx queue registers for all instances */9676 if (!adev->gfx.ip_dump_gfx_queues)9677 return;9678 9679 index = 0;9680 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);9681 amdgpu_gfx_off_ctrl(adev, false);9682 mutex_lock(&adev->srbm_mutex);9683 for (i = 0; i < adev->gfx.me.num_me; i++) {9684 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {9685 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {9686 nv_grbm_select(adev, i, j, k, 0);9687 9688 for (reg = 0; reg < reg_count; reg++) {9689 adev->gfx.ip_dump_gfx_queues[index + reg] =9690 RREG32(SOC15_REG_ENTRY_OFFSET(9691 gc_gfx_queue_reg_list_10[reg]));9692 }9693 index += reg_count;9694 }9695 }9696 }9697 nv_grbm_select(adev, 0, 0, 0, 0);9698 mutex_unlock(&adev->srbm_mutex);9699 amdgpu_gfx_off_ctrl(adev, true);9700}9701 9702static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {9703 .name = "gfx_v10_0",9704 .early_init = gfx_v10_0_early_init,9705 .late_init = gfx_v10_0_late_init,9706 .sw_init = gfx_v10_0_sw_init,9707 .sw_fini = gfx_v10_0_sw_fini,9708 .hw_init = gfx_v10_0_hw_init,9709 .hw_fini = gfx_v10_0_hw_fini,9710 .suspend = gfx_v10_0_suspend,9711 .resume = gfx_v10_0_resume,9712 .is_idle = gfx_v10_0_is_idle,9713 .wait_for_idle = gfx_v10_0_wait_for_idle,9714 .soft_reset = gfx_v10_0_soft_reset,9715 .set_clockgating_state = gfx_v10_0_set_clockgating_state,9716 .set_powergating_state = gfx_v10_0_set_powergating_state,9717 .get_clockgating_state = gfx_v10_0_get_clockgating_state,9718 .dump_ip_state = gfx_v10_ip_dump,9719 .print_ip_state = gfx_v10_ip_print,9720};9721 9722static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {9723 .type = AMDGPU_RING_TYPE_GFX,9724 .align_mask = 0xff,9725 .nop = PACKET3(PACKET3_NOP, 0x3FFF),9726 .support_64bit_ptrs = true,9727 .secure_submission_supported = true,9728 .get_rptr = gfx_v10_0_ring_get_rptr_gfx,9729 .get_wptr = gfx_v10_0_ring_get_wptr_gfx,9730 .set_wptr = gfx_v10_0_ring_set_wptr_gfx,9731 .emit_frame_size = /* totally 242 maximum if 16 IBs */9732 5 + /* COND_EXEC */9733 7 + /* PIPELINE_SYNC */9734 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +9735 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +9736 4 + /* VM_FLUSH */9737 8 + /* FENCE for VM_FLUSH */9738 20 + /* GDS switch */9739 4 + /* double SWITCH_BUFFER,9740 * the first COND_EXEC jump to the place9741 * just prior to this double SWITCH_BUFFER9742 */9743 5 + /* COND_EXEC */9744 7 + /* HDP_flush */9745 4 + /* VGT_flush */9746 14 + /* CE_META */9747 31 + /* DE_META */9748 3 + /* CNTX_CTRL */9749 5 + /* HDP_INVL */9750 8 + 8 + /* FENCE x2 */9751 2 + /* SWITCH_BUFFER */9752 8, /* gfx_v10_0_emit_mem_sync */9753 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */9754 .emit_ib = gfx_v10_0_ring_emit_ib_gfx,9755 .emit_fence = gfx_v10_0_ring_emit_fence,9756 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,9757 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,9758 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,9759 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,9760 .test_ring = gfx_v10_0_ring_test_ring,9761 .test_ib = gfx_v10_0_ring_test_ib,9762 .insert_nop = gfx_v10_ring_insert_nop,9763 .pad_ib = amdgpu_ring_generic_pad_ib,9764 .emit_switch_buffer = gfx_v10_0_ring_emit_sb,9765 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,9766 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,9767 .preempt_ib = gfx_v10_0_ring_preempt_ib,9768 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,9769 .emit_wreg = gfx_v10_0_ring_emit_wreg,9770 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,9771 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,9772 .soft_recovery = gfx_v10_0_ring_soft_recovery,9773 .emit_mem_sync = gfx_v10_0_emit_mem_sync,9774 .reset = gfx_v10_0_reset_kgq,9775};9776 9777static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {9778 .type = AMDGPU_RING_TYPE_COMPUTE,9779 .align_mask = 0xff,9780 .nop = PACKET3(PACKET3_NOP, 0x3FFF),9781 .support_64bit_ptrs = true,9782 .get_rptr = gfx_v10_0_ring_get_rptr_compute,9783 .get_wptr = gfx_v10_0_ring_get_wptr_compute,9784 .set_wptr = gfx_v10_0_ring_set_wptr_compute,9785 .emit_frame_size =9786 20 + /* gfx_v10_0_ring_emit_gds_switch */9787 7 + /* gfx_v10_0_ring_emit_hdp_flush */9788 5 + /* hdp invalidate */9789 7 + /* gfx_v10_0_ring_emit_pipeline_sync */9790 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +9791 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +9792 2 + /* gfx_v10_0_ring_emit_vm_flush */9793 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */9794 8, /* gfx_v10_0_emit_mem_sync */9795 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */9796 .emit_ib = gfx_v10_0_ring_emit_ib_compute,9797 .emit_fence = gfx_v10_0_ring_emit_fence,9798 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,9799 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,9800 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,9801 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,9802 .test_ring = gfx_v10_0_ring_test_ring,9803 .test_ib = gfx_v10_0_ring_test_ib,9804 .insert_nop = gfx_v10_ring_insert_nop,9805 .pad_ib = amdgpu_ring_generic_pad_ib,9806 .emit_wreg = gfx_v10_0_ring_emit_wreg,9807 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,9808 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,9809 .soft_recovery = gfx_v10_0_ring_soft_recovery,9810 .emit_mem_sync = gfx_v10_0_emit_mem_sync,9811 .reset = gfx_v10_0_reset_kcq,9812};9813 9814static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {9815 .type = AMDGPU_RING_TYPE_KIQ,9816 .align_mask = 0xff,9817 .nop = PACKET3(PACKET3_NOP, 0x3FFF),9818 .support_64bit_ptrs = true,9819 .get_rptr = gfx_v10_0_ring_get_rptr_compute,9820 .get_wptr = gfx_v10_0_ring_get_wptr_compute,9821 .set_wptr = gfx_v10_0_ring_set_wptr_compute,9822 .emit_frame_size =9823 20 + /* gfx_v10_0_ring_emit_gds_switch */9824 7 + /* gfx_v10_0_ring_emit_hdp_flush */9825 5 + /*hdp invalidate */9826 7 + /* gfx_v10_0_ring_emit_pipeline_sync */9827 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +9828 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +9829 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */9830 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */9831 .emit_ib = gfx_v10_0_ring_emit_ib_compute,9832 .emit_fence = gfx_v10_0_ring_emit_fence_kiq,9833 .test_ring = gfx_v10_0_ring_test_ring,9834 .test_ib = gfx_v10_0_ring_test_ib,9835 .insert_nop = amdgpu_ring_insert_nop,9836 .pad_ib = amdgpu_ring_generic_pad_ib,9837 .emit_rreg = gfx_v10_0_ring_emit_rreg,9838 .emit_wreg = gfx_v10_0_ring_emit_wreg,9839 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,9840 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,9841};9842 9843static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)9844{9845 int i;9846 9847 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;9848 9849 for (i = 0; i < adev->gfx.num_gfx_rings; i++)9850 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;9851 9852 for (i = 0; i < adev->gfx.num_compute_rings; i++)9853 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;9854}9855 9856static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {9857 .set = gfx_v10_0_set_eop_interrupt_state,9858 .process = gfx_v10_0_eop_irq,9859};9860 9861static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {9862 .set = gfx_v10_0_set_priv_reg_fault_state,9863 .process = gfx_v10_0_priv_reg_irq,9864};9865 9866static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = {9867 .set = gfx_v10_0_set_bad_op_fault_state,9868 .process = gfx_v10_0_bad_op_irq,9869};9870 9871static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {9872 .set = gfx_v10_0_set_priv_inst_fault_state,9873 .process = gfx_v10_0_priv_inst_irq,9874};9875 9876static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {9877 .set = gfx_v10_0_kiq_set_interrupt_state,9878 .process = gfx_v10_0_kiq_irq,9879};9880 9881static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)9882{9883 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;9884 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;9885 9886 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;9887 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;9888 9889 adev->gfx.priv_reg_irq.num_types = 1;9890 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;9891 9892 adev->gfx.bad_op_irq.num_types = 1;9893 adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs;9894 9895 adev->gfx.priv_inst_irq.num_types = 1;9896 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;9897}9898 9899static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)9900{9901 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {9902 case IP_VERSION(10, 1, 10):9903 case IP_VERSION(10, 1, 1):9904 case IP_VERSION(10, 1, 3):9905 case IP_VERSION(10, 1, 4):9906 case IP_VERSION(10, 3, 2):9907 case IP_VERSION(10, 3, 1):9908 case IP_VERSION(10, 3, 4):9909 case IP_VERSION(10, 3, 5):9910 case IP_VERSION(10, 3, 6):9911 case IP_VERSION(10, 3, 3):9912 case IP_VERSION(10, 3, 7):9913 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;9914 break;9915 case IP_VERSION(10, 1, 2):9916 case IP_VERSION(10, 3, 0):9917 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;9918 break;9919 default:9920 break;9921 }9922}9923 9924static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)9925{9926 unsigned int total_cu = adev->gfx.config.max_cu_per_sh *9927 adev->gfx.config.max_sh_per_se *9928 adev->gfx.config.max_shader_engines;9929 9930 adev->gds.gds_size = 0x10000;9931 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;9932 adev->gds.gws_size = 64;9933 adev->gds.oa_size = 16;9934}9935 9936static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)9937{9938 /* set gfx eng mqd */9939 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =9940 sizeof(struct v10_gfx_mqd);9941 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =9942 gfx_v10_0_gfx_mqd_init;9943 /* set compute eng mqd */9944 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =9945 sizeof(struct v10_compute_mqd);9946 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =9947 gfx_v10_0_compute_mqd_init;9948}9949 9950static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,9951 u32 bitmap)9952{9953 u32 data;9954 9955 if (!bitmap)9956 return;9957 9958 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;9959 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;9960 9961 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);9962}9963 9964static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)9965{9966 u32 disabled_mask =9967 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);9968 u32 efuse_setting = 0;9969 u32 vbios_setting = 0;9970 9971 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);9972 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;9973 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;9974 9975 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);9976 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;9977 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;9978 9979 disabled_mask |= efuse_setting | vbios_setting;9980 9981 return (~disabled_mask);9982}9983 9984static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)9985{9986 u32 wgp_idx, wgp_active_bitmap;9987 u32 cu_bitmap_per_wgp, cu_active_bitmap;9988 9989 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);9990 cu_active_bitmap = 0;9991 9992 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {9993 /* if there is one WGP enabled, it means 2 CUs will be enabled */9994 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);9995 if (wgp_active_bitmap & (1 << wgp_idx))9996 cu_active_bitmap |= cu_bitmap_per_wgp;9997 }9998 9999 return cu_active_bitmap;10000}10001 10002static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,10003 struct amdgpu_cu_info *cu_info)10004{10005 int i, j, k, counter, active_cu_number = 0;10006 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;10007 unsigned int disable_masks[4 * 2];10008 10009 if (!adev || !cu_info)10010 return -EINVAL;10011 10012 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);10013 10014 mutex_lock(&adev->grbm_idx_mutex);10015 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {10016 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {10017 bitmap = i * adev->gfx.config.max_sh_per_se + j;10018 if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==10019 IP_VERSION(10, 3, 0)) ||10020 (amdgpu_ip_version(adev, GC_HWIP, 0) ==10021 IP_VERSION(10, 3, 3)) ||10022 (amdgpu_ip_version(adev, GC_HWIP, 0) ==10023 IP_VERSION(10, 3, 6)) ||10024 (amdgpu_ip_version(adev, GC_HWIP, 0) ==10025 IP_VERSION(10, 3, 7))) &&10026 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))10027 continue;10028 mask = 1;10029 ao_bitmap = 0;10030 counter = 0;10031 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);10032 if (i < 4 && j < 2)10033 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(10034 adev, disable_masks[i * 2 + j]);10035 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);10036 cu_info->bitmap[0][i][j] = bitmap;10037 10038 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {10039 if (bitmap & mask) {10040 if (counter < adev->gfx.config.max_cu_per_sh)10041 ao_bitmap |= mask;10042 counter++;10043 }10044 mask <<= 1;10045 }10046 active_cu_number += counter;10047 if (i < 2 && j < 2)10048 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));10049 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;10050 }10051 }10052 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);10053 mutex_unlock(&adev->grbm_idx_mutex);10054 10055 cu_info->number = active_cu_number;10056 cu_info->ao_cu_mask = ao_cu_mask;10057 cu_info->simd_per_cu = NUM_SIMD_PER_CU;10058 10059 return 0;10060}10061 10062static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)10063{10064 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;10065 10066 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);10067 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;10068 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;10069 10070 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);10071 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;10072 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;10073 10074 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *10075 adev->gfx.config.max_shader_engines);10076 disabled_sa = efuse_setting | vbios_setting;10077 disabled_sa &= max_sa_mask;10078 10079 return disabled_sa;10080}10081 10082static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)10083{10084 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;10085 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;10086 10087 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);10088 10089 max_sa_per_se = adev->gfx.config.max_sh_per_se;10090 max_sa_per_se_mask = (1 << max_sa_per_se) - 1;10091 max_shader_engines = adev->gfx.config.max_shader_engines;10092 10093 for (se_index = 0; max_shader_engines > se_index; se_index++) {10094 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);10095 disabled_sa_per_se &= max_sa_per_se_mask;10096 if (disabled_sa_per_se == max_sa_per_se_mask) {10097 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);10098 break;10099 }10100 }10101}10102 10103static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)10104{10105 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,10106 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |10107 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |10108 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));10109 10110 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);10111 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,10112 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |10113 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |10114 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |10115 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));10116 10117 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,10118 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |10119 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |10120 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));10121 10122 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);10123 10124 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,10125 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));10126}10127 10128const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {10129 .type = AMD_IP_BLOCK_TYPE_GFX,10130 .major = 10,10131 .minor = 0,10132 .rev = 0,10133 .funcs = &gfx_v10_0_ip_funcs,10134};10135