705 lines · c
1/*2 * Copyright 2019 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include "amdgpu.h"25#include "gfxhub_v2_1.h"26 27#include "gc/gc_10_3_0_offset.h"28#include "gc/gc_10_3_0_sh_mask.h"29#include "gc/gc_10_3_0_default.h"30#include "navi10_enum.h"31 32#include "soc15_common.h"33 34#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP 0x16f835#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP_BASE_IDX 036 37static const char * const gfxhub_client_ids[] = {38 "CB/DB",39 "Reserved",40 "GE1",41 "GE2",42 "CPF",43 "CPC",44 "CPG",45 "RLC",46 "TCP",47 "SQC (inst)",48 "SQC (data)",49 "SQG",50 "Reserved",51 "SDMA0",52 "SDMA1",53 "GCR",54 "SDMA2",55 "SDMA3",56};57 58static uint32_t gfxhub_v2_1_get_invalidate_req(unsigned int vmid,59 uint32_t flush_type)60{61 u32 req = 0;62 63 /* invalidate using legacy mode on vmid*/64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,65 PER_VMID_INVALIDATE_REQ, 1 << vmid);66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);70 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);71 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);72 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,73 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);74 75 return req;76}77 78static void79gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev,80 uint32_t status)81{82 u32 cid = REG_GET_FIELD(status,83 GCVM_L2_PROTECTION_FAULT_STATUS, CID);84 85 dev_err(adev->dev,86 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",87 status);88 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",89 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],90 cid);91 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",92 REG_GET_FIELD(status,93 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));94 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",95 REG_GET_FIELD(status,96 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));97 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",98 REG_GET_FIELD(status,99 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));100 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",101 REG_GET_FIELD(status,102 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));103 dev_err(adev->dev, "\t RW: 0x%lx\n",104 REG_GET_FIELD(status,105 GCVM_L2_PROTECTION_FAULT_STATUS, RW));106}107 108static u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)109{110 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);111 112 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;113 base <<= 24;114 115 return base;116}117 118static u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev)119{120 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;121}122 123static void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,124 uint64_t page_table_base)125{126 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];127 128 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,129 hub->ctx_addr_distance * vmid,130 lower_32_bits(page_table_base));131 132 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,133 hub->ctx_addr_distance * vmid,134 upper_32_bits(page_table_base));135}136 137static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev)138{139 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);140 141 gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base);142 143 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,144 (u32)(adev->gmc.gart_start >> 12));145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,146 (u32)(adev->gmc.gart_start >> 44));147 148 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,149 (u32)(adev->gmc.gart_end >> 12));150 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,151 (u32)(adev->gmc.gart_end >> 44));152}153 154static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)155{156 uint64_t value;157 158 if (amdgpu_sriov_vf(adev))159 return;160 161 /* Program the AGP BAR */162 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);163 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);164 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);165 166 /* Program the system aperture low logical page number. */167 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,168 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);169 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,170 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);171 172 /* Set default page address. */173 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);174 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,175 (u32)(value >> 12));176 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,177 (u32)(value >> 44));178 179 /* Program "protection fault". */180 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,181 (u32)(adev->dummy_page_addr >> 12));182 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,183 (u32)((u64)adev->dummy_page_addr >> 44));184 185 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,186 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);187}188 189 190static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev)191{192 uint32_t tmp;193 194 /* Setup TLB control */195 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);196 197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,200 ENABLE_ADVANCED_DRIVER_MODEL, 1);201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,202 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);203 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,204 MTYPE, MTYPE_UC); /* UC, uncached */205 206 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);207}208 209static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev)210{211 uint32_t tmp;212 213 /* These registers are not accessible to VF-SRIOV.214 * The PF will program them instead.215 */216 if (amdgpu_sriov_vf(adev))217 return;218 219 /* Setup L2 cache */220 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);222 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,224 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);225 /* XXX for emulation, Refer to closed source code.*/226 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,227 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);228 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);230 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);231 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);232 233 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);234 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);236 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);237 238 tmp = mmGCVM_L2_CNTL3_DEFAULT;239 if (adev->gmc.translate_further) {240 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);241 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,242 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);243 } else {244 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);245 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,246 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);247 }248 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);249 250 tmp = mmGCVM_L2_CNTL4_DEFAULT;251 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);252 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);253 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);254 255 tmp = mmGCVM_L2_CNTL5_DEFAULT;256 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);257 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);258}259 260static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev)261{262 uint32_t tmp;263 264 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);265 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);266 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);267 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,268 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);269 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);270}271 272static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)273{274 /* These registers are not accessible to VF-SRIOV.275 * The PF will program them instead.276 */277 if (amdgpu_sriov_vf(adev))278 return;279 280 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,281 0xFFFFFFFF);282 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,283 0x0000000F);284 285 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,286 0);287 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,288 0);289 290 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);291 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);292 293}294 295static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)296{297 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];298 int i;299 uint32_t tmp;300 301 for (i = 0; i <= 14; i++) {302 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);303 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);304 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,305 adev->vm_manager.num_level);306 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,307 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);308 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,309 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);310 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,311 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);312 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,313 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);314 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,315 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);316 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,317 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);318 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,319 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);320 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,321 PAGE_TABLE_BLOCK_SIZE,322 adev->vm_manager.block_size - 9);323 /* Send no-retry XNACK on fault to suppress VM fault storm. */324 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,325 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,326 !adev->gmc.noretry);327 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,328 i * hub->ctx_distance, tmp);329 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,330 i * hub->ctx_addr_distance, 0);331 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,332 i * hub->ctx_addr_distance, 0);333 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,334 i * hub->ctx_addr_distance,335 lower_32_bits(adev->vm_manager.max_pfn - 1));336 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,337 i * hub->ctx_addr_distance,338 upper_32_bits(adev->vm_manager.max_pfn - 1));339 }340 341 hub->vm_cntx_cntl = tmp;342}343 344static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev)345{346 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];347 unsigned int i;348 349 for (i = 0 ; i < 18; ++i) {350 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,351 i * hub->eng_addr_distance, 0xffffffff);352 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,353 i * hub->eng_addr_distance, 0x1f);354 }355}356 357static int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev)358{359 if (amdgpu_sriov_vf(adev)) {360 /*361 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are362 * VF copy registers so vbios post doesn't program them, for363 * SRIOV driver need to program them364 */365 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE,366 adev->gmc.vram_start >> 24);367 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP,368 adev->gmc.vram_end >> 24);369 }370 371 /* GART Enable. */372 gfxhub_v2_1_init_gart_aperture_regs(adev);373 gfxhub_v2_1_init_system_aperture_regs(adev);374 gfxhub_v2_1_init_tlb_regs(adev);375 gfxhub_v2_1_init_cache_regs(adev);376 377 gfxhub_v2_1_enable_system_domain(adev);378 gfxhub_v2_1_disable_identity_aperture(adev);379 gfxhub_v2_1_setup_vmid_config(adev);380 gfxhub_v2_1_program_invalidation(adev);381 382 return 0;383}384 385static void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)386{387 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];388 u32 tmp;389 u32 i;390 391 /* Disable all tables */392 for (i = 0; i < 16; i++)393 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL,394 i * hub->ctx_distance, 0);395 396 /* Setup TLB control */397 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);398 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);399 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,400 ENABLE_ADVANCED_DRIVER_MODEL, 0);401 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);402 403 if (amdgpu_sriov_vf(adev))404 return;405 406 /* Setup L2 cache */407 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);408 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);409}410 411/**412 * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling413 *414 * @adev: amdgpu_device pointer415 * @value: true redirects VM faults to the default page416 */417static void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,418 bool value)419{420 u32 tmp;421 422 /* These registers are not accessible to VF-SRIOV.423 * The PF will program them instead.424 */425 if (amdgpu_sriov_vf(adev))426 return;427 428 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);429 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,430 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);431 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,432 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);433 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,434 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);435 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,436 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);437 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,438 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,439 value);440 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,441 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);442 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,443 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);444 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,445 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);446 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,447 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);448 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,449 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);450 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,451 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);452 if (!value) {453 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,454 CRASH_ON_NO_RETRY_FAULT, 1);455 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,456 CRASH_ON_RETRY_FAULT, 1);457 }458 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);459}460 461static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = {462 .print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status,463 .get_invalidate_req = gfxhub_v2_1_get_invalidate_req,464};465 466static void gfxhub_v2_1_init(struct amdgpu_device *adev)467{468 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];469 470 hub->ctx0_ptb_addr_lo32 =471 SOC15_REG_OFFSET(GC, 0,472 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);473 hub->ctx0_ptb_addr_hi32 =474 SOC15_REG_OFFSET(GC, 0,475 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);476 hub->vm_inv_eng0_sem =477 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);478 hub->vm_inv_eng0_req =479 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);480 hub->vm_inv_eng0_ack =481 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);482 hub->vm_context0_cntl =483 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);484 hub->vm_l2_pro_fault_status =485 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);486 hub->vm_l2_pro_fault_cntl =487 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);488 489 hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL;490 hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -491 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;492 hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ -493 mmGCVM_INVALIDATE_ENG0_REQ;494 hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -495 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;496 497 hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |498 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |499 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |500 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |501 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |502 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |503 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;504 505 hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs;506}507 508static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)509{510 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL);511 u32 max_region =512 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);513 u32 max_num_physical_nodes = 0;514 u32 max_physical_node_id = 0;515 516 switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {517 case IP_VERSION(4, 8, 0):518 max_num_physical_nodes = 4;519 max_physical_node_id = 3;520 break;521 default:522 return -EINVAL;523 }524 525 /* PF_MAX_REGION=0 means xgmi is disabled */526 if (max_region) {527 adev->gmc.xgmi.num_physical_nodes = max_region + 1;528 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)529 return -EINVAL;530 531 adev->gmc.xgmi.physical_node_id =532 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);533 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)534 return -EINVAL;535 536 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(537 RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE),538 GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;539 }540 541 return 0;542}543 544static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)545{546 int i;547 u32 tmp = 0, disabled_sa = 0;548 u32 efuse_setting, vbios_setting;549 550 u32 max_sa_mask = amdgpu_gfx_create_bitmask(551 adev->gfx.config.max_sh_per_se *552 adev->gfx.config.max_shader_engines);553 554 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {555 case IP_VERSION(10, 3, 1):556 case IP_VERSION(10, 3, 3):557 /* Get SA disabled bitmap from eFuse setting */558 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);559 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;560 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;561 562 /* Get SA disabled bitmap from VBIOS setting */563 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);564 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;565 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;566 567 disabled_sa |= efuse_setting | vbios_setting;568 /* Make sure not to report harvested SAs beyond the max SA count */569 disabled_sa &= max_sa_mask;570 571 for (i = 0; disabled_sa > 0; i++) {572 if (disabled_sa & 1)573 tmp |= 0x3 << (i * 2);574 disabled_sa >>= 1;575 }576 disabled_sa = tmp;577 578 WREG32_SOC15(GC, 0, mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa);579 break;580 default:581 break;582 }583}584 585static void gfxhub_v2_1_save_regs(struct amdgpu_device *adev)586{587 int i;588 589 adev->gmc.VM_L2_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);590 adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);591 adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL);592 adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32);593 adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32);594 adev->gmc.VM_L2_PROTECTION_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);595 adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2);596 adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3);597 adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4);598 adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32);599 adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32);600 adev->gmc.VM_DEBUG = RREG32_SOC15(GC, 0, mmGCVM_DEBUG);601 adev->gmc.VM_L2_MM_GROUP_RT_CLASSES = RREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES);602 adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID);603 adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2 = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2);604 adev->gmc.VM_L2_CACHE_PARITY_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL);605 adev->gmc.VM_L2_IH_LOG_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL);606 607 for (i = 0; i <= 15; i++) {608 adev->gmc.VM_CONTEXT_CNTL[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i);609 adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2);610 adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, i * 2);611 adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, i * 2);612 adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, i * 2);613 adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, i * 2);614 adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, i * 2);615 }616 617 adev->gmc.MC_VM_MX_L1_TLB_CNTL = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);618}619 620static void gfxhub_v2_1_restore_regs(struct amdgpu_device *adev)621{622 int i;623 624 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, adev->gmc.VM_L2_CNTL);625 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, adev->gmc.VM_L2_CNTL2);626 WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL, adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL);627 WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32, adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32);628 WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32, adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32);629 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL);630 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2);631 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3, adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3);632 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4, adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4);633 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32, adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32);634 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32, adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32);635 WREG32_SOC15(GC, 0, mmGCVM_DEBUG, adev->gmc.VM_DEBUG);636 WREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES, adev->gmc.VM_L2_MM_GROUP_RT_CLASSES);637 WREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID, adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID);638 WREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2, adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2);639 WREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL, adev->gmc.VM_L2_CACHE_PARITY_CNTL);640 WREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL, adev->gmc.VM_L2_IH_LOG_CNTL);641 642 for (i = 0; i <= 15; i++) {643 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, adev->gmc.VM_CONTEXT_CNTL[i]);644 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i]);645 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[i]);646 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[i]);647 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[i]);648 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[i]);649 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[i]);650 }651 652 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, adev->gmc.vram_start >> 24);653 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, adev->gmc.vram_end >> 24);654 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, adev->gmc.MC_VM_MX_L1_TLB_CNTL);655}656 657static void gfxhub_v2_1_halt(struct amdgpu_device *adev)658{659 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];660 int i;661 uint32_t tmp;662 int time = 1000;663 664 gfxhub_v2_1_set_fault_enable_default(adev, false);665 666 for (i = 0; i <= 14; i++) {667 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,668 i * hub->ctx_addr_distance, ~0);669 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,670 i * hub->ctx_addr_distance, ~0);671 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,672 i * hub->ctx_addr_distance,673 0);674 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,675 i * hub->ctx_addr_distance,676 0);677 }678 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);679 while ((tmp & (GRBM_STATUS2__EA_BUSY_MASK |680 GRBM_STATUS2__EA_LINK_BUSY_MASK)) != 0 &&681 time) {682 udelay(100);683 time--;684 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);685 }686 687 if (!time)688 DRM_WARN("failed to wait for GRBM(EA) idle\n");689}690 691const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {692 .get_fb_location = gfxhub_v2_1_get_fb_location,693 .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,694 .setup_vm_pt_regs = gfxhub_v2_1_setup_vm_pt_regs,695 .gart_enable = gfxhub_v2_1_gart_enable,696 .gart_disable = gfxhub_v2_1_gart_disable,697 .set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default,698 .init = gfxhub_v2_1_init,699 .get_xgmi_info = gfxhub_v2_1_get_xgmi_info,700 .utcl2_harvest = gfxhub_v2_1_utcl2_harvest,701 .mode2_save_regs = gfxhub_v2_1_save_regs,702 .mode2_restore_regs = gfxhub_v2_1_restore_regs,703 .halt = gfxhub_v2_1_halt,704};705