1400 lines · c
1/*2 * Copyright 2014 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include <linux/firmware.h>25#include <linux/module.h>26#include <linux/pci.h>27 28#include <drm/drm_cache.h>29#include "amdgpu.h"30#include "cikd.h"31#include "cik.h"32#include "gmc_v7_0.h"33#include "amdgpu_ucode.h"34#include "amdgpu_amdkfd.h"35#include "amdgpu_gem.h"36 37#include "bif/bif_4_1_d.h"38#include "bif/bif_4_1_sh_mask.h"39 40#include "gmc/gmc_7_1_d.h"41#include "gmc/gmc_7_1_sh_mask.h"42 43#include "oss/oss_2_0_d.h"44#include "oss/oss_2_0_sh_mask.h"45 46#include "dce/dce_8_0_d.h"47#include "dce/dce_8_0_sh_mask.h"48 49#include "amdgpu_atombios.h"50 51#include "ivsrcid/ivsrcid_vislands30.h"52 53static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);54static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);55static int gmc_v7_0_wait_for_idle(void *handle);56 57MODULE_FIRMWARE("amdgpu/bonaire_mc.bin");58MODULE_FIRMWARE("amdgpu/hawaii_mc.bin");59MODULE_FIRMWARE("amdgpu/topaz_mc.bin");60 61static const u32 golden_settings_iceland_a11[] = {62 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,63 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,64 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,65 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff66};67 68static const u32 iceland_mgcg_cgcg_init[] = {69 mmMC_MEM_POWER_LS, 0xffffffff, 0x0000010470};71 72static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)73{74 switch (adev->asic_type) {75 case CHIP_TOPAZ:76 amdgpu_device_program_register_sequence(adev,77 iceland_mgcg_cgcg_init,78 ARRAY_SIZE(iceland_mgcg_cgcg_init));79 amdgpu_device_program_register_sequence(adev,80 golden_settings_iceland_a11,81 ARRAY_SIZE(golden_settings_iceland_a11));82 break;83 default:84 break;85 }86}87 88static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)89{90 u32 blackout;91 92 gmc_v7_0_wait_for_idle((void *)adev);93 94 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);95 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {96 /* Block CPU access */97 WREG32(mmBIF_FB_EN, 0);98 /* blackout the MC */99 blackout = REG_SET_FIELD(blackout,100 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);101 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);102 }103 /* wait for the MC to settle */104 udelay(100);105}106 107static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)108{109 u32 tmp;110 111 /* unblackout the MC */112 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);113 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);114 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);115 /* allow CPU access */116 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);117 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);118 WREG32(mmBIF_FB_EN, tmp);119}120 121/**122 * gmc_v7_0_init_microcode - load ucode images from disk123 *124 * @adev: amdgpu_device pointer125 *126 * Use the firmware interface to load the ucode images into127 * the driver (not loaded into hw).128 * Returns 0 on success, error on failure.129 */130static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)131{132 const char *chip_name;133 int err;134 135 DRM_DEBUG("\n");136 137 switch (adev->asic_type) {138 case CHIP_BONAIRE:139 chip_name = "bonaire";140 break;141 case CHIP_HAWAII:142 chip_name = "hawaii";143 break;144 case CHIP_TOPAZ:145 chip_name = "topaz";146 break;147 case CHIP_KAVERI:148 case CHIP_KABINI:149 case CHIP_MULLINS:150 return 0;151 default:152 return -EINVAL;153 }154 155 err = amdgpu_ucode_request(adev, &adev->gmc.fw, "amdgpu/%s_mc.bin", chip_name);156 if (err) {157 pr_err("cik_mc: Failed to load firmware \"%s_mc.bin\"\n", chip_name);158 amdgpu_ucode_release(&adev->gmc.fw);159 }160 return err;161}162 163/**164 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw165 *166 * @adev: amdgpu_device pointer167 *168 * Load the GDDR MC ucode into the hw (CIK).169 * Returns 0 on success, error on failure.170 */171static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)172{173 const struct mc_firmware_header_v1_0 *hdr;174 const __le32 *fw_data = NULL;175 const __le32 *io_mc_regs = NULL;176 u32 running;177 int i, ucode_size, regs_size;178 179 if (!adev->gmc.fw)180 return -EINVAL;181 182 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;183 amdgpu_ucode_print_mc_hdr(&hdr->header);184 185 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);186 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);187 io_mc_regs = (const __le32 *)188 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));189 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;190 fw_data = (const __le32 *)191 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));192 193 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);194 195 if (running == 0) {196 /* reset the engine and set to writable */197 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);198 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);199 200 /* load mc io regs */201 for (i = 0; i < regs_size; i++) {202 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));203 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));204 }205 /* load the MC ucode */206 for (i = 0; i < ucode_size; i++)207 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));208 209 /* put the engine back into the active state */210 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);211 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);212 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);213 214 /* wait for training to complete */215 for (i = 0; i < adev->usec_timeout; i++) {216 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),217 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))218 break;219 udelay(1);220 }221 for (i = 0; i < adev->usec_timeout; i++) {222 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),223 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))224 break;225 udelay(1);226 }227 }228 229 return 0;230}231 232static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,233 struct amdgpu_gmc *mc)234{235 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;236 237 base <<= 24;238 239 amdgpu_gmc_set_agp_default(adev, mc);240 amdgpu_gmc_vram_location(adev, mc, base);241 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);242}243 244/**245 * gmc_v7_0_mc_program - program the GPU memory controller246 *247 * @adev: amdgpu_device pointer248 *249 * Set the location of vram, gart, and AGP in the GPU's250 * physical address space (CIK).251 */252static void gmc_v7_0_mc_program(struct amdgpu_device *adev)253{254 u32 tmp;255 int i, j;256 257 /* Initialize HDP */258 for (i = 0, j = 0; i < 32; i++, j += 0x6) {259 WREG32((0xb05 + j), 0x00000000);260 WREG32((0xb06 + j), 0x00000000);261 WREG32((0xb07 + j), 0x00000000);262 WREG32((0xb08 + j), 0x00000000);263 WREG32((0xb09 + j), 0x00000000);264 }265 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);266 267 if (gmc_v7_0_wait_for_idle((void *)adev))268 dev_warn(adev->dev, "Wait for MC idle timedout !\n");269 270 if (adev->mode_info.num_crtc) {271 /* Lockout access through VGA aperture*/272 tmp = RREG32(mmVGA_HDP_CONTROL);273 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);274 WREG32(mmVGA_HDP_CONTROL, tmp);275 276 /* disable VGA render */277 tmp = RREG32(mmVGA_RENDER_CONTROL);278 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);279 WREG32(mmVGA_RENDER_CONTROL, tmp);280 }281 /* Update configuration */282 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,283 adev->gmc.vram_start >> 12);284 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,285 adev->gmc.vram_end >> 12);286 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,287 adev->mem_scratch.gpu_addr >> 12);288 WREG32(mmMC_VM_AGP_BASE, 0);289 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);290 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);291 if (gmc_v7_0_wait_for_idle((void *)adev))292 dev_warn(adev->dev, "Wait for MC idle timedout !\n");293 294 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);295 296 tmp = RREG32(mmHDP_MISC_CNTL);297 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);298 WREG32(mmHDP_MISC_CNTL, tmp);299 300 tmp = RREG32(mmHDP_HOST_PATH_CNTL);301 WREG32(mmHDP_HOST_PATH_CNTL, tmp);302}303 304/**305 * gmc_v7_0_mc_init - initialize the memory controller driver params306 *307 * @adev: amdgpu_device pointer308 *309 * Look up the amount of vram, vram width, and decide how to place310 * vram and gart within the GPU's physical address space (CIK).311 * Returns 0 for success.312 */313static int gmc_v7_0_mc_init(struct amdgpu_device *adev)314{315 int r;316 317 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);318 if (!adev->gmc.vram_width) {319 u32 tmp;320 int chansize, numchan;321 322 /* Get VRAM informations */323 tmp = RREG32(mmMC_ARB_RAMCFG);324 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE))325 chansize = 64;326 else327 chansize = 32;328 329 tmp = RREG32(mmMC_SHARED_CHMAP);330 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {331 case 0:332 default:333 numchan = 1;334 break;335 case 1:336 numchan = 2;337 break;338 case 2:339 numchan = 4;340 break;341 case 3:342 numchan = 8;343 break;344 case 4:345 numchan = 3;346 break;347 case 5:348 numchan = 6;349 break;350 case 6:351 numchan = 10;352 break;353 case 7:354 numchan = 12;355 break;356 case 8:357 numchan = 16;358 break;359 }360 adev->gmc.vram_width = numchan * chansize;361 }362 /* size in MB on si */363 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;364 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;365 366 if (!(adev->flags & AMD_IS_APU)) {367 r = amdgpu_device_resize_fb_bar(adev);368 if (r)369 return r;370 }371 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);372 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);373 374#ifdef CONFIG_X86_64375 if ((adev->flags & AMD_IS_APU) &&376 adev->gmc.real_vram_size > adev->gmc.aper_size &&377 !amdgpu_passthrough(adev)) {378 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;379 adev->gmc.aper_size = adev->gmc.real_vram_size;380 }381#endif382 383 adev->gmc.visible_vram_size = adev->gmc.aper_size;384 385 /* set the gart size */386 if (amdgpu_gart_size == -1) {387 switch (adev->asic_type) {388 case CHIP_TOPAZ: /* no MM engines */389 default:390 adev->gmc.gart_size = 256ULL << 20;391 break;392#ifdef CONFIG_DRM_AMDGPU_CIK393 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */394 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */395 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */396 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */397 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */398 adev->gmc.gart_size = 1024ULL << 20;399 break;400#endif401 }402 } else {403 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;404 }405 406 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;407 gmc_v7_0_vram_gtt_location(adev, &adev->gmc);408 409 return 0;410}411 412/**413 * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid414 *415 * @adev: amdgpu_device pointer416 * @pasid: pasid to be flush417 * @flush_type: type of flush418 * @all_hub: flush all hubs419 * @inst: is used to select which instance of KIQ to use for the invalidation420 *421 * Flush the TLB for the requested pasid.422 */423static void gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,424 uint16_t pasid, uint32_t flush_type,425 bool all_hub, uint32_t inst)426{427 u32 mask = 0x0;428 int vmid;429 430 for (vmid = 1; vmid < 16; vmid++) {431 u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);432 433 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&434 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid)435 mask |= 1 << vmid;436 }437 438 WREG32(mmVM_INVALIDATE_REQUEST, mask);439 RREG32(mmVM_INVALIDATE_RESPONSE);440}441 442/*443 * GART444 * VMID 0 is the physical GPU addresses as used by the kernel.445 * VMIDs 1-15 are used for userspace clients and are handled446 * by the amdgpu vm/hsa code.447 */448 449/**450 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback451 *452 * @adev: amdgpu_device pointer453 * @vmid: vm instance to flush454 * @vmhub: which hub to flush455 * @flush_type: type of flush456 * *457 * Flush the TLB for the requested page table (CIK).458 */459static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,460 uint32_t vmhub, uint32_t flush_type)461{462 /* bits 0-15 are the VM contexts0-15 */463 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);464}465 466static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,467 unsigned int vmid, uint64_t pd_addr)468{469 uint32_t reg;470 471 if (vmid < 8)472 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;473 else474 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;475 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);476 477 /* bits 0-15 are the VM contexts0-15 */478 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);479 480 return pd_addr;481}482 483static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,484 unsigned int pasid)485{486 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);487}488 489static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,490 uint64_t *addr, uint64_t *flags)491{492 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);493}494 495static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev,496 struct amdgpu_bo_va_mapping *mapping,497 uint64_t *flags)498{499 *flags &= ~AMDGPU_PTE_EXECUTABLE;500 *flags &= ~AMDGPU_PTE_PRT;501}502 503/**504 * gmc_v7_0_set_fault_enable_default - update VM fault handling505 *506 * @adev: amdgpu_device pointer507 * @value: true redirects VM faults to the default page508 */509static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,510 bool value)511{512 u32 tmp;513 514 tmp = RREG32(mmVM_CONTEXT1_CNTL);515 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,516 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);517 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,518 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);519 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,520 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);521 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,522 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);523 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,524 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);525 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,526 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);527 WREG32(mmVM_CONTEXT1_CNTL, tmp);528}529 530/**531 * gmc_v7_0_set_prt - set PRT VM fault532 *533 * @adev: amdgpu_device pointer534 * @enable: enable/disable VM fault handling for PRT535 */536static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)537{538 uint32_t tmp;539 540 if (enable && !adev->gmc.prt_warning) {541 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");542 adev->gmc.prt_warning = true;543 }544 545 tmp = RREG32(mmVM_PRT_CNTL);546 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,547 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);548 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,549 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);550 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,551 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);552 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,553 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);554 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,555 L2_CACHE_STORE_INVALID_ENTRIES, enable);556 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,557 L1_TLB_STORE_INVALID_ENTRIES, enable);558 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,559 MASK_PDE0_FAULT, enable);560 WREG32(mmVM_PRT_CNTL, tmp);561 562 if (enable) {563 uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >>564 AMDGPU_GPU_PAGE_SHIFT;565 uint32_t high = adev->vm_manager.max_pfn -566 (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT);567 568 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);569 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);570 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);571 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);572 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);573 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);574 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);575 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);576 } else {577 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);578 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);579 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);580 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);581 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);582 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);583 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);584 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);585 }586}587 588/**589 * gmc_v7_0_gart_enable - gart enable590 *591 * @adev: amdgpu_device pointer592 *593 * This sets up the TLBs, programs the page tables for VMID0,594 * sets up the hw for VMIDs 1-15 which are allocated on595 * demand, and sets up the global locations for the LDS, GDS,596 * and GPUVM for FSA64 clients (CIK).597 * Returns 0 for success, errors for failure.598 */599static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)600{601 uint64_t table_addr;602 u32 tmp, field;603 int i;604 605 if (adev->gart.bo == NULL) {606 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");607 return -EINVAL;608 }609 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);610 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);611 612 /* Setup TLB control */613 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);614 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);615 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);616 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);617 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);618 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);619 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);620 /* Setup L2 cache */621 tmp = RREG32(mmVM_L2_CNTL);622 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);629 WREG32(mmVM_L2_CNTL, tmp);630 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);632 WREG32(mmVM_L2_CNTL2, tmp);633 634 field = adev->vm_manager.fragment_size;635 tmp = RREG32(mmVM_L2_CNTL3);636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);639 WREG32(mmVM_L2_CNTL3, tmp);640 /* setup context0 */641 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);642 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);643 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);644 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,645 (u32)(adev->dummy_page_addr >> 12));646 WREG32(mmVM_CONTEXT0_CNTL2, 0);647 tmp = RREG32(mmVM_CONTEXT0_CNTL);648 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);649 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);650 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);651 WREG32(mmVM_CONTEXT0_CNTL, tmp);652 653 WREG32(0x575, 0);654 WREG32(0x576, 0);655 WREG32(0x577, 0);656 657 /* empty context1-15 */658 /* FIXME start with 4G, once using 2 level pt switch to full659 * vm size space660 */661 /* set vm size, must be a multiple of 4 */662 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);663 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);664 for (i = 1; i < AMDGPU_NUM_VMID; i++) {665 if (i < 8)666 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,667 table_addr >> 12);668 else669 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,670 table_addr >> 12);671 }672 673 /* enable context1-15 */674 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,675 (u32)(adev->dummy_page_addr >> 12));676 WREG32(mmVM_CONTEXT1_CNTL2, 4);677 tmp = RREG32(mmVM_CONTEXT1_CNTL);678 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);679 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);680 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,681 adev->vm_manager.block_size - 9);682 WREG32(mmVM_CONTEXT1_CNTL, tmp);683 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)684 gmc_v7_0_set_fault_enable_default(adev, false);685 else686 gmc_v7_0_set_fault_enable_default(adev, true);687 688 if (adev->asic_type == CHIP_KAVERI) {689 tmp = RREG32(mmCHUB_CONTROL);690 tmp &= ~BYPASS_VM;691 WREG32(mmCHUB_CONTROL, tmp);692 }693 694 gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0);695 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",696 (unsigned int)(adev->gmc.gart_size >> 20),697 (unsigned long long)table_addr);698 return 0;699}700 701static int gmc_v7_0_gart_init(struct amdgpu_device *adev)702{703 int r;704 705 if (adev->gart.bo) {706 WARN(1, "R600 PCIE GART already initialized\n");707 return 0;708 }709 /* Initialize common gart structure */710 r = amdgpu_gart_init(adev);711 if (r)712 return r;713 adev->gart.table_size = adev->gart.num_gpu_pages * 8;714 adev->gart.gart_pte_flags = 0;715 return amdgpu_gart_table_vram_alloc(adev);716}717 718/**719 * gmc_v7_0_gart_disable - gart disable720 *721 * @adev: amdgpu_device pointer722 *723 * This disables all VM page table (CIK).724 */725static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)726{727 u32 tmp;728 729 /* Disable all tables */730 WREG32(mmVM_CONTEXT0_CNTL, 0);731 WREG32(mmVM_CONTEXT1_CNTL, 0);732 /* Setup TLB control */733 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);734 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);735 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);736 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);737 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);738 /* Setup L2 cache */739 tmp = RREG32(mmVM_L2_CNTL);740 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);741 WREG32(mmVM_L2_CNTL, tmp);742 WREG32(mmVM_L2_CNTL2, 0);743}744 745/**746 * gmc_v7_0_vm_decode_fault - print human readable fault info747 *748 * @adev: amdgpu_device pointer749 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value750 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value751 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value752 * @pasid: debug logging only - no functional use753 *754 * Print human readable fault information (CIK).755 */756static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,757 u32 addr, u32 mc_client, unsigned int pasid)758{759 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);760 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,761 PROTECTIONS);762 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,763 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };764 u32 mc_id;765 766 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,767 MEMORY_CLIENT_ID);768 769 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",770 protections, vmid, pasid, addr,771 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,772 MEMORY_CLIENT_RW) ?773 "write" : "read", block, mc_client, mc_id);774}775 776 777static const u32 mc_cg_registers[] = {778 mmMC_HUB_MISC_HUB_CG,779 mmMC_HUB_MISC_SIP_CG,780 mmMC_HUB_MISC_VM_CG,781 mmMC_XPB_CLK_GAT,782 mmATC_MISC_CG,783 mmMC_CITF_MISC_WR_CG,784 mmMC_CITF_MISC_RD_CG,785 mmMC_CITF_MISC_VM_CG,786 mmVM_L2_CG,787};788 789static const u32 mc_cg_ls_en[] = {790 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,791 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,792 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,793 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,794 ATC_MISC_CG__MEM_LS_ENABLE_MASK,795 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,796 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,797 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,798 VM_L2_CG__MEM_LS_ENABLE_MASK,799};800 801static const u32 mc_cg_en[] = {802 MC_HUB_MISC_HUB_CG__ENABLE_MASK,803 MC_HUB_MISC_SIP_CG__ENABLE_MASK,804 MC_HUB_MISC_VM_CG__ENABLE_MASK,805 MC_XPB_CLK_GAT__ENABLE_MASK,806 ATC_MISC_CG__ENABLE_MASK,807 MC_CITF_MISC_WR_CG__ENABLE_MASK,808 MC_CITF_MISC_RD_CG__ENABLE_MASK,809 MC_CITF_MISC_VM_CG__ENABLE_MASK,810 VM_L2_CG__ENABLE_MASK,811};812 813static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,814 bool enable)815{816 int i;817 u32 orig, data;818 819 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {820 orig = data = RREG32(mc_cg_registers[i]);821 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))822 data |= mc_cg_ls_en[i];823 else824 data &= ~mc_cg_ls_en[i];825 if (data != orig)826 WREG32(mc_cg_registers[i], data);827 }828}829 830static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,831 bool enable)832{833 int i;834 u32 orig, data;835 836 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {837 orig = data = RREG32(mc_cg_registers[i]);838 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))839 data |= mc_cg_en[i];840 else841 data &= ~mc_cg_en[i];842 if (data != orig)843 WREG32(mc_cg_registers[i], data);844 }845}846 847static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,848 bool enable)849{850 u32 orig, data;851 852 orig = data = RREG32_PCIE(ixPCIE_CNTL2);853 854 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {855 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);856 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);857 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);858 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);859 } else {860 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);861 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);862 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);863 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);864 }865 866 if (orig != data)867 WREG32_PCIE(ixPCIE_CNTL2, data);868}869 870static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,871 bool enable)872{873 u32 orig, data;874 875 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);876 877 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))878 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);879 else880 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);881 882 if (orig != data)883 WREG32(mmHDP_HOST_PATH_CNTL, data);884}885 886static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,887 bool enable)888{889 u32 orig, data;890 891 orig = data = RREG32(mmHDP_MEM_POWER_LS);892 893 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))894 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);895 else896 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);897 898 if (orig != data)899 WREG32(mmHDP_MEM_POWER_LS, data);900}901 902static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)903{904 switch (mc_seq_vram_type) {905 case MC_SEQ_MISC0__MT__GDDR1:906 return AMDGPU_VRAM_TYPE_GDDR1;907 case MC_SEQ_MISC0__MT__DDR2:908 return AMDGPU_VRAM_TYPE_DDR2;909 case MC_SEQ_MISC0__MT__GDDR3:910 return AMDGPU_VRAM_TYPE_GDDR3;911 case MC_SEQ_MISC0__MT__GDDR4:912 return AMDGPU_VRAM_TYPE_GDDR4;913 case MC_SEQ_MISC0__MT__GDDR5:914 return AMDGPU_VRAM_TYPE_GDDR5;915 case MC_SEQ_MISC0__MT__HBM:916 return AMDGPU_VRAM_TYPE_HBM;917 case MC_SEQ_MISC0__MT__DDR3:918 return AMDGPU_VRAM_TYPE_DDR3;919 default:920 return AMDGPU_VRAM_TYPE_UNKNOWN;921 }922}923 924static int gmc_v7_0_early_init(void *handle)925{926 struct amdgpu_device *adev = (struct amdgpu_device *)handle;927 928 gmc_v7_0_set_gmc_funcs(adev);929 gmc_v7_0_set_irq_funcs(adev);930 931 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;932 adev->gmc.shared_aperture_end =933 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;934 adev->gmc.private_aperture_start =935 adev->gmc.shared_aperture_end + 1;936 adev->gmc.private_aperture_end =937 adev->gmc.private_aperture_start + (4ULL << 30) - 1;938 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;939 940 return 0;941}942 943static int gmc_v7_0_late_init(void *handle)944{945 struct amdgpu_device *adev = (struct amdgpu_device *)handle;946 947 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)948 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);949 else950 return 0;951}952 953static unsigned int gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)954{955 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);956 unsigned int size;957 958 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {959 size = AMDGPU_VBIOS_VGA_ALLOCATION;960 } else {961 u32 viewport = RREG32(mmVIEWPORT_SIZE);962 963 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *964 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *965 4);966 }967 968 return size;969}970 971static int gmc_v7_0_sw_init(void *handle)972{973 int r;974 struct amdgpu_device *adev = (struct amdgpu_device *)handle;975 976 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);977 978 if (adev->flags & AMD_IS_APU) {979 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;980 } else {981 u32 tmp = RREG32(mmMC_SEQ_MISC0);982 983 tmp &= MC_SEQ_MISC0__MT__MASK;984 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);985 }986 987 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);988 if (r)989 return r;990 991 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);992 if (r)993 return r;994 995 /* Adjust VM size here.996 * Currently set to 4GB ((1 << 20) 4k pages).997 * Max GPUVM size for cayman and SI is 40 bits.998 */999 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);1000 1001 /* Set the internal MC address mask1002 * This is the max address of the GPU's1003 * internal address space.1004 */1005 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */1006 1007 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));1008 if (r) {1009 pr_warn("No suitable DMA available\n");1010 return r;1011 }1012 adev->need_swiotlb = drm_need_swiotlb(40);1013 1014 r = gmc_v7_0_init_microcode(adev);1015 if (r) {1016 DRM_ERROR("Failed to load mc firmware!\n");1017 return r;1018 }1019 1020 r = gmc_v7_0_mc_init(adev);1021 if (r)1022 return r;1023 1024 amdgpu_gmc_get_vbios_allocations(adev);1025 1026 /* Memory manager */1027 r = amdgpu_bo_init(adev);1028 if (r)1029 return r;1030 1031 r = gmc_v7_0_gart_init(adev);1032 if (r)1033 return r;1034 1035 /*1036 * number of VMs1037 * VMID 0 is reserved for System1038 * amdgpu graphics/compute will use VMIDs 1-71039 * amdkfd will use VMIDs 8-151040 */1041 adev->vm_manager.first_kfd_vmid = 8;1042 amdgpu_vm_manager_init(adev);1043 1044 /* base offset of vram pages */1045 if (adev->flags & AMD_IS_APU) {1046 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);1047 1048 tmp <<= 22;1049 adev->vm_manager.vram_base_offset = tmp;1050 } else {1051 adev->vm_manager.vram_base_offset = 0;1052 }1053 1054 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),1055 GFP_KERNEL);1056 if (!adev->gmc.vm_fault_info)1057 return -ENOMEM;1058 atomic_set(&adev->gmc.vm_fault_info_updated, 0);1059 1060 return 0;1061}1062 1063static int gmc_v7_0_sw_fini(void *handle)1064{1065 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1066 1067 amdgpu_gem_force_release(adev);1068 amdgpu_vm_manager_fini(adev);1069 kfree(adev->gmc.vm_fault_info);1070 amdgpu_gart_table_vram_free(adev);1071 amdgpu_bo_fini(adev);1072 amdgpu_ucode_release(&adev->gmc.fw);1073 1074 return 0;1075}1076 1077static int gmc_v7_0_hw_init(void *handle)1078{1079 int r;1080 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1081 1082 gmc_v7_0_init_golden_registers(adev);1083 1084 gmc_v7_0_mc_program(adev);1085 1086 if (!(adev->flags & AMD_IS_APU)) {1087 r = gmc_v7_0_mc_load_microcode(adev);1088 if (r) {1089 DRM_ERROR("Failed to load MC firmware!\n");1090 return r;1091 }1092 }1093 1094 r = gmc_v7_0_gart_enable(adev);1095 if (r)1096 return r;1097 1098 if (amdgpu_emu_mode == 1)1099 return amdgpu_gmc_vram_checking(adev);1100 1101 return 0;1102}1103 1104static int gmc_v7_0_hw_fini(void *handle)1105{1106 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1107 1108 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);1109 gmc_v7_0_gart_disable(adev);1110 1111 return 0;1112}1113 1114static int gmc_v7_0_suspend(void *handle)1115{1116 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1117 1118 gmc_v7_0_hw_fini(adev);1119 1120 return 0;1121}1122 1123static int gmc_v7_0_resume(void *handle)1124{1125 int r;1126 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1127 1128 r = gmc_v7_0_hw_init(adev);1129 if (r)1130 return r;1131 1132 amdgpu_vmid_reset_all(adev);1133 1134 return 0;1135}1136 1137static bool gmc_v7_0_is_idle(void *handle)1138{1139 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1140 u32 tmp = RREG32(mmSRBM_STATUS);1141 1142 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |1143 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))1144 return false;1145 1146 return true;1147}1148 1149static int gmc_v7_0_wait_for_idle(void *handle)1150{1151 unsigned int i;1152 u32 tmp;1153 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1154 1155 for (i = 0; i < adev->usec_timeout; i++) {1156 /* read MC_STATUS */1157 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |1158 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |1159 SRBM_STATUS__MCC_BUSY_MASK |1160 SRBM_STATUS__MCD_BUSY_MASK |1161 SRBM_STATUS__VMC_BUSY_MASK);1162 if (!tmp)1163 return 0;1164 udelay(1);1165 }1166 return -ETIMEDOUT;1167 1168}1169 1170static int gmc_v7_0_soft_reset(void *handle)1171{1172 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1173 u32 srbm_soft_reset = 0;1174 u32 tmp = RREG32(mmSRBM_STATUS);1175 1176 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)1177 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,1178 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);1179 1180 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |1181 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {1182 if (!(adev->flags & AMD_IS_APU))1183 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,1184 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);1185 }1186 1187 if (srbm_soft_reset) {1188 gmc_v7_0_mc_stop(adev);1189 if (gmc_v7_0_wait_for_idle((void *)adev))1190 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");1191 1192 tmp = RREG32(mmSRBM_SOFT_RESET);1193 tmp |= srbm_soft_reset;1194 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);1195 WREG32(mmSRBM_SOFT_RESET, tmp);1196 tmp = RREG32(mmSRBM_SOFT_RESET);1197 1198 udelay(50);1199 1200 tmp &= ~srbm_soft_reset;1201 WREG32(mmSRBM_SOFT_RESET, tmp);1202 tmp = RREG32(mmSRBM_SOFT_RESET);1203 1204 /* Wait a little for things to settle down */1205 udelay(50);1206 1207 gmc_v7_0_mc_resume(adev);1208 udelay(50);1209 }1210 1211 return 0;1212}1213 1214static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,1215 struct amdgpu_irq_src *src,1216 unsigned int type,1217 enum amdgpu_interrupt_state state)1218{1219 u32 tmp;1220 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |1221 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |1222 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |1223 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |1224 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |1225 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);1226 1227 switch (state) {1228 case AMDGPU_IRQ_STATE_DISABLE:1229 /* system context */1230 tmp = RREG32(mmVM_CONTEXT0_CNTL);1231 tmp &= ~bits;1232 WREG32(mmVM_CONTEXT0_CNTL, tmp);1233 /* VMs */1234 tmp = RREG32(mmVM_CONTEXT1_CNTL);1235 tmp &= ~bits;1236 WREG32(mmVM_CONTEXT1_CNTL, tmp);1237 break;1238 case AMDGPU_IRQ_STATE_ENABLE:1239 /* system context */1240 tmp = RREG32(mmVM_CONTEXT0_CNTL);1241 tmp |= bits;1242 WREG32(mmVM_CONTEXT0_CNTL, tmp);1243 /* VMs */1244 tmp = RREG32(mmVM_CONTEXT1_CNTL);1245 tmp |= bits;1246 WREG32(mmVM_CONTEXT1_CNTL, tmp);1247 break;1248 default:1249 break;1250 }1251 1252 return 0;1253}1254 1255static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,1256 struct amdgpu_irq_src *source,1257 struct amdgpu_iv_entry *entry)1258{1259 u32 addr, status, mc_client, vmid;1260 1261 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);1262 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);1263 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);1264 /* reset addr and status */1265 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);1266 1267 if (!addr && !status)1268 return 0;1269 1270 amdgpu_vm_update_fault_cache(adev, entry->pasid,1271 ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0));1272 1273 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)1274 gmc_v7_0_set_fault_enable_default(adev, false);1275 1276 if (printk_ratelimit()) {1277 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",1278 entry->src_id, entry->src_data[0]);1279 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",1280 addr);1281 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",1282 status);1283 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client,1284 entry->pasid);1285 }1286 1287 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,1288 VMID);1289 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)1290 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {1291 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;1292 u32 protections = REG_GET_FIELD(status,1293 VM_CONTEXT1_PROTECTION_FAULT_STATUS,1294 PROTECTIONS);1295 1296 info->vmid = vmid;1297 info->mc_id = REG_GET_FIELD(status,1298 VM_CONTEXT1_PROTECTION_FAULT_STATUS,1299 MEMORY_CLIENT_ID);1300 info->status = status;1301 info->page_addr = addr;1302 info->prot_valid = protections & 0x7 ? true : false;1303 info->prot_read = protections & 0x8 ? true : false;1304 info->prot_write = protections & 0x10 ? true : false;1305 info->prot_exec = protections & 0x20 ? true : false;1306 mb();1307 atomic_set(&adev->gmc.vm_fault_info_updated, 1);1308 }1309 1310 return 0;1311}1312 1313static int gmc_v7_0_set_clockgating_state(void *handle,1314 enum amd_clockgating_state state)1315{1316 bool gate = false;1317 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1318 1319 if (state == AMD_CG_STATE_GATE)1320 gate = true;1321 1322 if (!(adev->flags & AMD_IS_APU)) {1323 gmc_v7_0_enable_mc_mgcg(adev, gate);1324 gmc_v7_0_enable_mc_ls(adev, gate);1325 }1326 gmc_v7_0_enable_bif_mgls(adev, gate);1327 gmc_v7_0_enable_hdp_mgcg(adev, gate);1328 gmc_v7_0_enable_hdp_ls(adev, gate);1329 1330 return 0;1331}1332 1333static int gmc_v7_0_set_powergating_state(void *handle,1334 enum amd_powergating_state state)1335{1336 return 0;1337}1338 1339static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {1340 .name = "gmc_v7_0",1341 .early_init = gmc_v7_0_early_init,1342 .late_init = gmc_v7_0_late_init,1343 .sw_init = gmc_v7_0_sw_init,1344 .sw_fini = gmc_v7_0_sw_fini,1345 .hw_init = gmc_v7_0_hw_init,1346 .hw_fini = gmc_v7_0_hw_fini,1347 .suspend = gmc_v7_0_suspend,1348 .resume = gmc_v7_0_resume,1349 .is_idle = gmc_v7_0_is_idle,1350 .wait_for_idle = gmc_v7_0_wait_for_idle,1351 .soft_reset = gmc_v7_0_soft_reset,1352 .set_clockgating_state = gmc_v7_0_set_clockgating_state,1353 .set_powergating_state = gmc_v7_0_set_powergating_state,1354 .dump_ip_state = NULL,1355 .print_ip_state = NULL,1356};1357 1358static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {1359 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,1360 .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,1361 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,1362 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,1363 .set_prt = gmc_v7_0_set_prt,1364 .get_vm_pde = gmc_v7_0_get_vm_pde,1365 .get_vm_pte = gmc_v7_0_get_vm_pte,1366 .get_vbios_fb_size = gmc_v7_0_get_vbios_fb_size,1367};1368 1369static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {1370 .set = gmc_v7_0_vm_fault_interrupt_state,1371 .process = gmc_v7_0_process_interrupt,1372};1373 1374static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)1375{1376 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;1377}1378 1379static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)1380{1381 adev->gmc.vm_fault.num_types = 1;1382 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;1383}1384 1385const struct amdgpu_ip_block_version gmc_v7_0_ip_block = {1386 .type = AMD_IP_BLOCK_TYPE_GMC,1387 .major = 7,1388 .minor = 0,1389 .rev = 0,1390 .funcs = &gmc_v7_0_ip_funcs,1391};1392 1393const struct amdgpu_ip_block_version gmc_v7_4_ip_block = {1394 .type = AMD_IP_BLOCK_TYPE_GMC,1395 .major = 7,1396 .minor = 4,1397 .rev = 0,1398 .funcs = &gmc_v7_0_ip_funcs,1399};1400