401 lines · c
1/*2 * Copyright 2023 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include <linux/firmware.h>25#include "amdgpu.h"26#include "amdgpu_imu.h"27#include "amdgpu_dpm.h"28 29#include "imu_v12_0.h"30 31#include "gc/gc_12_0_0_offset.h"32#include "gc/gc_12_0_0_sh_mask.h"33#include "mmhub/mmhub_4_1_0_offset.h"34 35MODULE_FIRMWARE("amdgpu/gc_12_0_0_imu.bin");36MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu.bin");37 38#define TRANSFER_RAM_MASK 0x001c000039 40static int imu_v12_0_init_microcode(struct amdgpu_device *adev)41{42 char ucode_prefix[15];43 int err;44 const struct imu_firmware_header_v1_0 *imu_hdr;45 struct amdgpu_firmware_info *info = NULL;46 47 DRM_DEBUG("\n");48 49 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));50 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, "amdgpu/%s_imu.bin", ucode_prefix);51 if (err)52 goto out;53 54 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;55 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version);56 57 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {58 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I];59 info->ucode_id = AMDGPU_UCODE_ID_IMU_I;60 info->fw = adev->gfx.imu_fw;61 adev->firmware.fw_size +=62 ALIGN(le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes), PAGE_SIZE);63 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_D];64 info->ucode_id = AMDGPU_UCODE_ID_IMU_D;65 info->fw = adev->gfx.imu_fw;66 adev->firmware.fw_size +=67 ALIGN(le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes), PAGE_SIZE);68 }69 70out:71 if (err) {72 dev_err(adev->dev,73 "gfx12: Failed to load firmware \"%s_imu.bin\"\n",74 ucode_prefix);75 amdgpu_ucode_release(&adev->gfx.imu_fw);76 }77 78 return err;79}80 81static int imu_v12_0_load_microcode(struct amdgpu_device *adev)82{83 const struct imu_firmware_header_v1_0 *hdr;84 const __le32 *fw_data;85 unsigned i, fw_size;86 87 if (!adev->gfx.imu_fw)88 return -EINVAL;89 90 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;91 92 fw_data = (const __le32 *)(adev->gfx.imu_fw->data +93 le32_to_cpu(hdr->header.ucode_array_offset_bytes));94 fw_size = le32_to_cpu(hdr->imu_iram_ucode_size_bytes) / 4;95 96 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0);97 98 for (i = 0; i < fw_size; i++)99 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++));100 101 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version);102 103 fw_data = (const __le32 *)(adev->gfx.imu_fw->data +104 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +105 le32_to_cpu(hdr->imu_iram_ucode_size_bytes));106 fw_size = le32_to_cpu(hdr->imu_dram_ucode_size_bytes) / 4;107 108 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0);109 110 for (i = 0; i < fw_size; i++)111 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++));112 113 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version);114 115 return 0;116}117 118static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev)119{120 u32 imu_reg_val = 0;121 int i;122 123 for (i = 0; i < adev->usec_timeout; i++) {124 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);125 if ((imu_reg_val & 0x1f) == 0x1f)126 break;127 udelay(1);128 }129 130 if (i >= adev->usec_timeout) {131 dev_err(adev->dev, "init imu: IMU start timeout\n");132 return -ETIMEDOUT;133 }134 135 return 0;136}137 138static void imu_v12_0_setup(struct amdgpu_device *adev)139{140 u32 imu_reg_val;141 142 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);143 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff);144 145 if (adev->gfx.imu.mode == DEBUG_MODE) {146 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);147 imu_reg_val |= 0x1;148 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);149 150 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);151 imu_reg_val |= 0x20010007;152 WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val);153 154 }155}156 157static int imu_v12_0_start(struct amdgpu_device *adev)158{159 u32 imu_reg_val;160 161 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);162 imu_reg_val &= 0xfffffffe;163 WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);164 165 if (adev->flags & AMD_IS_APU)166 amdgpu_dpm_set_gfx_power_up_by_imu(adev);167 168 return imu_v12_0_wait_for_reset_status(adev);169}170 171static const struct imu_rlc_ram_golden imu_rlc_ram_golden_12_0_1[] = {172 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCH_PIPE_STEER, 0x1e4, 0x1c0000),173 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL1X_PIPE_STEER, 0x1e4, 0x1c0000),174 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL1_PIPE_STEER, 0x1e4, 0x1c0000),175 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_0, 0x13571357, 0x1c0000),176 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_1, 0x64206420, 0x1c0000),177 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_2, 0x2460246, 0x1c0000),178 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_3, 0x75317531, 0x1c0000),179 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xc0d41183, 0x1c0000),180 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_CHICKEN_BITS, 0x507d1c0, 0x1c0000),181 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_CHICKEN_BITS, 0x507d1c0, 0x1c0000),182 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_RB_WPTR_POLL_CNTL, 0x600100, 0x1c0000),183 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_CREDITS, 0x3f7fff, 0x1c0000),184 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_CREDITS, 0x3f7ebf, 0x1c0000),185 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE0, 0x2e00000, 0x1c0000),186 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE1, 0x1a078, 0x1c0000),187 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE2, 0x0, 0x1c0000),188 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE0, 0x0, 0x1c0000),189 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE1, 0x12030, 0x1c0000),190 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE2, 0x0, 0x1c0000),191 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_VCC_RESERVE0, 0x19041000, 0x1c0000),192 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_VCC_RESERVE1, 0x80000000, 0x1c0000),193 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_VCC_RESERVE0, 0x1e080000, 0x1c0000),194 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_VCC_RESERVE1, 0x80000000, 0x1c0000),195 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_PRIORITY, 0x880, 0x1c0000),196 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_PRIORITY, 0x8880, 0x1c0000),197 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_ARB_FINAL, 0x17, 0x1c0000),198 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_ARB_FINAL, 0x77, 0x1c0000),199 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_ENABLE, 0x00000001, 0x1c0000),200 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_ENABLE, 0x00000001, 0x1c0000),201 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x20000, 0x1c0000),202 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0c, 0x1c0000),203 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xfffff, 0x1c0000),204 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_MISC, 0x0091, 0x1c0000),205 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_MISC, 0x0091, 0x1c0000),206 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),207 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x00008500, 0x1c0000),208 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0x00880007, 0x1c0000),209 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regTD_CNTL, 0x00000001, 0x1c0000),210 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000000, 0x1c0000),211 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000),212 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000001, 0x1c0000),213 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000),214 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000100, 0x1c0000),215 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000),216 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000101, 0x1c0000),217 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000),218 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),219 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x08200545, 0x1c0000),220 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBMH_CP_PERFMON_CNTL, 0x00000000, 0x1c0000),221 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCB_PERFCOUNTER0_SELECT1, 0x000fffff, 0x1c0000),222 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_DEBUG_2, 0x00020000, 0x1c0000),223 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_CPC_DEBUG, 0x00500010, 0x1c0000),224 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000500, 0x1c0000),225 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x00000001, 0x1c0000),226 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x00000000, 0x1c0000),227 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START, 0x00000000, 0x1c0000),228 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END, 0x0000000f, 0x1c0000),229 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 0x00006000, 0x1c0000),230 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 0x0000600f, 0x1c0000),231 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0x1c0000),232 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0x1c0000),233 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_TOP_OF_DRAM_SLOT1, 0xff800000, 0xe0000000),234 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_LOWER_TOP_OF_DRAM2, 0x00000001, 0x1c0000),235 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_UPPER_TOP_OF_DRAM2, 0x0000ffff, 0x1c0000),236 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0x1c0000),237 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0x1c0000),238 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0x1c0000),239 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0x1c0000),240 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000551, 0x1c0000),241 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0x1c0000),242 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0x1c0000),243 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0x1c0000),244 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0x1c0000),245 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x0003d000, 0x1c0000),246 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x0003d7ff, 0x1c0000),247 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 0x1c0000),248 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 0x1c0000)249};250 251static void program_imu_rlc_ram_old(struct amdgpu_device *adev,252 const struct imu_rlc_ram_golden *regs,253 const u32 array_size)254{255 const struct imu_rlc_ram_golden *entry;256 u32 reg, data;257 int i;258 259 for (i = 0; i < array_size; ++i) {260 entry = ®s[i];261 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;262 reg |= entry->addr_mask;263 data = entry->data;264 if (entry->reg == regGCMC_VM_AGP_BASE)265 data = 0x00ffffff;266 else if (entry->reg == regGCMC_VM_AGP_TOP)267 data = 0x0;268 else if (entry->reg == regGCMC_VM_FB_LOCATION_BASE)269 data = adev->gmc.vram_start >> 24;270 else if (entry->reg == regGCMC_VM_FB_LOCATION_TOP)271 data = adev->gmc.vram_end >> 24;272 273 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);274 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg);275 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data);276 }277}278 279static u32 imu_v12_0_grbm_gfx_index_remap(struct amdgpu_device *adev,280 u32 data, bool high)281{282 u32 val, inst_index;283 284 inst_index = REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_INDEX);285 286 if (high)287 val = inst_index >> 5;288 else289 val = REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES) << 18 |290 REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES) << 19 |291 REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES) << 20 |292 REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX) << 21 |293 REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX) << 25 |294 (inst_index & 0x1f);295 296 return val;297}298 299static u32 imu_v12_init_gfxhub_settings(struct amdgpu_device *adev,300 u32 reg, u32 data)301{302 if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_BASE))303 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);304 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_TOP))305 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_TOP);306 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_OFFSET))307 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET);308 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BASE))309 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE);310 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BOT))311 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT);312 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_TOP))313 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP);314 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL))315 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);316 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR))317 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR);318 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR))319 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR);320 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START))321 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_FB_ADDRESS_START);322 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END))323 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_FB_ADDRESS_END);324 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START))325 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START);326 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END))327 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END);328 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB))329 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB);330 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB))331 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB);332 else333 return data;334}335 336static void program_imu_rlc_ram(struct amdgpu_device *adev,337 const u32 *regs,338 const u32 array_size)339{340 u32 reg, data, val_h = 0, val_l = TRANSFER_RAM_MASK;341 int i;342 343 if (array_size % 3)344 return;345 346 for (i = 0; i < array_size; i += 3) {347 reg = regs[i + 0];348 data = regs[i + 2];349 data = imu_v12_init_gfxhub_settings(adev, reg, data);350 if (reg == SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX)) {351 val_l = imu_v12_0_grbm_gfx_index_remap(adev, data, false);352 val_h = imu_v12_0_grbm_gfx_index_remap(adev, data, true);353 } else {354 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, val_h);355 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg | val_l);356 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data);357 }358 }359}360 361static void imu_v12_0_program_rlc_ram(struct amdgpu_device *adev)362{363 u32 reg_data, size = 0;364 const u32 *data;365 int r = -EINVAL;366 367 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2);368 369 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {370 case IP_VERSION(12, 0, 0):371 case IP_VERSION(12, 0, 1):372 if (!r)373 program_imu_rlc_ram(adev, data, (const u32)size);374 else375 program_imu_rlc_ram_old(adev, imu_rlc_ram_golden_12_0_1,376 (const u32)ARRAY_SIZE(imu_rlc_ram_golden_12_0_1));377 break;378 default:379 BUG();380 break;381 }382 383 //Indicate the latest entry384 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);385 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0);386 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0);387 388 reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX);389 reg_data |= GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK;390 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, reg_data);391}392 393const struct amdgpu_imu_funcs gfx_v12_0_imu_funcs = {394 .init_microcode = imu_v12_0_init_microcode,395 .load_microcode = imu_v12_0_load_microcode,396 .setup_imu = imu_v12_0_setup,397 .start_imu = imu_v12_0_start,398 .program_rlc_ram = imu_v12_0_program_rlc_ram,399 .wait_for_reset_status = imu_v12_0_wait_for_reset_status,400};401