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1/*2 * Copyright 2019 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include "amdgpu.h"25#include "amdgpu_jpeg.h"26#include "amdgpu_cs.h"27#include "amdgpu_pm.h"28#include "soc15.h"29#include "soc15d.h"30#include "jpeg_v2_0.h"31 32#include "vcn/vcn_2_0_0_offset.h"33#include "vcn/vcn_2_0_0_sh_mask.h"34#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"35 36static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);37static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);38static int jpeg_v2_0_set_powergating_state(void *handle,39 enum amd_powergating_state state);40 41/**42 * jpeg_v2_0_early_init - set function pointers43 *44 * @handle: amdgpu_device pointer45 *46 * Set ring and irq function pointers47 */48static int jpeg_v2_0_early_init(void *handle)49{50 struct amdgpu_device *adev = (struct amdgpu_device *)handle;51 52 adev->jpeg.num_jpeg_inst = 1;53 adev->jpeg.num_jpeg_rings = 1;54 55 jpeg_v2_0_set_dec_ring_funcs(adev);56 jpeg_v2_0_set_irq_funcs(adev);57 58 return 0;59}60 61/**62 * jpeg_v2_0_sw_init - sw init for JPEG block63 *64 * @handle: amdgpu_device pointer65 *66 * Load firmware and sw initialization67 */68static int jpeg_v2_0_sw_init(void *handle)69{70 struct amdgpu_device *adev = (struct amdgpu_device *)handle;71 struct amdgpu_ring *ring;72 int r;73 74 /* JPEG TRAP */75 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,76 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);77 if (r)78 return r;79 80 r = amdgpu_jpeg_sw_init(adev);81 if (r)82 return r;83 84 r = amdgpu_jpeg_resume(adev);85 if (r)86 return r;87 88 ring = adev->jpeg.inst->ring_dec;89 ring->use_doorbell = true;90 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;91 ring->vm_hub = AMDGPU_MMHUB0(0);92 sprintf(ring->name, "jpeg_dec");93 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,94 0, AMDGPU_RING_PRIO_DEFAULT, NULL);95 if (r)96 return r;97 98 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;99 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);100 101 return 0;102}103 104/**105 * jpeg_v2_0_sw_fini - sw fini for JPEG block106 *107 * @handle: amdgpu_device pointer108 *109 * JPEG suspend and free up sw allocation110 */111static int jpeg_v2_0_sw_fini(void *handle)112{113 int r;114 struct amdgpu_device *adev = (struct amdgpu_device *)handle;115 116 r = amdgpu_jpeg_suspend(adev);117 if (r)118 return r;119 120 r = amdgpu_jpeg_sw_fini(adev);121 122 return r;123}124 125/**126 * jpeg_v2_0_hw_init - start and test JPEG block127 *128 * @handle: amdgpu_device pointer129 *130 */131static int jpeg_v2_0_hw_init(void *handle)132{133 struct amdgpu_device *adev = (struct amdgpu_device *)handle;134 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;135 136 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,137 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);138 139 return amdgpu_ring_test_helper(ring);140}141 142/**143 * jpeg_v2_0_hw_fini - stop the hardware block144 *145 * @handle: amdgpu_device pointer146 *147 * Stop the JPEG block, mark ring as not ready any more148 */149static int jpeg_v2_0_hw_fini(void *handle)150{151 struct amdgpu_device *adev = (struct amdgpu_device *)handle;152 153 cancel_delayed_work_sync(&adev->vcn.idle_work);154 155 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&156 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))157 jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);158 159 return 0;160}161 162/**163 * jpeg_v2_0_suspend - suspend JPEG block164 *165 * @handle: amdgpu_device pointer166 *167 * HW fini and suspend JPEG block168 */169static int jpeg_v2_0_suspend(void *handle)170{171 struct amdgpu_device *adev = (struct amdgpu_device *)handle;172 int r;173 174 r = jpeg_v2_0_hw_fini(adev);175 if (r)176 return r;177 178 r = amdgpu_jpeg_suspend(adev);179 180 return r;181}182 183/**184 * jpeg_v2_0_resume - resume JPEG block185 *186 * @handle: amdgpu_device pointer187 *188 * Resume firmware and hw init JPEG block189 */190static int jpeg_v2_0_resume(void *handle)191{192 int r;193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;194 195 r = amdgpu_jpeg_resume(adev);196 if (r)197 return r;198 199 r = jpeg_v2_0_hw_init(adev);200 201 return r;202}203 204static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)205{206 uint32_t data;207 int r = 0;208 209 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {210 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;211 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);212 213 r = SOC15_WAIT_ON_RREG(JPEG, 0,214 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,215 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);216 217 if (r) {218 DRM_ERROR("amdgpu: JPEG disable power gating failed\n");219 return r;220 }221 }222 223 /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */224 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;225 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);226 227 return 0;228}229 230static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev)231{232 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {233 uint32_t data;234 int r = 0;235 236 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));237 data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;238 data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;239 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);240 241 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;242 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);243 244 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,245 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),246 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);247 248 if (r) {249 DRM_ERROR("amdgpu: JPEG enable power gating failed\n");250 return r;251 }252 }253 254 return 0;255}256 257static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device *adev)258{259 uint32_t data;260 261 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);262 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)263 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;264 else265 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;266 267 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;268 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;269 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);270 271 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);272 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK273 | JPEG_CGC_GATE__JPEG2_DEC_MASK274 | JPEG_CGC_GATE__JPEG_ENC_MASK275 | JPEG_CGC_GATE__JMCIF_MASK276 | JPEG_CGC_GATE__JRBBM_MASK);277 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);278}279 280static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device *adev)281{282 uint32_t data;283 284 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);285 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)286 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;287 else288 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;289 290 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;291 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;292 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);293 294 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);295 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK296 |JPEG_CGC_GATE__JPEG2_DEC_MASK297 |JPEG_CGC_GATE__JPEG_ENC_MASK298 |JPEG_CGC_GATE__JMCIF_MASK299 |JPEG_CGC_GATE__JRBBM_MASK);300 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);301}302 303/**304 * jpeg_v2_0_start - start JPEG block305 *306 * @adev: amdgpu_device pointer307 *308 * Setup and start the JPEG block309 */310static int jpeg_v2_0_start(struct amdgpu_device *adev)311{312 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;313 int r;314 315 if (adev->pm.dpm_enabled)316 amdgpu_dpm_enable_jpeg(adev, true);317 318 /* disable power gating */319 r = jpeg_v2_0_disable_power_gating(adev);320 if (r)321 return r;322 323 /* JPEG disable CGC */324 jpeg_v2_0_disable_clock_gating(adev);325 326 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);327 328 /* enable JMI channel */329 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,330 ~UVD_JMI_CNTL__SOFT_RESET_MASK);331 332 /* enable System Interrupt for JRBC */333 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),334 JPEG_SYS_INT_EN__DJRBC_MASK,335 ~JPEG_SYS_INT_EN__DJRBC_MASK);336 337 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);338 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));339 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,340 lower_32_bits(ring->gpu_addr));341 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,342 upper_32_bits(ring->gpu_addr));343 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);344 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);345 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);346 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);347 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);348 349 return 0;350}351 352/**353 * jpeg_v2_0_stop - stop JPEG block354 *355 * @adev: amdgpu_device pointer356 *357 * stop the JPEG block358 */359static int jpeg_v2_0_stop(struct amdgpu_device *adev)360{361 int r;362 363 /* reset JMI */364 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),365 UVD_JMI_CNTL__SOFT_RESET_MASK,366 ~UVD_JMI_CNTL__SOFT_RESET_MASK);367 368 /* enable JPEG CGC */369 jpeg_v2_0_enable_clock_gating(adev);370 371 /* enable power gating */372 r = jpeg_v2_0_enable_power_gating(adev);373 if (r)374 return r;375 376 if (adev->pm.dpm_enabled)377 amdgpu_dpm_enable_jpeg(adev, false);378 379 return 0;380}381 382/**383 * jpeg_v2_0_dec_ring_get_rptr - get read pointer384 *385 * @ring: amdgpu_ring pointer386 *387 * Returns the current hardware read pointer388 */389static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)390{391 struct amdgpu_device *adev = ring->adev;392 393 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);394}395 396/**397 * jpeg_v2_0_dec_ring_get_wptr - get write pointer398 *399 * @ring: amdgpu_ring pointer400 *401 * Returns the current hardware write pointer402 */403static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)404{405 struct amdgpu_device *adev = ring->adev;406 407 if (ring->use_doorbell)408 return *ring->wptr_cpu_addr;409 else410 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);411}412 413/**414 * jpeg_v2_0_dec_ring_set_wptr - set write pointer415 *416 * @ring: amdgpu_ring pointer417 *418 * Commits the write pointer to the hardware419 */420static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)421{422 struct amdgpu_device *adev = ring->adev;423 424 if (ring->use_doorbell) {425 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);426 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));427 } else {428 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));429 }430}431 432/**433 * jpeg_v2_0_dec_ring_insert_start - insert a start command434 *435 * @ring: amdgpu_ring pointer436 *437 * Write a start command to the ring.438 */439void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)440{441 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,442 0, 0, PACKETJ_TYPE0));443 amdgpu_ring_write(ring, 0x68e04);444 445 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,446 0, 0, PACKETJ_TYPE0));447 amdgpu_ring_write(ring, 0x80010000);448}449 450/**451 * jpeg_v2_0_dec_ring_insert_end - insert a end command452 *453 * @ring: amdgpu_ring pointer454 *455 * Write a end command to the ring.456 */457void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)458{459 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,460 0, 0, PACKETJ_TYPE0));461 amdgpu_ring_write(ring, 0x68e04);462 463 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,464 0, 0, PACKETJ_TYPE0));465 amdgpu_ring_write(ring, 0x00010000);466}467 468/**469 * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command470 *471 * @ring: amdgpu_ring pointer472 * @addr: address473 * @seq: sequence number474 * @flags: fence related flags475 *476 * Write a fence and a trap command to the ring.477 */478void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,479 unsigned flags)480{481 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);482 483 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,484 0, 0, PACKETJ_TYPE0));485 amdgpu_ring_write(ring, seq);486 487 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,488 0, 0, PACKETJ_TYPE0));489 amdgpu_ring_write(ring, seq);490 491 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,492 0, 0, PACKETJ_TYPE0));493 amdgpu_ring_write(ring, lower_32_bits(addr));494 495 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,496 0, 0, PACKETJ_TYPE0));497 amdgpu_ring_write(ring, upper_32_bits(addr));498 499 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,500 0, 0, PACKETJ_TYPE0));501 amdgpu_ring_write(ring, 0x8);502 503 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,504 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));505 amdgpu_ring_write(ring, 0);506 507 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,508 0, 0, PACKETJ_TYPE0));509 amdgpu_ring_write(ring, 0x3fbc);510 511 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,512 0, 0, PACKETJ_TYPE0));513 amdgpu_ring_write(ring, 0x1);514 515 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));516 amdgpu_ring_write(ring, 0);517}518 519/**520 * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer521 *522 * @ring: amdgpu_ring pointer523 * @job: job to retrieve vmid from524 * @ib: indirect buffer to execute525 * @flags: unused526 *527 * Write ring commands to execute the indirect buffer.528 */529void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,530 struct amdgpu_job *job,531 struct amdgpu_ib *ib,532 uint32_t flags)533{534 unsigned vmid = AMDGPU_JOB_GET_VMID(job);535 536 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET,537 0, 0, PACKETJ_TYPE0));538 amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT));539 540 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,541 0, 0, PACKETJ_TYPE0));542 543 if (ring->funcs->parse_cs)544 amdgpu_ring_write(ring, 0);545 else546 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));547 548 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,549 0, 0, PACKETJ_TYPE0));550 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));551 552 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,553 0, 0, PACKETJ_TYPE0));554 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));555 556 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,557 0, 0, PACKETJ_TYPE0));558 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));559 560 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,561 0, 0, PACKETJ_TYPE0));562 amdgpu_ring_write(ring, ib->length_dw);563 564 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,565 0, 0, PACKETJ_TYPE0));566 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));567 568 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,569 0, 0, PACKETJ_TYPE0));570 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));571 572 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));573 amdgpu_ring_write(ring, 0);574 575 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,576 0, 0, PACKETJ_TYPE0));577 amdgpu_ring_write(ring, 0x01400200);578 579 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,580 0, 0, PACKETJ_TYPE0));581 amdgpu_ring_write(ring, 0x2);582 583 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,584 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));585 amdgpu_ring_write(ring, 0x2);586}587 588void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,589 uint32_t val, uint32_t mask)590{591 uint32_t reg_offset = (reg << 2);592 593 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,594 0, 0, PACKETJ_TYPE0));595 amdgpu_ring_write(ring, 0x01400200);596 597 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,598 0, 0, PACKETJ_TYPE0));599 amdgpu_ring_write(ring, val);600 601 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,602 0, 0, PACKETJ_TYPE0));603 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {604 amdgpu_ring_write(ring, 0);605 amdgpu_ring_write(ring,606 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));607 } else {608 amdgpu_ring_write(ring, reg_offset);609 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,610 0, 0, PACKETJ_TYPE3));611 }612 amdgpu_ring_write(ring, mask);613}614 615void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,616 unsigned vmid, uint64_t pd_addr)617{618 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];619 uint32_t data0, data1, mask;620 621 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);622 623 /* wait for register write */624 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;625 data1 = lower_32_bits(pd_addr);626 mask = 0xffffffff;627 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);628}629 630void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)631{632 uint32_t reg_offset = (reg << 2);633 634 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,635 0, 0, PACKETJ_TYPE0));636 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {637 amdgpu_ring_write(ring, 0);638 amdgpu_ring_write(ring,639 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));640 } else {641 amdgpu_ring_write(ring, reg_offset);642 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,643 0, 0, PACKETJ_TYPE0));644 }645 amdgpu_ring_write(ring, val);646}647 648void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)649{650 int i;651 652 WARN_ON(ring->wptr % 2 || count % 2);653 654 for (i = 0; i < count / 2; i++) {655 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));656 amdgpu_ring_write(ring, 0);657 }658}659 660static bool jpeg_v2_0_is_idle(void *handle)661{662 struct amdgpu_device *adev = (struct amdgpu_device *)handle;663 664 return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &665 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==666 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);667}668 669static int jpeg_v2_0_wait_for_idle(void *handle)670{671 struct amdgpu_device *adev = (struct amdgpu_device *)handle;672 int ret;673 674 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,675 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);676 677 return ret;678}679 680static int jpeg_v2_0_set_clockgating_state(void *handle,681 enum amd_clockgating_state state)682{683 struct amdgpu_device *adev = (struct amdgpu_device *)handle;684 bool enable = (state == AMD_CG_STATE_GATE);685 686 if (enable) {687 if (!jpeg_v2_0_is_idle(handle))688 return -EBUSY;689 jpeg_v2_0_enable_clock_gating(adev);690 } else {691 jpeg_v2_0_disable_clock_gating(adev);692 }693 694 return 0;695}696 697static int jpeg_v2_0_set_powergating_state(void *handle,698 enum amd_powergating_state state)699{700 struct amdgpu_device *adev = (struct amdgpu_device *)handle;701 int ret;702 703 if (state == adev->jpeg.cur_state)704 return 0;705 706 if (state == AMD_PG_STATE_GATE)707 ret = jpeg_v2_0_stop(adev);708 else709 ret = jpeg_v2_0_start(adev);710 711 if (!ret)712 adev->jpeg.cur_state = state;713 714 return ret;715}716 717static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev,718 struct amdgpu_irq_src *source,719 unsigned type,720 enum amdgpu_interrupt_state state)721{722 return 0;723}724 725static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev,726 struct amdgpu_irq_src *source,727 struct amdgpu_iv_entry *entry)728{729 DRM_DEBUG("IH: JPEG TRAP\n");730 731 switch (entry->src_id) {732 case VCN_2_0__SRCID__JPEG_DECODE:733 amdgpu_fence_process(adev->jpeg.inst->ring_dec);734 break;735 default:736 DRM_ERROR("Unhandled interrupt: %d %d\n",737 entry->src_id, entry->src_data[0]);738 break;739 }740 741 return 0;742}743 744static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {745 .name = "jpeg_v2_0",746 .early_init = jpeg_v2_0_early_init,747 .late_init = NULL,748 .sw_init = jpeg_v2_0_sw_init,749 .sw_fini = jpeg_v2_0_sw_fini,750 .hw_init = jpeg_v2_0_hw_init,751 .hw_fini = jpeg_v2_0_hw_fini,752 .suspend = jpeg_v2_0_suspend,753 .resume = jpeg_v2_0_resume,754 .is_idle = jpeg_v2_0_is_idle,755 .wait_for_idle = jpeg_v2_0_wait_for_idle,756 .check_soft_reset = NULL,757 .pre_soft_reset = NULL,758 .soft_reset = NULL,759 .post_soft_reset = NULL,760 .set_clockgating_state = jpeg_v2_0_set_clockgating_state,761 .set_powergating_state = jpeg_v2_0_set_powergating_state,762 .dump_ip_state = NULL,763 .print_ip_state = NULL,764};765 766static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {767 .type = AMDGPU_RING_TYPE_VCN_JPEG,768 .align_mask = 0xf,769 .get_rptr = jpeg_v2_0_dec_ring_get_rptr,770 .get_wptr = jpeg_v2_0_dec_ring_get_wptr,771 .set_wptr = jpeg_v2_0_dec_ring_set_wptr,772 .parse_cs = jpeg_v2_dec_ring_parse_cs,773 .emit_frame_size =774 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +775 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +776 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */777 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */778 8 + 16,779 .emit_ib_size = 24, /* jpeg_v2_0_dec_ring_emit_ib */780 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,781 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,782 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,783 .test_ring = amdgpu_jpeg_dec_ring_test_ring,784 .test_ib = amdgpu_jpeg_dec_ring_test_ib,785 .insert_nop = jpeg_v2_0_dec_ring_nop,786 .insert_start = jpeg_v2_0_dec_ring_insert_start,787 .insert_end = jpeg_v2_0_dec_ring_insert_end,788 .pad_ib = amdgpu_ring_generic_pad_ib,789 .begin_use = amdgpu_jpeg_ring_begin_use,790 .end_use = amdgpu_jpeg_ring_end_use,791 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,792 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,793 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,794};795 796static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)797{798 adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs;799}800 801static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = {802 .set = jpeg_v2_0_set_interrupt_state,803 .process = jpeg_v2_0_process_interrupt,804};805 806static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev)807{808 adev->jpeg.inst->irq.num_types = 1;809 adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;810}811 812const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = {813 .type = AMD_IP_BLOCK_TYPE_JPEG,814 .major = 2,815 .minor = 0,816 .rev = 0,817 .funcs = &jpeg_v2_0_ip_funcs,818};819 820/**821 * jpeg_v2_dec_ring_parse_cs - command submission parser822 *823 * @parser: Command submission parser context824 * @job: the job to parse825 * @ib: the IB to parse826 *827 * Parse the command stream, return -EINVAL for invalid packet,828 * 0 otherwise829 */830int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,831 struct amdgpu_job *job,832 struct amdgpu_ib *ib)833{834 u32 i, reg, res, cond, type;835 struct amdgpu_device *adev = parser->adev;836 837 for (i = 0; i < ib->length_dw ; i += 2) {838 reg = CP_PACKETJ_GET_REG(ib->ptr[i]);839 res = CP_PACKETJ_GET_RES(ib->ptr[i]);840 cond = CP_PACKETJ_GET_COND(ib->ptr[i]);841 type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);842 843 if (res) /* only support 0 at the moment */844 return -EINVAL;845 846 switch (type) {847 case PACKETJ_TYPE0:848 if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START ||849 reg > JPEG_REG_RANGE_END) {850 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);851 return -EINVAL;852 }853 break;854 case PACKETJ_TYPE3:855 if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START ||856 reg > JPEG_REG_RANGE_END) {857 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);858 return -EINVAL;859 }860 break;861 case PACKETJ_TYPE6:862 if (ib->ptr[i] == CP_PACKETJ_NOP)863 continue;864 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);865 return -EINVAL;866 default:867 dev_err(adev->dev, "Unknown packet type %d !\n", type);868 return -EINVAL;869 }870 }871 872 return 0;873}874