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1/*2 * Copyright 2019 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#ifndef __JPEG_V2_0_H__25#define __JPEG_V2_0_H__26 27#define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff28#define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x402929#define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a30#define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b31#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea32#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb33#define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf34#define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d135#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e836#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e937#define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x408238#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ec39#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ed40#define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x408541#define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x408442#define mmUVD_JRBC_STATUS_INTERNAL_OFFSET 0x408943#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f44#define mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET 0x414945 46#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x1800047 48#define JPEG_REG_RANGE_START 0x400049#define JPEG_REG_RANGE_END 0x41c250 51void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);52void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);53void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,54 unsigned flags);55void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,56 struct amdgpu_ib *ib, uint32_t flags);57void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,58 uint32_t val, uint32_t mask);59void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,60 unsigned vmid, uint64_t pd_addr);61void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);62void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);63int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,64 struct amdgpu_job *job,65 struct amdgpu_ib *ib);66 67extern const struct amdgpu_ip_block_version jpeg_v2_0_ip_block;68 69#endif /* __JPEG_V2_0_H__ */70