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1/*2 * Copyright 2019 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include "amdgpu.h"25#include "amdgpu_jpeg.h"26#include "amdgpu_pm.h"27#include "soc15.h"28#include "soc15d.h"29#include "jpeg_v2_0.h"30 31#include "vcn/vcn_3_0_0_offset.h"32#include "vcn/vcn_3_0_0_sh_mask.h"33#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"34 35#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f36 37static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);38static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);39static int jpeg_v3_0_set_powergating_state(void *handle,40 enum amd_powergating_state state);41 42/**43 * jpeg_v3_0_early_init - set function pointers44 *45 * @handle: amdgpu_device pointer46 *47 * Set ring and irq function pointers48 */49static int jpeg_v3_0_early_init(void *handle)50{51 struct amdgpu_device *adev = (struct amdgpu_device *)handle;52 53 u32 harvest;54 55 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {56 case IP_VERSION(3, 1, 1):57 case IP_VERSION(3, 1, 2):58 break;59 default:60 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);61 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)62 return -ENOENT;63 break;64 }65 66 adev->jpeg.num_jpeg_inst = 1;67 adev->jpeg.num_jpeg_rings = 1;68 69 jpeg_v3_0_set_dec_ring_funcs(adev);70 jpeg_v3_0_set_irq_funcs(adev);71 72 return 0;73}74 75/**76 * jpeg_v3_0_sw_init - sw init for JPEG block77 *78 * @handle: amdgpu_device pointer79 *80 * Load firmware and sw initialization81 */82static int jpeg_v3_0_sw_init(void *handle)83{84 struct amdgpu_device *adev = (struct amdgpu_device *)handle;85 struct amdgpu_ring *ring;86 int r;87 88 /* JPEG TRAP */89 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,90 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);91 if (r)92 return r;93 94 r = amdgpu_jpeg_sw_init(adev);95 if (r)96 return r;97 98 r = amdgpu_jpeg_resume(adev);99 if (r)100 return r;101 102 ring = adev->jpeg.inst->ring_dec;103 ring->use_doorbell = true;104 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;105 ring->vm_hub = AMDGPU_MMHUB0(0);106 sprintf(ring->name, "jpeg_dec");107 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,108 AMDGPU_RING_PRIO_DEFAULT, NULL);109 if (r)110 return r;111 112 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;113 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);114 115 return 0;116}117 118/**119 * jpeg_v3_0_sw_fini - sw fini for JPEG block120 *121 * @handle: amdgpu_device pointer122 *123 * JPEG suspend and free up sw allocation124 */125static int jpeg_v3_0_sw_fini(void *handle)126{127 struct amdgpu_device *adev = (struct amdgpu_device *)handle;128 int r;129 130 r = amdgpu_jpeg_suspend(adev);131 if (r)132 return r;133 134 r = amdgpu_jpeg_sw_fini(adev);135 136 return r;137}138 139/**140 * jpeg_v3_0_hw_init - start and test JPEG block141 *142 * @handle: amdgpu_device pointer143 *144 */145static int jpeg_v3_0_hw_init(void *handle)146{147 struct amdgpu_device *adev = (struct amdgpu_device *)handle;148 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;149 150 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,151 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);152 153 return amdgpu_ring_test_helper(ring);154}155 156/**157 * jpeg_v3_0_hw_fini - stop the hardware block158 *159 * @handle: amdgpu_device pointer160 *161 * Stop the JPEG block, mark ring as not ready any more162 */163static int jpeg_v3_0_hw_fini(void *handle)164{165 struct amdgpu_device *adev = (struct amdgpu_device *)handle;166 167 cancel_delayed_work_sync(&adev->vcn.idle_work);168 169 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&170 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))171 jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);172 173 return 0;174}175 176/**177 * jpeg_v3_0_suspend - suspend JPEG block178 *179 * @handle: amdgpu_device pointer180 *181 * HW fini and suspend JPEG block182 */183static int jpeg_v3_0_suspend(void *handle)184{185 struct amdgpu_device *adev = (struct amdgpu_device *)handle;186 int r;187 188 r = jpeg_v3_0_hw_fini(adev);189 if (r)190 return r;191 192 r = amdgpu_jpeg_suspend(adev);193 194 return r;195}196 197/**198 * jpeg_v3_0_resume - resume JPEG block199 *200 * @handle: amdgpu_device pointer201 *202 * Resume firmware and hw init JPEG block203 */204static int jpeg_v3_0_resume(void *handle)205{206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;207 int r;208 209 r = amdgpu_jpeg_resume(adev);210 if (r)211 return r;212 213 r = jpeg_v3_0_hw_init(adev);214 215 return r;216}217 218static void jpeg_v3_0_disable_clock_gating(struct amdgpu_device *adev)219{220 uint32_t data = 0;221 222 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);223 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)224 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;225 else226 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;227 228 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;229 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;230 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);231 232 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);233 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK234 | JPEG_CGC_GATE__JPEG2_DEC_MASK235 | JPEG_CGC_GATE__JPEG_ENC_MASK236 | JPEG_CGC_GATE__JMCIF_MASK237 | JPEG_CGC_GATE__JRBBM_MASK);238 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);239 240 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);241 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK242 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK243 | JPEG_CGC_CTRL__JMCIF_MODE_MASK244 | JPEG_CGC_CTRL__JRBBM_MODE_MASK);245 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);246}247 248static void jpeg_v3_0_enable_clock_gating(struct amdgpu_device *adev)249{250 uint32_t data = 0;251 252 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);253 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK254 |JPEG_CGC_GATE__JPEG2_DEC_MASK255 |JPEG_CGC_GATE__JPEG_ENC_MASK256 |JPEG_CGC_GATE__JMCIF_MASK257 |JPEG_CGC_GATE__JRBBM_MASK);258 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);259}260 261static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev)262{263 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {264 uint32_t data = 0;265 int r = 0;266 267 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;268 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);269 270 r = SOC15_WAIT_ON_RREG(JPEG, 0,271 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,272 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);273 274 if (r) {275 DRM_ERROR("amdgpu: JPEG disable power gating failed\n");276 return r;277 }278 }279 280 /* disable anti hang mechanism */281 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,282 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);283 284 /* keep the JPEG in static PG mode */285 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,286 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);287 288 return 0;289}290 291static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device *adev)292{293 /* enable anti hang mechanism */294 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS),295 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,296 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);297 298 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {299 uint32_t data = 0;300 int r = 0;301 302 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;303 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);304 305 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,306 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),307 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);308 309 if (r) {310 DRM_ERROR("amdgpu: JPEG enable power gating failed\n");311 return r;312 }313 }314 315 return 0;316}317 318/**319 * jpeg_v3_0_start - start JPEG block320 *321 * @adev: amdgpu_device pointer322 *323 * Setup and start the JPEG block324 */325static int jpeg_v3_0_start(struct amdgpu_device *adev)326{327 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;328 int r;329 330 if (adev->pm.dpm_enabled)331 amdgpu_dpm_enable_jpeg(adev, true);332 333 /* disable power gating */334 r = jpeg_v3_0_disable_static_power_gating(adev);335 if (r)336 return r;337 338 /* JPEG disable CGC */339 jpeg_v3_0_disable_clock_gating(adev);340 341 /* MJPEG global tiling registers */342 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,343 adev->gfx.config.gb_addr_config);344 WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG,345 adev->gfx.config.gb_addr_config);346 347 /* enable JMI channel */348 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,349 ~UVD_JMI_CNTL__SOFT_RESET_MASK);350 351 /* enable System Interrupt for JRBC */352 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),353 JPEG_SYS_INT_EN__DJRBC_MASK,354 ~JPEG_SYS_INT_EN__DJRBC_MASK);355 356 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);357 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));358 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,359 lower_32_bits(ring->gpu_addr));360 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,361 upper_32_bits(ring->gpu_addr));362 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);363 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);364 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);365 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);366 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);367 368 return 0;369}370 371/**372 * jpeg_v3_0_stop - stop JPEG block373 *374 * @adev: amdgpu_device pointer375 *376 * stop the JPEG block377 */378static int jpeg_v3_0_stop(struct amdgpu_device *adev)379{380 int r;381 382 /* reset JMI */383 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),384 UVD_JMI_CNTL__SOFT_RESET_MASK,385 ~UVD_JMI_CNTL__SOFT_RESET_MASK);386 387 jpeg_v3_0_enable_clock_gating(adev);388 389 /* enable power gating */390 r = jpeg_v3_0_enable_static_power_gating(adev);391 if (r)392 return r;393 394 if (adev->pm.dpm_enabled)395 amdgpu_dpm_enable_jpeg(adev, false);396 397 return 0;398}399 400/**401 * jpeg_v3_0_dec_ring_get_rptr - get read pointer402 *403 * @ring: amdgpu_ring pointer404 *405 * Returns the current hardware read pointer406 */407static uint64_t jpeg_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)408{409 struct amdgpu_device *adev = ring->adev;410 411 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);412}413 414/**415 * jpeg_v3_0_dec_ring_get_wptr - get write pointer416 *417 * @ring: amdgpu_ring pointer418 *419 * Returns the current hardware write pointer420 */421static uint64_t jpeg_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)422{423 struct amdgpu_device *adev = ring->adev;424 425 if (ring->use_doorbell)426 return *ring->wptr_cpu_addr;427 else428 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);429}430 431/**432 * jpeg_v3_0_dec_ring_set_wptr - set write pointer433 *434 * @ring: amdgpu_ring pointer435 *436 * Commits the write pointer to the hardware437 */438static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)439{440 struct amdgpu_device *adev = ring->adev;441 442 if (ring->use_doorbell) {443 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);444 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));445 } else {446 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));447 }448}449 450static bool jpeg_v3_0_is_idle(void *handle)451{452 struct amdgpu_device *adev = (struct amdgpu_device *)handle;453 int ret = 1;454 455 ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &456 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==457 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));458 459 return ret;460}461 462static int jpeg_v3_0_wait_for_idle(void *handle)463{464 struct amdgpu_device *adev = (struct amdgpu_device *)handle;465 466 return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,467 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,468 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);469}470 471static int jpeg_v3_0_set_clockgating_state(void *handle,472 enum amd_clockgating_state state)473{474 struct amdgpu_device *adev = (struct amdgpu_device *)handle;475 bool enable = state == AMD_CG_STATE_GATE;476 477 if (enable) {478 if (!jpeg_v3_0_is_idle(handle))479 return -EBUSY;480 jpeg_v3_0_enable_clock_gating(adev);481 } else {482 jpeg_v3_0_disable_clock_gating(adev);483 }484 485 return 0;486}487 488static int jpeg_v3_0_set_powergating_state(void *handle,489 enum amd_powergating_state state)490{491 struct amdgpu_device *adev = (struct amdgpu_device *)handle;492 int ret;493 494 if(state == adev->jpeg.cur_state)495 return 0;496 497 if (state == AMD_PG_STATE_GATE)498 ret = jpeg_v3_0_stop(adev);499 else500 ret = jpeg_v3_0_start(adev);501 502 if(!ret)503 adev->jpeg.cur_state = state;504 505 return ret;506}507 508static int jpeg_v3_0_set_interrupt_state(struct amdgpu_device *adev,509 struct amdgpu_irq_src *source,510 unsigned type,511 enum amdgpu_interrupt_state state)512{513 return 0;514}515 516static int jpeg_v3_0_process_interrupt(struct amdgpu_device *adev,517 struct amdgpu_irq_src *source,518 struct amdgpu_iv_entry *entry)519{520 DRM_DEBUG("IH: JPEG TRAP\n");521 522 switch (entry->src_id) {523 case VCN_2_0__SRCID__JPEG_DECODE:524 amdgpu_fence_process(adev->jpeg.inst->ring_dec);525 break;526 default:527 DRM_ERROR("Unhandled interrupt: %d %d\n",528 entry->src_id, entry->src_data[0]);529 break;530 }531 532 return 0;533}534 535static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {536 .name = "jpeg_v3_0",537 .early_init = jpeg_v3_0_early_init,538 .late_init = NULL,539 .sw_init = jpeg_v3_0_sw_init,540 .sw_fini = jpeg_v3_0_sw_fini,541 .hw_init = jpeg_v3_0_hw_init,542 .hw_fini = jpeg_v3_0_hw_fini,543 .suspend = jpeg_v3_0_suspend,544 .resume = jpeg_v3_0_resume,545 .is_idle = jpeg_v3_0_is_idle,546 .wait_for_idle = jpeg_v3_0_wait_for_idle,547 .check_soft_reset = NULL,548 .pre_soft_reset = NULL,549 .soft_reset = NULL,550 .post_soft_reset = NULL,551 .set_clockgating_state = jpeg_v3_0_set_clockgating_state,552 .set_powergating_state = jpeg_v3_0_set_powergating_state,553 .dump_ip_state = NULL,554 .print_ip_state = NULL,555};556 557static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {558 .type = AMDGPU_RING_TYPE_VCN_JPEG,559 .align_mask = 0xf,560 .get_rptr = jpeg_v3_0_dec_ring_get_rptr,561 .get_wptr = jpeg_v3_0_dec_ring_get_wptr,562 .set_wptr = jpeg_v3_0_dec_ring_set_wptr,563 .parse_cs = jpeg_v2_dec_ring_parse_cs,564 .emit_frame_size =565 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +566 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +567 8 + /* jpeg_v3_0_dec_ring_emit_vm_flush */568 18 + 18 + /* jpeg_v3_0_dec_ring_emit_fence x2 vm fence */569 8 + 16,570 .emit_ib_size = 22, /* jpeg_v3_0_dec_ring_emit_ib */571 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,572 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,573 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,574 .test_ring = amdgpu_jpeg_dec_ring_test_ring,575 .test_ib = amdgpu_jpeg_dec_ring_test_ib,576 .insert_nop = jpeg_v2_0_dec_ring_nop,577 .insert_start = jpeg_v2_0_dec_ring_insert_start,578 .insert_end = jpeg_v2_0_dec_ring_insert_end,579 .pad_ib = amdgpu_ring_generic_pad_ib,580 .begin_use = amdgpu_jpeg_ring_begin_use,581 .end_use = amdgpu_jpeg_ring_end_use,582 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,583 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,584 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,585};586 587static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)588{589 adev->jpeg.inst->ring_dec->funcs = &jpeg_v3_0_dec_ring_vm_funcs;590}591 592static const struct amdgpu_irq_src_funcs jpeg_v3_0_irq_funcs = {593 .set = jpeg_v3_0_set_interrupt_state,594 .process = jpeg_v3_0_process_interrupt,595};596 597static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev)598{599 adev->jpeg.inst->irq.num_types = 1;600 adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;601}602 603const struct amdgpu_ip_block_version jpeg_v3_0_ip_block =604{605 .type = AMD_IP_BLOCK_TYPE_JPEG,606 .major = 3,607 .minor = 0,608 .rev = 0,609 .funcs = &jpeg_v3_0_ip_funcs,610};611