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1/*2 * Copyright 2023 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include <linux/firmware.h>25#include <linux/module.h>26#include "amdgpu.h"27#include "soc15_common.h"28#include "soc21.h"29#include "gc/gc_12_0_0_offset.h"30#include "gc/gc_12_0_0_sh_mask.h"31#include "gc/gc_11_0_0_default.h"32#include "v12_structs.h"33#include "mes_v12_api_def.h"34 35MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin");36MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin");37MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin");38MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin");39MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin");40MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin");41 42static int mes_v12_0_hw_init(void *handle);43static int mes_v12_0_hw_fini(void *handle);44static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev);45static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev);46 47#define MES_EOP_SIZE 204848 49static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring)50{51 struct amdgpu_device *adev = ring->adev;52 53 if (ring->use_doorbell) {54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,55 ring->wptr);56 WDOORBELL64(ring->doorbell_index, ring->wptr);57 } else {58 BUG();59 }60}61 62static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring)63{64 return *ring->rptr_cpu_addr;65}66 67static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring)68{69 u64 wptr;70 71 if (ring->use_doorbell)72 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);73 else74 BUG();75 return wptr;76}77 78static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = {79 .type = AMDGPU_RING_TYPE_MES,80 .align_mask = 1,81 .nop = 0,82 .support_64bit_ptrs = true,83 .get_rptr = mes_v12_0_ring_get_rptr,84 .get_wptr = mes_v12_0_ring_get_wptr,85 .set_wptr = mes_v12_0_ring_set_wptr,86 .insert_nop = amdgpu_ring_insert_nop,87};88 89static const char *mes_v12_0_opcodes[] = {90 "SET_HW_RSRC",91 "SET_SCHEDULING_CONFIG",92 "ADD_QUEUE",93 "REMOVE_QUEUE",94 "PERFORM_YIELD",95 "SET_GANG_PRIORITY_LEVEL",96 "SUSPEND",97 "RESUME",98 "RESET",99 "SET_LOG_BUFFER",100 "CHANGE_GANG_PRORITY",101 "QUERY_SCHEDULER_STATUS",102 "unused",103 "SET_DEBUG_VMID",104 "MISC",105 "UPDATE_ROOT_PAGE_TABLE",106 "AMD_LOG",107 "SET_SE_MODE",108 "SET_GANG_SUBMIT",109 "SET_HW_RSRC_1",110};111 112static const char *mes_v12_0_misc_opcodes[] = {113 "WRITE_REG",114 "INV_GART",115 "QUERY_STATUS",116 "READ_REG",117 "WAIT_REG_MEM",118 "SET_SHADER_DEBUGGER",119 "NOTIFY_WORK_ON_UNMAPPED_QUEUE",120 "NOTIFY_TO_UNMAP_PROCESSES",121};122 123static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt)124{125 const char *op_str = NULL;126 127 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes))128 op_str = mes_v12_0_opcodes[x_pkt->header.opcode];129 130 return op_str;131}132 133static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt)134{135 const char *op_str = NULL;136 137 if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&138 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes)))139 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode];140 141 return op_str;142}143 144static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,145 int pipe, void *pkt, int size,146 int api_status_off)147{148 union MESAPI__QUERY_MES_STATUS mes_status_pkt;149 signed long timeout = 2100000; /* 2100 ms */150 struct amdgpu_device *adev = mes->adev;151 struct amdgpu_ring *ring = &mes->ring[pipe];152 spinlock_t *ring_lock = &mes->ring_lock[pipe];153 struct MES_API_STATUS *api_status;154 union MESAPI__MISC *x_pkt = pkt;155 const char *op_str, *misc_op_str;156 unsigned long flags;157 u64 status_gpu_addr;158 u32 seq, status_offset;159 u64 *status_ptr;160 signed long r;161 int ret;162 163 if (x_pkt->header.opcode >= MES_SCH_API_MAX)164 return -EINVAL;165 166 if (amdgpu_emu_mode) {167 timeout *= 100;168 } else if (amdgpu_sriov_vf(adev)) {169 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */170 timeout = 15 * 600 * 1000;171 }172 173 ret = amdgpu_device_wb_get(adev, &status_offset);174 if (ret)175 return ret;176 177 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4);178 status_ptr = (u64 *)&adev->wb.wb[status_offset];179 *status_ptr = 0;180 181 spin_lock_irqsave(ring_lock, flags);182 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);183 if (r)184 goto error_unlock_free;185 186 seq = ++ring->fence_drv.sync_seq;187 r = amdgpu_fence_wait_polling(ring,188 seq - ring->fence_drv.num_fences_mask,189 timeout);190 if (r < 1)191 goto error_undo;192 193 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);194 api_status->api_completion_fence_addr = status_gpu_addr;195 api_status->api_completion_fence_value = 1;196 197 amdgpu_ring_write_multiple(ring, pkt, size / 4);198 199 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));200 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;201 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;202 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;203 mes_status_pkt.api_status.api_completion_fence_addr =204 ring->fence_drv.gpu_addr;205 mes_status_pkt.api_status.api_completion_fence_value = seq;206 207 amdgpu_ring_write_multiple(ring, &mes_status_pkt,208 sizeof(mes_status_pkt) / 4);209 210 amdgpu_ring_commit(ring);211 spin_unlock_irqrestore(ring_lock, flags);212 213 op_str = mes_v12_0_get_op_string(x_pkt);214 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt);215 216 if (misc_op_str)217 dev_dbg(adev->dev, "MES(%d) msg=%s (%s) was emitted\n",218 pipe, op_str, misc_op_str);219 else if (op_str)220 dev_dbg(adev->dev, "MES(%d) msg=%s was emitted\n",221 pipe, op_str);222 else223 dev_dbg(adev->dev, "MES(%d) msg=%d was emitted\n",224 pipe, x_pkt->header.opcode);225 226 r = amdgpu_fence_wait_polling(ring, seq, timeout);227 if (r < 1 || !*status_ptr) {228 229 if (misc_op_str)230 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n",231 pipe, op_str, misc_op_str);232 else if (op_str)233 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s\n",234 pipe, op_str);235 else236 dev_err(adev->dev, "MES(%d) failed to respond to msg=%d\n",237 pipe, x_pkt->header.opcode);238 239 while (halt_if_hws_hang)240 schedule();241 242 r = -ETIMEDOUT;243 goto error_wb_free;244 }245 246 amdgpu_device_wb_free(adev, status_offset);247 return 0;248 249error_undo:250 dev_err(adev->dev, "MES ring buffer is full.\n");251 amdgpu_ring_undo(ring);252 253error_unlock_free:254 spin_unlock_irqrestore(ring_lock, flags);255 256error_wb_free:257 amdgpu_device_wb_free(adev, status_offset);258 return r;259}260 261static int convert_to_mes_queue_type(int queue_type)262{263 if (queue_type == AMDGPU_RING_TYPE_GFX)264 return MES_QUEUE_TYPE_GFX;265 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)266 return MES_QUEUE_TYPE_COMPUTE;267 else if (queue_type == AMDGPU_RING_TYPE_SDMA)268 return MES_QUEUE_TYPE_SDMA;269 else if (queue_type == AMDGPU_RING_TYPE_MES)270 return MES_QUEUE_TYPE_SCHQ;271 else272 BUG();273 return -1;274}275 276static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes,277 struct mes_add_queue_input *input)278{279 struct amdgpu_device *adev = mes->adev;280 union MESAPI__ADD_QUEUE mes_add_queue_pkt;281 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];282 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;283 284 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));285 286 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;287 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;288 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;289 290 mes_add_queue_pkt.process_id = input->process_id;291 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;292 mes_add_queue_pkt.process_va_start = input->process_va_start;293 mes_add_queue_pkt.process_va_end = input->process_va_end;294 mes_add_queue_pkt.process_quantum = input->process_quantum;295 mes_add_queue_pkt.process_context_addr = input->process_context_addr;296 mes_add_queue_pkt.gang_quantum = input->gang_quantum;297 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;298 mes_add_queue_pkt.inprocess_gang_priority =299 input->inprocess_gang_priority;300 mes_add_queue_pkt.gang_global_priority_level =301 input->gang_global_priority_level;302 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;303 mes_add_queue_pkt.mqd_addr = input->mqd_addr;304 305 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;306 307 mes_add_queue_pkt.queue_type =308 convert_to_mes_queue_type(input->queue_type);309 mes_add_queue_pkt.paging = input->paging;310 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;311 mes_add_queue_pkt.gws_base = input->gws_base;312 mes_add_queue_pkt.gws_size = input->gws_size;313 mes_add_queue_pkt.trap_handler_addr = input->tba_addr;314 mes_add_queue_pkt.tma_addr = input->tma_addr;315 mes_add_queue_pkt.trap_en = input->trap_en;316 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;317 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;318 319 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */320 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;321 mes_add_queue_pkt.gds_size = input->queue_size;322 323 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */324 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;325 mes_add_queue_pkt.gds_size = input->queue_size;326 327 return mes_v12_0_submit_pkt_and_poll_completion(mes,328 AMDGPU_MES_SCHED_PIPE,329 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),330 offsetof(union MESAPI__ADD_QUEUE, api_status));331}332 333static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes,334 struct mes_remove_queue_input *input)335{336 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;337 338 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));339 340 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;341 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;342 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;343 344 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;345 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;346 347 return mes_v12_0_submit_pkt_and_poll_completion(mes,348 AMDGPU_MES_SCHED_PIPE,349 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),350 offsetof(union MESAPI__REMOVE_QUEUE, api_status));351}352 353static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes,354 struct mes_reset_queue_input *input)355{356 union MESAPI__RESET mes_reset_queue_pkt;357 int pipe;358 359 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));360 361 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;362 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;363 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;364 365 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;366 mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr;367 /*mes_reset_queue_pkt.reset_queue_only = 1;*/368 369 if (mes->adev->enable_uni_mes)370 pipe = AMDGPU_MES_KIQ_PIPE;371 else372 pipe = AMDGPU_MES_SCHED_PIPE;373 374 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,375 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),376 offsetof(union MESAPI__REMOVE_QUEUE, api_status));377}378 379static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes,380 struct mes_map_legacy_queue_input *input)381{382 union MESAPI__ADD_QUEUE mes_add_queue_pkt;383 int pipe;384 385 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));386 387 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;388 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;389 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;390 391 mes_add_queue_pkt.pipe_id = input->pipe_id;392 mes_add_queue_pkt.queue_id = input->queue_id;393 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;394 mes_add_queue_pkt.mqd_addr = input->mqd_addr;395 mes_add_queue_pkt.wptr_addr = input->wptr_addr;396 mes_add_queue_pkt.queue_type =397 convert_to_mes_queue_type(input->queue_type);398 mes_add_queue_pkt.map_legacy_kq = 1;399 400 if (mes->adev->enable_uni_mes)401 pipe = AMDGPU_MES_KIQ_PIPE;402 else403 pipe = AMDGPU_MES_SCHED_PIPE;404 405 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,406 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),407 offsetof(union MESAPI__ADD_QUEUE, api_status));408}409 410static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes,411 struct mes_unmap_legacy_queue_input *input)412{413 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;414 int pipe;415 416 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));417 418 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;419 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;420 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;421 422 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;423 mes_remove_queue_pkt.gang_context_addr = 0;424 425 mes_remove_queue_pkt.pipe_id = input->pipe_id;426 mes_remove_queue_pkt.queue_id = input->queue_id;427 428 if (input->action == PREEMPT_QUEUES_NO_UNMAP) {429 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;430 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;431 mes_remove_queue_pkt.tf_data =432 lower_32_bits(input->trail_fence_data);433 } else {434 mes_remove_queue_pkt.unmap_legacy_queue = 1;435 mes_remove_queue_pkt.queue_type =436 convert_to_mes_queue_type(input->queue_type);437 }438 439 if (mes->adev->enable_uni_mes)440 pipe = AMDGPU_MES_KIQ_PIPE;441 else442 pipe = AMDGPU_MES_SCHED_PIPE;443 444 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,445 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),446 offsetof(union MESAPI__REMOVE_QUEUE, api_status));447}448 449static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes,450 struct mes_suspend_gang_input *input)451{452 return 0;453}454 455static int mes_v12_0_resume_gang(struct amdgpu_mes *mes,456 struct mes_resume_gang_input *input)457{458 return 0;459}460 461static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe)462{463 union MESAPI__QUERY_MES_STATUS mes_status_pkt;464 465 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));466 467 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;468 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;469 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;470 471 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,472 &mes_status_pkt, sizeof(mes_status_pkt),473 offsetof(union MESAPI__QUERY_MES_STATUS, api_status));474}475 476static int mes_v12_0_misc_op(struct amdgpu_mes *mes,477 struct mes_misc_op_input *input)478{479 union MESAPI__MISC misc_pkt;480 int pipe;481 482 if (mes->adev->enable_uni_mes)483 pipe = AMDGPU_MES_KIQ_PIPE;484 else485 pipe = AMDGPU_MES_SCHED_PIPE;486 487 memset(&misc_pkt, 0, sizeof(misc_pkt));488 489 misc_pkt.header.type = MES_API_TYPE_SCHEDULER;490 misc_pkt.header.opcode = MES_SCH_API_MISC;491 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;492 493 switch (input->op) {494 case MES_MISC_OP_READ_REG:495 misc_pkt.opcode = MESAPI_MISC__READ_REG;496 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;497 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;498 break;499 case MES_MISC_OP_WRITE_REG:500 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;501 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;502 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;503 break;504 case MES_MISC_OP_WRM_REG_WAIT:505 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;506 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;507 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;508 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;509 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;510 misc_pkt.wait_reg_mem.reg_offset2 = 0;511 break;512 case MES_MISC_OP_WRM_REG_WR_WAIT:513 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;514 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;515 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;516 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;517 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;518 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;519 break;520 case MES_MISC_OP_SET_SHADER_DEBUGGER:521 pipe = AMDGPU_MES_SCHED_PIPE;522 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;523 misc_pkt.set_shader_debugger.process_context_addr =524 input->set_shader_debugger.process_context_addr;525 misc_pkt.set_shader_debugger.flags.u32all =526 input->set_shader_debugger.flags.u32all;527 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =528 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;529 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,530 input->set_shader_debugger.tcp_watch_cntl,531 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));532 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;533 break;534 default:535 DRM_ERROR("unsupported misc op (%d) \n", input->op);536 return -EINVAL;537 }538 539 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,540 &misc_pkt, sizeof(misc_pkt),541 offsetof(union MESAPI__MISC, api_status));542}543 544static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)545{546 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt;547 548 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt));549 550 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER;551 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;552 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;553 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa;554 555 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,556 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),557 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));558}559 560static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)561{562 int i;563 struct amdgpu_device *adev = mes->adev;564 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;565 566 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));567 568 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;569 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;570 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;571 572 if (pipe == AMDGPU_MES_SCHED_PIPE) {573 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;574 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;575 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;576 mes_set_hw_res_pkt.paging_vmid = 0;577 578 for (i = 0; i < MAX_COMPUTE_PIPES; i++)579 mes_set_hw_res_pkt.compute_hqd_mask[i] =580 mes->compute_hqd_mask[i];581 582 for (i = 0; i < MAX_GFX_PIPES; i++)583 mes_set_hw_res_pkt.gfx_hqd_mask[i] =584 mes->gfx_hqd_mask[i];585 586 for (i = 0; i < MAX_SDMA_PIPES; i++)587 mes_set_hw_res_pkt.sdma_hqd_mask[i] =588 mes->sdma_hqd_mask[i];589 590 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)591 mes_set_hw_res_pkt.aggregated_doorbells[i] =592 mes->aggregated_doorbells[i];593 }594 595 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr =596 mes->sch_ctx_gpu_addr[pipe];597 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =598 mes->query_status_fence_gpu_addr[pipe];599 600 for (i = 0; i < 5; i++) {601 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];602 mes_set_hw_res_pkt.mmhub_base[i] =603 adev->reg_offset[MMHUB_HWIP][0][i];604 mes_set_hw_res_pkt.osssys_base[i] =605 adev->reg_offset[OSSSYS_HWIP][0][i];606 }607 608 mes_set_hw_res_pkt.disable_reset = 1;609 mes_set_hw_res_pkt.disable_mes_log = 1;610 mes_set_hw_res_pkt.use_different_vmid_compute = 1;611 mes_set_hw_res_pkt.enable_reg_active_poll = 1;612 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;613 614 /*615 * Keep oversubscribe timer for sdma . When we have unmapped doorbell616 * handling support, other queue will not use the oversubscribe timer.617 * handling mode - 0: disabled; 1: basic version; 2: basic+ version618 */619 mes_set_hw_res_pkt.oversubscription_timer = 50;620 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;621 622 if (amdgpu_mes_log_enable) {623 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;624 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr + pipe * AMDGPU_MES_LOG_BUFFER_SIZE;625 }626 627 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,628 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),629 offsetof(union MESAPI_SET_HW_RESOURCES, api_status));630}631 632static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes)633{634 struct amdgpu_device *adev = mes->adev;635 uint32_t data;636 637 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);638 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |639 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |640 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);641 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<642 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;643 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;644 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data);645 646 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);647 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |648 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |649 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);650 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<651 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;652 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;653 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data);654 655 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);656 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |657 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |658 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);659 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<660 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;661 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;662 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data);663 664 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);665 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |666 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |667 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);668 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<669 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;670 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;671 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data);672 673 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);674 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |675 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |676 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);677 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<678 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;679 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;680 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data);681 682 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;683 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data);684}685 686 687static void mes_v12_0_enable_unmapped_doorbell_handling(688 struct amdgpu_mes *mes, bool enable)689{690 struct amdgpu_device *adev = mes->adev;691 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL);692 693 /*694 * The default PROC_LSB settng is 0xc which means doorbell695 * addr[16:12] gives the doorbell page number. For kfd, each696 * process will use 2 pages of doorbell, we need to change the697 * setting to 0xd698 */699 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK;700 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT;701 702 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT;703 704 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data);705}706 707static int mes_v12_0_reset_legacy_queue(struct amdgpu_mes *mes,708 struct mes_reset_legacy_queue_input *input)709{710 union MESAPI__RESET mes_reset_queue_pkt;711 int pipe;712 713 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));714 715 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;716 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;717 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;718 719 mes_reset_queue_pkt.queue_type =720 convert_to_mes_queue_type(input->queue_type);721 722 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) {723 mes_reset_queue_pkt.reset_legacy_gfx = 1;724 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id;725 mes_reset_queue_pkt.queue_id_lp = input->queue_id;726 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr;727 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset;728 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr;729 mes_reset_queue_pkt.vmid_id_lp = input->vmid;730 } else {731 mes_reset_queue_pkt.reset_queue_only = 1;732 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;733 }734 735 if (mes->adev->enable_uni_mes)736 pipe = AMDGPU_MES_KIQ_PIPE;737 else738 pipe = AMDGPU_MES_SCHED_PIPE;739 740 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,741 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),742 offsetof(union MESAPI__RESET, api_status));743}744 745static const struct amdgpu_mes_funcs mes_v12_0_funcs = {746 .add_hw_queue = mes_v12_0_add_hw_queue,747 .remove_hw_queue = mes_v12_0_remove_hw_queue,748 .map_legacy_queue = mes_v12_0_map_legacy_queue,749 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue,750 .suspend_gang = mes_v12_0_suspend_gang,751 .resume_gang = mes_v12_0_resume_gang,752 .misc_op = mes_v12_0_misc_op,753 .reset_legacy_queue = mes_v12_0_reset_legacy_queue,754 .reset_hw_queue = mes_v12_0_reset_hw_queue,755};756 757static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,758 enum admgpu_mes_pipe pipe)759{760 int r;761 const struct mes_firmware_header_v1_0 *mes_hdr;762 const __le32 *fw_data;763 unsigned fw_size;764 765 mes_hdr = (const struct mes_firmware_header_v1_0 *)766 adev->mes.fw[pipe]->data;767 768 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +769 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));770 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);771 772 r = amdgpu_bo_create_reserved(adev, fw_size,773 PAGE_SIZE,774 AMDGPU_GEM_DOMAIN_VRAM,775 &adev->mes.ucode_fw_obj[pipe],776 &adev->mes.ucode_fw_gpu_addr[pipe],777 (void **)&adev->mes.ucode_fw_ptr[pipe]);778 if (r) {779 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);780 return r;781 }782 783 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);784 785 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);786 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);787 788 return 0;789}790 791static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,792 enum admgpu_mes_pipe pipe)793{794 int r;795 const struct mes_firmware_header_v1_0 *mes_hdr;796 const __le32 *fw_data;797 unsigned fw_size;798 799 mes_hdr = (const struct mes_firmware_header_v1_0 *)800 adev->mes.fw[pipe]->data;801 802 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +803 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));804 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);805 806 r = amdgpu_bo_create_reserved(adev, fw_size,807 64 * 1024,808 AMDGPU_GEM_DOMAIN_VRAM,809 &adev->mes.data_fw_obj[pipe],810 &adev->mes.data_fw_gpu_addr[pipe],811 (void **)&adev->mes.data_fw_ptr[pipe]);812 if (r) {813 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);814 return r;815 }816 817 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);818 819 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);820 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);821 822 return 0;823}824 825static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev,826 enum admgpu_mes_pipe pipe)827{828 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],829 &adev->mes.data_fw_gpu_addr[pipe],830 (void **)&adev->mes.data_fw_ptr[pipe]);831 832 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],833 &adev->mes.ucode_fw_gpu_addr[pipe],834 (void **)&adev->mes.ucode_fw_ptr[pipe]);835}836 837static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)838{839 uint64_t ucode_addr;840 uint32_t pipe, data = 0;841 842 if (enable) {843 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);844 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);845 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);846 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);847 848 mutex_lock(&adev->srbm_mutex);849 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {850 soc21_grbm_select(adev, 3, pipe, 0, 0);851 852 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;853 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,854 lower_32_bits(ucode_addr));855 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,856 upper_32_bits(ucode_addr));857 }858 soc21_grbm_select(adev, 0, 0, 0, 0);859 mutex_unlock(&adev->srbm_mutex);860 861 /* unhalt MES and activate pipe0 */862 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);863 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);864 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);865 866 if (amdgpu_emu_mode)867 msleep(100);868 else if (adev->enable_uni_mes)869 udelay(500);870 else871 udelay(50);872 } else {873 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);874 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);875 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);876 data = REG_SET_FIELD(data, CP_MES_CNTL,877 MES_INVALIDATE_ICACHE, 1);878 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);879 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);880 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);881 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);882 }883}884 885static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev)886{887 uint64_t ucode_addr;888 int pipe;889 890 mes_v12_0_enable(adev, false);891 892 mutex_lock(&adev->srbm_mutex);893 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {894 /* me=3, queue=0 */895 soc21_grbm_select(adev, 3, pipe, 0, 0);896 897 /* set ucode start address */898 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;899 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,900 lower_32_bits(ucode_addr));901 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,902 upper_32_bits(ucode_addr));903 904 soc21_grbm_select(adev, 0, 0, 0, 0);905 }906 mutex_unlock(&adev->srbm_mutex);907}908 909/* This function is for backdoor MES firmware */910static int mes_v12_0_load_microcode(struct amdgpu_device *adev,911 enum admgpu_mes_pipe pipe, bool prime_icache)912{913 int r;914 uint32_t data;915 916 mes_v12_0_enable(adev, false);917 918 if (!adev->mes.fw[pipe])919 return -EINVAL;920 921 r = mes_v12_0_allocate_ucode_buffer(adev, pipe);922 if (r)923 return r;924 925 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe);926 if (r) {927 mes_v12_0_free_ucode_buffers(adev, pipe);928 return r;929 }930 931 mutex_lock(&adev->srbm_mutex);932 /* me=3, pipe=0, queue=0 */933 soc21_grbm_select(adev, 3, pipe, 0, 0);934 935 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);936 937 /* set ucode fimrware address */938 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,939 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));940 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,941 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));942 943 /* set ucode instruction cache boundary to 2M-1 */944 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);945 946 /* set ucode data firmware address */947 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,948 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));949 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,950 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));951 952 /* Set data cache boundary CP_MES_MDBOUND_LO */953 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);954 955 if (prime_icache) {956 /* invalidate ICACHE */957 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);958 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);959 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);960 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);961 962 /* prime the ICACHE. */963 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);964 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);965 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);966 }967 968 soc21_grbm_select(adev, 0, 0, 0, 0);969 mutex_unlock(&adev->srbm_mutex);970 971 return 0;972}973 974static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev,975 enum admgpu_mes_pipe pipe)976{977 int r;978 u32 *eop;979 980 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,981 AMDGPU_GEM_DOMAIN_GTT,982 &adev->mes.eop_gpu_obj[pipe],983 &adev->mes.eop_gpu_addr[pipe],984 (void **)&eop);985 if (r) {986 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);987 return r;988 }989 990 memset(eop, 0,991 adev->mes.eop_gpu_obj[pipe]->tbo.base.size);992 993 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);994 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);995 996 return 0;997}998 999static int mes_v12_0_mqd_init(struct amdgpu_ring *ring)1000{1001 struct v12_compute_mqd *mqd = ring->mqd_ptr;1002 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;1003 uint32_t tmp;1004 1005 mqd->header = 0xC0310800;1006 mqd->compute_pipelinestat_enable = 0x00000001;1007 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;1008 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;1009 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;1010 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;1011 mqd->compute_misc_reserved = 0x00000007;1012 1013 eop_base_addr = ring->eop_gpu_addr >> 8;1014 1015 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */1016 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;1017 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,1018 (order_base_2(MES_EOP_SIZE / 4) - 1));1019 1020 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);1021 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);1022 mqd->cp_hqd_eop_control = tmp;1023 1024 /* disable the queue if it's active */1025 ring->wptr = 0;1026 mqd->cp_hqd_pq_rptr = 0;1027 mqd->cp_hqd_pq_wptr_lo = 0;1028 mqd->cp_hqd_pq_wptr_hi = 0;1029 1030 /* set the pointer to the MQD */1031 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;1032 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);1033 1034 /* set MQD vmid to 0 */1035 tmp = regCP_MQD_CONTROL_DEFAULT;1036 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);1037 mqd->cp_mqd_control = tmp;1038 1039 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */1040 hqd_gpu_addr = ring->gpu_addr >> 8;1041 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);1042 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);1043 1044 /* set the wb address whether it's enabled or not */1045 wb_gpu_addr = ring->rptr_gpu_addr;1046 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;1047 mqd->cp_hqd_pq_rptr_report_addr_hi =1048 upper_32_bits(wb_gpu_addr) & 0xffff;1049 1050 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */1051 wb_gpu_addr = ring->wptr_gpu_addr;1052 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;1053 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;1054 1055 /* set up the HQD, this is similar to CP_RB0_CNTL */1056 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;1057 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,1058 (order_base_2(ring->ring_size / 4) - 1));1059 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,1060 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));1061 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);1062 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);1063 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);1064 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);1065 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);1066 mqd->cp_hqd_pq_control = tmp;1067 1068 /* enable doorbell */1069 tmp = 0;1070 if (ring->use_doorbell) {1071 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,1072 DOORBELL_OFFSET, ring->doorbell_index);1073 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,1074 DOORBELL_EN, 1);1075 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,1076 DOORBELL_SOURCE, 0);1077 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,1078 DOORBELL_HIT, 0);1079 } else {1080 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,1081 DOORBELL_EN, 0);1082 }1083 mqd->cp_hqd_pq_doorbell_control = tmp;1084 1085 mqd->cp_hqd_vmid = 0;1086 /* activate the queue */1087 mqd->cp_hqd_active = 1;1088 1089 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;1090 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,1091 PRELOAD_SIZE, 0x55);1092 mqd->cp_hqd_persistent_state = tmp;1093 1094 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;1095 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;1096 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;1097 1098 /*1099 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped1100 * doorbell handling. This is a reserved CP internal register can1101 * not be accesss by others1102 */1103 mqd->reserved_184 = BIT(15);1104 1105 return 0;1106}1107 1108static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring)1109{1110 struct v12_compute_mqd *mqd = ring->mqd_ptr;1111 struct amdgpu_device *adev = ring->adev;1112 uint32_t data = 0;1113 1114 mutex_lock(&adev->srbm_mutex);1115 soc21_grbm_select(adev, 3, ring->pipe, 0, 0);1116 1117 /* set CP_HQD_VMID.VMID = 0. */1118 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);1119 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);1120 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);1121 1122 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */1123 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);1124 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,1125 DOORBELL_EN, 0);1126 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);1127 1128 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */1129 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);1130 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);1131 1132 /* set CP_MQD_CONTROL.VMID=0 */1133 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);1134 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);1135 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);1136 1137 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */1138 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);1139 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);1140 1141 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */1142 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,1143 mqd->cp_hqd_pq_rptr_report_addr_lo);1144 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,1145 mqd->cp_hqd_pq_rptr_report_addr_hi);1146 1147 /* set CP_HQD_PQ_CONTROL */1148 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);1149 1150 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */1151 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,1152 mqd->cp_hqd_pq_wptr_poll_addr_lo);1153 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,1154 mqd->cp_hqd_pq_wptr_poll_addr_hi);1155 1156 /* set CP_HQD_PQ_DOORBELL_CONTROL */1157 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,1158 mqd->cp_hqd_pq_doorbell_control);1159 1160 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */1161 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);1162 1163 /* set CP_HQD_ACTIVE.ACTIVE=1 */1164 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);1165 1166 soc21_grbm_select(adev, 0, 0, 0, 0);1167 mutex_unlock(&adev->srbm_mutex);1168}1169 1170static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev)1171{1172 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];1173 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;1174 int r;1175 1176 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)1177 return -EINVAL;1178 1179 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);1180 if (r) {1181 DRM_ERROR("Failed to lock KIQ (%d).\n", r);1182 return r;1183 }1184 1185 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]);1186 1187 r = amdgpu_ring_test_ring(kiq_ring);1188 if (r) {1189 DRM_ERROR("kfq enable failed\n");1190 kiq_ring->sched.ready = false;1191 }1192 return r;1193}1194 1195static int mes_v12_0_queue_init(struct amdgpu_device *adev,1196 enum admgpu_mes_pipe pipe)1197{1198 struct amdgpu_ring *ring;1199 int r;1200 1201 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)1202 ring = &adev->gfx.kiq[0].ring;1203 else1204 ring = &adev->mes.ring[pipe];1205 1206 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) &&1207 (amdgpu_in_reset(adev) || adev->in_suspend)) {1208 *(ring->wptr_cpu_addr) = 0;1209 *(ring->rptr_cpu_addr) = 0;1210 amdgpu_ring_clear_ring(ring);1211 }1212 1213 r = mes_v12_0_mqd_init(ring);1214 if (r)1215 return r;1216 1217 if (pipe == AMDGPU_MES_SCHED_PIPE) {1218 if (adev->enable_uni_mes)1219 r = amdgpu_mes_map_legacy_queue(adev, ring);1220 else1221 r = mes_v12_0_kiq_enable_queue(adev);1222 if (r)1223 return r;1224 } else {1225 mes_v12_0_queue_init_register(ring);1226 }1227 1228 /* get MES scheduler/KIQ versions */1229 mutex_lock(&adev->srbm_mutex);1230 soc21_grbm_select(adev, 3, pipe, 0, 0);1231 1232 if (pipe == AMDGPU_MES_SCHED_PIPE)1233 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);1234 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)1235 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);1236 1237 soc21_grbm_select(adev, 0, 0, 0, 0);1238 mutex_unlock(&adev->srbm_mutex);1239 1240 return 0;1241}1242 1243static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe)1244{1245 struct amdgpu_ring *ring;1246 1247 ring = &adev->mes.ring[pipe];1248 1249 ring->funcs = &mes_v12_0_ring_funcs;1250 1251 ring->me = 3;1252 ring->pipe = pipe;1253 ring->queue = 0;1254 1255 ring->ring_obj = NULL;1256 ring->use_doorbell = true;1257 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe];1258 ring->no_scheduler = true;1259 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);1260 1261 if (pipe == AMDGPU_MES_SCHED_PIPE)1262 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;1263 else1264 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;1265 1266 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,1267 AMDGPU_RING_PRIO_DEFAULT, NULL);1268}1269 1270static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev)1271{1272 struct amdgpu_ring *ring;1273 1274 spin_lock_init(&adev->gfx.kiq[0].ring_lock);1275 1276 ring = &adev->gfx.kiq[0].ring;1277 1278 ring->me = 3;1279 ring->pipe = 1;1280 ring->queue = 0;1281 1282 ring->adev = NULL;1283 ring->ring_obj = NULL;1284 ring->use_doorbell = true;1285 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;1286 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];1287 ring->no_scheduler = true;1288 sprintf(ring->name, "mes_kiq_%d.%d.%d",1289 ring->me, ring->pipe, ring->queue);1290 1291 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,1292 AMDGPU_RING_PRIO_DEFAULT, NULL);1293}1294 1295static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev,1296 enum admgpu_mes_pipe pipe)1297{1298 int r, mqd_size = sizeof(struct v12_compute_mqd);1299 struct amdgpu_ring *ring;1300 1301 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)1302 ring = &adev->gfx.kiq[0].ring;1303 else1304 ring = &adev->mes.ring[pipe];1305 1306 if (ring->mqd_obj)1307 return 0;1308 1309 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,1310 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,1311 &ring->mqd_gpu_addr, &ring->mqd_ptr);1312 if (r) {1313 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);1314 return r;1315 }1316 1317 memset(ring->mqd_ptr, 0, mqd_size);1318 1319 /* prepare MQD backup */1320 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);1321 if (!adev->mes.mqd_backup[pipe])1322 dev_warn(adev->dev,1323 "no memory to create MQD backup for ring %s\n",1324 ring->name);1325 1326 return 0;1327}1328 1329static int mes_v12_0_sw_init(void *handle)1330{1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1332 int pipe, r;1333 1334 adev->mes.funcs = &mes_v12_0_funcs;1335 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init;1336 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;1337 adev->mes.enable_legacy_queue_map = true;1338 1339 adev->mes.event_log_size = adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE) : AMDGPU_MES_LOG_BUFFER_SIZE;1340 1341 r = amdgpu_mes_init(adev);1342 if (r)1343 return r;1344 1345 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {1346 r = mes_v12_0_allocate_eop_buf(adev, pipe);1347 if (r)1348 return r;1349 1350 r = mes_v12_0_mqd_sw_init(adev, pipe);1351 if (r)1352 return r;1353 1354 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)1355 r = mes_v12_0_kiq_ring_init(adev);1356 else1357 r = mes_v12_0_ring_init(adev, pipe);1358 if (r)1359 return r;1360 }1361 1362 return 0;1363}1364 1365static int mes_v12_0_sw_fini(void *handle)1366{1367 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1368 int pipe;1369 1370 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {1371 kfree(adev->mes.mqd_backup[pipe]);1372 1373 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],1374 &adev->mes.eop_gpu_addr[pipe],1375 NULL);1376 amdgpu_ucode_release(&adev->mes.fw[pipe]);1377 1378 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) {1379 amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj,1380 &adev->mes.ring[pipe].mqd_gpu_addr,1381 &adev->mes.ring[pipe].mqd_ptr);1382 amdgpu_ring_fini(&adev->mes.ring[pipe]);1383 }1384 }1385 1386 if (!adev->enable_uni_mes) {1387 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,1388 &adev->gfx.kiq[0].ring.mqd_gpu_addr,1389 &adev->gfx.kiq[0].ring.mqd_ptr);1390 amdgpu_ring_fini(&adev->gfx.kiq[0].ring);1391 }1392 1393 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {1394 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);1395 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);1396 }1397 1398 amdgpu_mes_fini(adev);1399 return 0;1400}1401 1402static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev)1403{1404 uint32_t data;1405 int i;1406 1407 mutex_lock(&adev->srbm_mutex);1408 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0);1409 1410 /* disable the queue if it's active */1411 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {1412 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);1413 for (i = 0; i < adev->usec_timeout; i++) {1414 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))1415 break;1416 udelay(1);1417 }1418 }1419 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);1420 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,1421 DOORBELL_EN, 0);1422 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,1423 DOORBELL_HIT, 1);1424 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);1425 1426 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);1427 1428 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);1429 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);1430 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);1431 1432 soc21_grbm_select(adev, 0, 0, 0, 0);1433 mutex_unlock(&adev->srbm_mutex);1434 1435 adev->mes.ring[0].sched.ready = false;1436}1437 1438static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring)1439{1440 uint32_t tmp;1441 struct amdgpu_device *adev = ring->adev;1442 1443 /* tell RLC which is KIQ queue */1444 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);1445 tmp &= 0xffffff00;1446 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);1447 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);1448 tmp |= 0x80;1449 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);1450}1451 1452static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev)1453{1454 int r = 0;1455 1456 if (adev->enable_uni_mes)1457 mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]);1458 else1459 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring);1460 1461 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {1462 1463 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);1464 if (r) {1465 DRM_ERROR("failed to load MES fw, r=%d\n", r);1466 return r;1467 }1468 1469 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);1470 if (r) {1471 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);1472 return r;1473 }1474 1475 mes_v12_0_set_ucode_start_addr(adev);1476 1477 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)1478 mes_v12_0_set_ucode_start_addr(adev);1479 1480 mes_v12_0_enable(adev, true);1481 1482 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);1483 if (r)1484 goto failure;1485 1486 if (adev->enable_uni_mes) {1487 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE);1488 if (r)1489 goto failure;1490 1491 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE);1492 }1493 1494 if (adev->mes.enable_legacy_queue_map) {1495 r = mes_v12_0_hw_init(adev);1496 if (r)1497 goto failure;1498 }1499 1500 return r;1501 1502failure:1503 mes_v12_0_hw_fini(adev);1504 return r;1505}1506 1507static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev)1508{1509 if (adev->mes.ring[0].sched.ready) {1510 if (adev->enable_uni_mes)1511 amdgpu_mes_unmap_legacy_queue(adev,1512 &adev->mes.ring[AMDGPU_MES_SCHED_PIPE],1513 RESET_QUEUES, 0, 0);1514 else1515 mes_v12_0_kiq_dequeue_sched(adev);1516 1517 adev->mes.ring[0].sched.ready = false;1518 }1519 1520 mes_v12_0_enable(adev, false);1521 1522 return 0;1523}1524 1525static int mes_v12_0_hw_init(void *handle)1526{1527 int r;1528 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1529 1530 if (adev->mes.ring[0].sched.ready)1531 goto out;1532 1533 if (!adev->enable_mes_kiq) {1534 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {1535 r = mes_v12_0_load_microcode(adev,1536 AMDGPU_MES_SCHED_PIPE, true);1537 if (r) {1538 DRM_ERROR("failed to MES fw, r=%d\n", r);1539 return r;1540 }1541 1542 mes_v12_0_set_ucode_start_addr(adev);1543 1544 } else if (adev->firmware.load_type ==1545 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {1546 1547 mes_v12_0_set_ucode_start_addr(adev);1548 }1549 1550 mes_v12_0_enable(adev, true);1551 }1552 1553 /* Enable the MES to handle doorbell ring on unmapped queue */1554 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true);1555 1556 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);1557 if (r)1558 goto failure;1559 1560 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE);1561 if (r)1562 goto failure;1563 1564 if (adev->enable_uni_mes)1565 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE);1566 1567 mes_v12_0_init_aggregated_doorbell(&adev->mes);1568 1569 r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE);1570 if (r) {1571 DRM_ERROR("MES is busy\n");1572 goto failure;1573 }1574 1575out:1576 /*1577 * Disable KIQ ring usage from the driver once MES is enabled.1578 * MES uses KIQ ring exclusively so driver cannot access KIQ ring1579 * with MES enabled.1580 */1581 adev->gfx.kiq[0].ring.sched.ready = false;1582 adev->mes.ring[0].sched.ready = true;1583 1584 return 0;1585 1586failure:1587 mes_v12_0_hw_fini(adev);1588 return r;1589}1590 1591static int mes_v12_0_hw_fini(void *handle)1592{1593 return 0;1594}1595 1596static int mes_v12_0_suspend(void *handle)1597{1598 int r;1599 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1600 1601 r = amdgpu_mes_suspend(adev);1602 if (r)1603 return r;1604 1605 return mes_v12_0_hw_fini(adev);1606}1607 1608static int mes_v12_0_resume(void *handle)1609{1610 int r;1611 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1612 1613 r = mes_v12_0_hw_init(adev);1614 if (r)1615 return r;1616 1617 return amdgpu_mes_resume(adev);1618}1619 1620static int mes_v12_0_early_init(void *handle)1621{1622 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1623 int pipe, r;1624 1625 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {1626 r = amdgpu_mes_init_microcode(adev, pipe);1627 if (r)1628 return r;1629 }1630 1631 return 0;1632}1633 1634static int mes_v12_0_late_init(void *handle)1635{1636 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1637 1638 /* it's only intended for use in mes_self_test case, not for s0ix and reset */1639 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend)1640 amdgpu_mes_self_test(adev);1641 1642 return 0;1643}1644 1645static const struct amd_ip_funcs mes_v12_0_ip_funcs = {1646 .name = "mes_v12_0",1647 .early_init = mes_v12_0_early_init,1648 .late_init = mes_v12_0_late_init,1649 .sw_init = mes_v12_0_sw_init,1650 .sw_fini = mes_v12_0_sw_fini,1651 .hw_init = mes_v12_0_hw_init,1652 .hw_fini = mes_v12_0_hw_fini,1653 .suspend = mes_v12_0_suspend,1654 .resume = mes_v12_0_resume,1655};1656 1657const struct amdgpu_ip_block_version mes_v12_0_ip_block = {1658 .type = AMD_IP_BLOCK_TYPE_MES,1659 .major = 12,1660 .minor = 0,1661 .rev = 0,1662 .funcs = &mes_v12_0_ip_funcs,1663};1664