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1/*2 * Copyright 2021 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include "amdgpu.h"25#include "mmhub_v3_0.h"26 27#include "mmhub/mmhub_3_0_0_offset.h"28#include "mmhub/mmhub_3_0_0_sh_mask.h"29#include "navi10_enum.h"30 31#include "soc15_common.h"32 33#define regMMVM_L2_CNTL3_DEFAULT 0x8010000734#define regMMVM_L2_CNTL4_DEFAULT 0x000000c135#define regMMVM_L2_CNTL5_DEFAULT 0x00003fe036 37static const char *mmhub_client_ids_v3_0_0[][2] = {38 [0][0] = "VMC",39 [4][0] = "DCEDMC",40 [5][0] = "DCEVGA",41 [6][0] = "MP0",42 [7][0] = "MP1",43 [8][0] = "MPIO",44 [16][0] = "HDP",45 [17][0] = "LSDMA",46 [18][0] = "JPEG",47 [19][0] = "VCNU0",48 [21][0] = "VSCH",49 [22][0] = "VCNU1",50 [23][0] = "VCN1",51 [32+20][0] = "VCN0",52 [2][1] = "DBGUNBIO",53 [3][1] = "DCEDWB",54 [4][1] = "DCEDMC",55 [5][1] = "DCEVGA",56 [6][1] = "MP0",57 [7][1] = "MP1",58 [8][1] = "MPIO",59 [10][1] = "DBGU0",60 [11][1] = "DBGU1",61 [12][1] = "DBGU2",62 [13][1] = "DBGU3",63 [14][1] = "XDP",64 [15][1] = "OSSSYS",65 [16][1] = "HDP",66 [17][1] = "LSDMA",67 [18][1] = "JPEG",68 [19][1] = "VCNU0",69 [20][1] = "VCN0",70 [21][1] = "VSCH",71 [22][1] = "VCNU1",72 [23][1] = "VCN1",73};74 75static uint32_t mmhub_v3_0_get_invalidate_req(unsigned int vmid,76 uint32_t flush_type)77{78 u32 req = 0;79 80 /* invalidate using legacy mode on vmid*/81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,82 PER_VMID_INVALIDATE_REQ, 1 << vmid);83 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);84 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);85 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);86 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);87 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);88 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);89 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,90 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);91 92 return req;93}94 95static void96mmhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev,97 uint32_t status)98{99 uint32_t cid, rw;100 const char *mmhub_cid = NULL;101 102 cid = REG_GET_FIELD(status,103 MMVM_L2_PROTECTION_FAULT_STATUS, CID);104 rw = REG_GET_FIELD(status,105 MMVM_L2_PROTECTION_FAULT_STATUS, RW);106 107 dev_err(adev->dev,108 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",109 status);110 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {111 case IP_VERSION(3, 0, 0):112 case IP_VERSION(3, 0, 1):113 mmhub_cid = mmhub_client_ids_v3_0_0[cid][rw];114 break;115 default:116 mmhub_cid = NULL;117 break;118 }119 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",120 mmhub_cid ? mmhub_cid : "unknown", cid);121 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",122 REG_GET_FIELD(status,123 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));124 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",125 REG_GET_FIELD(status,126 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));127 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",128 REG_GET_FIELD(status,129 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));130 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",131 REG_GET_FIELD(status,132 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));133 dev_err(adev->dev, "\t RW: 0x%x\n", rw);134}135 136static void mmhub_v3_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,137 uint64_t page_table_base)138{139 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];140 141 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,142 hub->ctx_addr_distance * vmid,143 lower_32_bits(page_table_base));144 145 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,146 hub->ctx_addr_distance * vmid,147 upper_32_bits(page_table_base));148}149 150static void mmhub_v3_0_init_gart_aperture_regs(struct amdgpu_device *adev)151{152 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);153 154 mmhub_v3_0_setup_vm_pt_regs(adev, 0, pt_base);155 156 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,157 (u32)(adev->gmc.gart_start >> 12));158 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,159 (u32)(adev->gmc.gart_start >> 44));160 161 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,162 (u32)(adev->gmc.gart_end >> 12));163 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,164 (u32)(adev->gmc.gart_end >> 44));165}166 167static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)168{169 uint64_t value;170 uint32_t tmp;171 172 if (amdgpu_sriov_vf(adev))173 return;174 175 /*176 * the new L1 policy will block SRIOV guest from writing177 * these regs, and they will be programed at host.178 * so skip programing these regs.179 */180 /* Program the AGP BAR */181 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);182 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);184 185 /* Program the system aperture low logical page number. */186 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,187 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);188 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,189 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);190 191 /* Set default page address. */192 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);193 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,194 (u32)(value >> 12));195 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,196 (u32)(value >> 44));197 198 /* Program "protection fault". */199 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,200 (u32)(adev->dummy_page_addr >> 12));201 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,202 (u32)((u64)adev->dummy_page_addr >> 44));203 204 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);205 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,206 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);207 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);208}209 210static void mmhub_v3_0_init_tlb_regs(struct amdgpu_device *adev)211{212 uint32_t tmp;213 214 /* Setup TLB control */215 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);216 217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);219 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,220 ENABLE_ADVANCED_DRIVER_MODEL, 1);221 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,222 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);223 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);224 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,225 MTYPE, MTYPE_UC); /* UC, uncached */226 227 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);228}229 230static void mmhub_v3_0_init_cache_regs(struct amdgpu_device *adev)231{232 uint32_t tmp;233 234 /* These registers are not accessible to VF-SRIOV.235 * The PF will program them instead.236 */237 if (amdgpu_sriov_vf(adev))238 return;239 240 /* Setup L2 cache */241 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);242 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);243 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);244 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,245 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);246 /* XXX for emulation, Refer to closed source code.*/247 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,248 0);249 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);250 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);251 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);252 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);253 254 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);255 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);256 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);257 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);258 259 tmp = regMMVM_L2_CNTL3_DEFAULT;260 if (adev->gmc.translate_further) {261 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);262 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,263 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);264 } else {265 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);266 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,267 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);268 }269 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);270 271 tmp = regMMVM_L2_CNTL4_DEFAULT;272 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);273 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);274 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);275 276 tmp = regMMVM_L2_CNTL5_DEFAULT;277 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);278 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);279}280 281static void mmhub_v3_0_enable_system_domain(struct amdgpu_device *adev)282{283 uint32_t tmp;284 285 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);286 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);287 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);288 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,289 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);290 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);291}292 293static void mmhub_v3_0_disable_identity_aperture(struct amdgpu_device *adev)294{295 /* These registers are not accessible to VF-SRIOV.296 * The PF will program them instead.297 */298 if (amdgpu_sriov_vf(adev))299 return;300 301 WREG32_SOC15(MMHUB, 0,302 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,303 0xFFFFFFFF);304 WREG32_SOC15(MMHUB, 0,305 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,306 0x0000000F);307 308 WREG32_SOC15(MMHUB, 0,309 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);310 WREG32_SOC15(MMHUB, 0,311 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);312 313 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,314 0);315 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,316 0);317}318 319static void mmhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)320{321 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];322 int i;323 uint32_t tmp;324 325 for (i = 0; i <= 14; i++) {326 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);327 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);328 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,329 adev->vm_manager.num_level);330 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,331 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);332 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,333 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,334 1);335 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,336 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);337 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,338 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);339 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,340 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);341 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,342 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);343 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,344 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);345 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,346 PAGE_TABLE_BLOCK_SIZE,347 adev->vm_manager.block_size - 9);348 /* Send no-retry XNACK on fault to suppress VM fault storm. */349 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,350 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,351 !amdgpu_noretry);352 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,353 i * hub->ctx_distance, tmp);354 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,355 i * hub->ctx_addr_distance, 0);356 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,357 i * hub->ctx_addr_distance, 0);358 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,359 i * hub->ctx_addr_distance,360 lower_32_bits(adev->vm_manager.max_pfn - 1));361 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,362 i * hub->ctx_addr_distance,363 upper_32_bits(adev->vm_manager.max_pfn - 1));364 }365 366 hub->vm_cntx_cntl = tmp;367}368 369static void mmhub_v3_0_program_invalidation(struct amdgpu_device *adev)370{371 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];372 unsigned i;373 374 for (i = 0; i < 18; ++i) {375 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,376 i * hub->eng_addr_distance, 0xffffffff);377 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,378 i * hub->eng_addr_distance, 0x1f);379 }380}381 382static int mmhub_v3_0_gart_enable(struct amdgpu_device *adev)383{384 /* GART Enable. */385 mmhub_v3_0_init_gart_aperture_regs(adev);386 mmhub_v3_0_init_system_aperture_regs(adev);387 mmhub_v3_0_init_tlb_regs(adev);388 mmhub_v3_0_init_cache_regs(adev);389 390 mmhub_v3_0_enable_system_domain(adev);391 mmhub_v3_0_disable_identity_aperture(adev);392 mmhub_v3_0_setup_vmid_config(adev);393 mmhub_v3_0_program_invalidation(adev);394 395 return 0;396}397 398static void mmhub_v3_0_gart_disable(struct amdgpu_device *adev)399{400 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];401 u32 tmp;402 u32 i;403 404 /* Disable all tables */405 for (i = 0; i < 16; i++)406 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,407 i * hub->ctx_distance, 0);408 409 /* Setup TLB control */410 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);411 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);412 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,413 ENABLE_ADVANCED_DRIVER_MODEL, 0);414 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);415 416 /* Setup L2 cache */417 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);418 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);419 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);420 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);421}422 423/**424 * mmhub_v3_0_set_fault_enable_default - update GART/VM fault handling425 *426 * @adev: amdgpu_device pointer427 * @value: true redirects VM faults to the default page428 */429static void mmhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)430{431 u32 tmp;432 433 /* These registers are not accessible to VF-SRIOV.434 * The PF will program them instead.435 */436 if (amdgpu_sriov_vf(adev))437 return;438 439 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);440 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,441 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);442 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,443 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);444 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,445 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);446 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,447 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);448 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,449 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,450 value);451 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,452 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);453 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,454 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);455 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,456 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);457 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,458 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);459 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,460 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);461 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,462 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);463 if (!value) {464 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,465 CRASH_ON_NO_RETRY_FAULT, 1);466 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,467 CRASH_ON_RETRY_FAULT, 1);468 }469 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);470}471 472static const struct amdgpu_vmhub_funcs mmhub_v3_0_vmhub_funcs = {473 .print_l2_protection_fault_status = mmhub_v3_0_print_l2_protection_fault_status,474 .get_invalidate_req = mmhub_v3_0_get_invalidate_req,475};476 477static void mmhub_v3_0_init(struct amdgpu_device *adev)478{479 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];480 481 hub->ctx0_ptb_addr_lo32 =482 SOC15_REG_OFFSET(MMHUB, 0,483 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);484 hub->ctx0_ptb_addr_hi32 =485 SOC15_REG_OFFSET(MMHUB, 0,486 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);487 hub->vm_inv_eng0_sem =488 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);489 hub->vm_inv_eng0_req =490 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);491 hub->vm_inv_eng0_ack =492 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);493 hub->vm_context0_cntl =494 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);495 hub->vm_l2_pro_fault_status =496 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);497 hub->vm_l2_pro_fault_cntl =498 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);499 500 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;501 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -502 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;503 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -504 regMMVM_INVALIDATE_ENG0_REQ;505 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -506 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;507 508 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |509 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |510 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |511 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |512 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |513 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |514 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;515 516 hub->vm_l2_bank_select_reserved_cid2 =517 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);518 519 hub->vm_contexts_disable =520 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXTS_DISABLE);521 522 hub->vmhub_funcs = &mmhub_v3_0_vmhub_funcs;523}524 525static u64 mmhub_v3_0_get_fb_location(struct amdgpu_device *adev)526{527 u64 base;528 529 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);530 531 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;532 base <<= 24;533 534 return base;535}536 537static u64 mmhub_v3_0_get_mc_fb_offset(struct amdgpu_device *adev)538{539 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;540}541 542static void mmhub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,543 bool enable)544{545 uint32_t def, data;546#if 0547 uint32_t def1, data1, def2 = 0, data2 = 0;548#endif549 550 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);551#if 0552 def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);553 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);554#endif555 556 if (enable) {557 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;558#if 0559 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |560 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |561 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |562 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |563 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |564 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);565 566 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |567 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |568 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |569 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |570 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |571 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);572#endif573 } else {574 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;575#if 0576 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |577 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |578 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |579 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |580 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |581 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);582 583 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |584 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |585 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |586 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |587 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |588 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);589#endif590 }591 592 if (def != data)593 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);594#if 0595 if (def1 != data1)596 WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1);597 598 if (def2 != data2)599 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);600#endif601}602 603static void mmhub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,604 bool enable)605{606 uint32_t def, data;607 608 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);609 610 if (enable)611 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;612 else613 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;614 615 if (def != data)616 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);617}618 619static int mmhub_v3_0_set_clockgating(struct amdgpu_device *adev,620 enum amd_clockgating_state state)621{622 if (amdgpu_sriov_vf(adev))623 return 0;624 625 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)626 mmhub_v3_0_update_medium_grain_clock_gating(adev,627 state == AMD_CG_STATE_GATE);628 629 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)630 mmhub_v3_0_update_medium_grain_light_sleep(adev,631 state == AMD_CG_STATE_GATE);632 633 return 0;634}635 636static void mmhub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)637{638 int data;639 640 if (amdgpu_sriov_vf(adev))641 *flags = 0;642 643 data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);644 645 /* AMD_CG_SUPPORT_MC_MGCG */646 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK)647 *flags |= AMD_CG_SUPPORT_MC_MGCG;648 649 /* AMD_CG_SUPPORT_MC_LS */650 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)651 *flags |= AMD_CG_SUPPORT_MC_LS;652}653 654const struct amdgpu_mmhub_funcs mmhub_v3_0_funcs = {655 .init = mmhub_v3_0_init,656 .get_fb_location = mmhub_v3_0_get_fb_location,657 .get_mc_fb_offset = mmhub_v3_0_get_mc_fb_offset,658 .gart_enable = mmhub_v3_0_gart_enable,659 .set_fault_enable_default = mmhub_v3_0_set_fault_enable_default,660 .gart_disable = mmhub_v3_0_gart_disable,661 .set_clockgating = mmhub_v3_0_set_clockgating,662 .get_clockgating = mmhub_v3_0_get_clockgating,663 .setup_vm_pt_regs = mmhub_v3_0_setup_vm_pt_regs,664};665