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1/*2 * Copyright 2019 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#ifndef __MMSCH_V2_0_H__25#define __MMSCH_V2_0_H__26 27// addressBlock: uvd0_mmsch_dec28// base address: 0x1e00029#define mmMMSCH_UCODE_ADDR 0x000030#define mmMMSCH_UCODE_ADDR_BASE_IDX 031#define mmMMSCH_UCODE_DATA 0x000132#define mmMMSCH_UCODE_DATA_BASE_IDX 033#define mmMMSCH_SRAM_ADDR 0x000234#define mmMMSCH_SRAM_ADDR_BASE_IDX 035#define mmMMSCH_SRAM_DATA 0x000336#define mmMMSCH_SRAM_DATA_BASE_IDX 037#define mmMMSCH_VF_SRAM_OFFSET 0x000438#define mmMMSCH_VF_SRAM_OFFSET_BASE_IDX 039#define mmMMSCH_DB_SRAM_OFFSET 0x000540#define mmMMSCH_DB_SRAM_OFFSET_BASE_IDX 041#define mmMMSCH_CTX_SRAM_OFFSET 0x000642#define mmMMSCH_CTX_SRAM_OFFSET_BASE_IDX 043#define mmMMSCH_CTL 0x000744#define mmMMSCH_CTL_BASE_IDX 045#define mmMMSCH_INTR 0x000846#define mmMMSCH_INTR_BASE_IDX 047#define mmMMSCH_INTR_ACK 0x000948#define mmMMSCH_INTR_ACK_BASE_IDX 049#define mmMMSCH_INTR_STATUS 0x000a50#define mmMMSCH_INTR_STATUS_BASE_IDX 051#define mmMMSCH_VF_VMID 0x000b52#define mmMMSCH_VF_VMID_BASE_IDX 053#define mmMMSCH_VF_CTX_ADDR_LO 0x000c54#define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX 055#define mmMMSCH_VF_CTX_ADDR_HI 0x000d56#define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX 057#define mmMMSCH_VF_CTX_SIZE 0x000e58#define mmMMSCH_VF_CTX_SIZE_BASE_IDX 059#define mmMMSCH_VF_GPCOM_ADDR_LO 0x000f60#define mmMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 061#define mmMMSCH_VF_GPCOM_ADDR_HI 0x001062#define mmMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 063#define mmMMSCH_VF_GPCOM_SIZE 0x001164#define mmMMSCH_VF_GPCOM_SIZE_BASE_IDX 065#define mmMMSCH_VF_MAILBOX_HOST 0x001266#define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX 067#define mmMMSCH_VF_MAILBOX_RESP 0x001368#define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX 069#define mmMMSCH_VF_MAILBOX_0 0x001470#define mmMMSCH_VF_MAILBOX_0_BASE_IDX 071#define mmMMSCH_VF_MAILBOX_0_RESP 0x001572#define mmMMSCH_VF_MAILBOX_0_RESP_BASE_IDX 073#define mmMMSCH_VF_MAILBOX_1 0x001674#define mmMMSCH_VF_MAILBOX_1_BASE_IDX 075#define mmMMSCH_VF_MAILBOX_1_RESP 0x001776#define mmMMSCH_VF_MAILBOX_1_RESP_BASE_IDX 077#define mmMMSCH_CNTL 0x001c78#define mmMMSCH_CNTL_BASE_IDX 079#define mmMMSCH_NONCACHE_OFFSET0 0x001d80#define mmMMSCH_NONCACHE_OFFSET0_BASE_IDX 081#define mmMMSCH_NONCACHE_SIZE0 0x001e82#define mmMMSCH_NONCACHE_SIZE0_BASE_IDX 083#define mmMMSCH_NONCACHE_OFFSET1 0x001f84#define mmMMSCH_NONCACHE_OFFSET1_BASE_IDX 085#define mmMMSCH_NONCACHE_SIZE1 0x002086#define mmMMSCH_NONCACHE_SIZE1_BASE_IDX 087#define mmMMSCH_PDEBUG_STATUS 0x002188#define mmMMSCH_PDEBUG_STATUS_BASE_IDX 089#define mmMMSCH_PDEBUG_DATA_32UPPERBITS 0x002290#define mmMMSCH_PDEBUG_DATA_32UPPERBITS_BASE_IDX 091#define mmMMSCH_PDEBUG_DATA_32LOWERBITS 0x002392#define mmMMSCH_PDEBUG_DATA_32LOWERBITS_BASE_IDX 093#define mmMMSCH_PDEBUG_EPC 0x002494#define mmMMSCH_PDEBUG_EPC_BASE_IDX 095#define mmMMSCH_PDEBUG_EXCCAUSE 0x002596#define mmMMSCH_PDEBUG_EXCCAUSE_BASE_IDX 097#define mmMMSCH_PROC_STATE1 0x002698#define mmMMSCH_PROC_STATE1_BASE_IDX 099#define mmMMSCH_LAST_MC_ADDR 0x0027100#define mmMMSCH_LAST_MC_ADDR_BASE_IDX 0101#define mmMMSCH_LAST_MEM_ACCESS_HI 0x0028102#define mmMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX 0103#define mmMMSCH_LAST_MEM_ACCESS_LO 0x0029104#define mmMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX 0105#define mmMMSCH_IOV_ACTIVE_FCN_ID 0x002a106#define mmMMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX 0107#define mmMMSCH_SCRATCH_0 0x002b108#define mmMMSCH_SCRATCH_0_BASE_IDX 0109#define mmMMSCH_SCRATCH_1 0x002c110#define mmMMSCH_SCRATCH_1_BASE_IDX 0111#define mmMMSCH_GPUIOV_SCH_BLOCK_0 0x002d112#define mmMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX 0113#define mmMMSCH_GPUIOV_CMD_CONTROL_0 0x002e114#define mmMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX 0115#define mmMMSCH_GPUIOV_CMD_STATUS_0 0x002f116#define mmMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX 0117#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0 0x0030118#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX 0119#define mmMMSCH_GPUIOV_ACTIVE_FCNS_0 0x0031120#define mmMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX 0121#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0 0x0032122#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX 0123#define mmMMSCH_GPUIOV_DW6_0 0x0033124#define mmMMSCH_GPUIOV_DW6_0_BASE_IDX 0125#define mmMMSCH_GPUIOV_DW7_0 0x0034126#define mmMMSCH_GPUIOV_DW7_0_BASE_IDX 0127#define mmMMSCH_GPUIOV_DW8_0 0x0035128#define mmMMSCH_GPUIOV_DW8_0_BASE_IDX 0129#define mmMMSCH_GPUIOV_SCH_BLOCK_1 0x0036130#define mmMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX 0131#define mmMMSCH_GPUIOV_CMD_CONTROL_1 0x0037132#define mmMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX 0133#define mmMMSCH_GPUIOV_CMD_STATUS_1 0x0038134#define mmMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX 0135#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1 0x0039136#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX 0137#define mmMMSCH_GPUIOV_ACTIVE_FCNS_1 0x003a138#define mmMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX 0139#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1 0x003b140#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX 0141#define mmMMSCH_GPUIOV_DW6_1 0x003c142#define mmMMSCH_GPUIOV_DW6_1_BASE_IDX 0143#define mmMMSCH_GPUIOV_DW7_1 0x003d144#define mmMMSCH_GPUIOV_DW7_1_BASE_IDX 0145#define mmMMSCH_GPUIOV_DW8_1 0x003e146#define mmMMSCH_GPUIOV_DW8_1_BASE_IDX 0147#define mmMMSCH_GPUIOV_CNTXT 0x003f148#define mmMMSCH_GPUIOV_CNTXT_BASE_IDX 0149#define mmMMSCH_SCRATCH_2 0x0040150#define mmMMSCH_SCRATCH_2_BASE_IDX 0151#define mmMMSCH_SCRATCH_3 0x0041152#define mmMMSCH_SCRATCH_3_BASE_IDX 0153#define mmMMSCH_SCRATCH_4 0x0042154#define mmMMSCH_SCRATCH_4_BASE_IDX 0155#define mmMMSCH_SCRATCH_5 0x0043156#define mmMMSCH_SCRATCH_5_BASE_IDX 0157#define mmMMSCH_SCRATCH_6 0x0044158#define mmMMSCH_SCRATCH_6_BASE_IDX 0159#define mmMMSCH_SCRATCH_7 0x0045160#define mmMMSCH_SCRATCH_7_BASE_IDX 0161#define mmMMSCH_VFID_FIFO_HEAD_0 0x0046162#define mmMMSCH_VFID_FIFO_HEAD_0_BASE_IDX 0163#define mmMMSCH_VFID_FIFO_TAIL_0 0x0047164#define mmMMSCH_VFID_FIFO_TAIL_0_BASE_IDX 0165#define mmMMSCH_VFID_FIFO_HEAD_1 0x0048166#define mmMMSCH_VFID_FIFO_HEAD_1_BASE_IDX 0167#define mmMMSCH_VFID_FIFO_TAIL_1 0x0049168#define mmMMSCH_VFID_FIFO_TAIL_1_BASE_IDX 0169#define mmMMSCH_NACK_STATUS 0x004a170#define mmMMSCH_NACK_STATUS_BASE_IDX 0171#define mmMMSCH_VF_MAILBOX0_DATA 0x004b172#define mmMMSCH_VF_MAILBOX0_DATA_BASE_IDX 0173#define mmMMSCH_VF_MAILBOX1_DATA 0x004c174#define mmMMSCH_VF_MAILBOX1_DATA_BASE_IDX 0175#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0 0x004d176#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX 0177#define mmMMSCH_GPUIOV_CMD_STATUS_IP_0 0x004e178#define mmMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX 0179#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 0x004f180#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX 0181#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1 0x0050182#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX 0183#define mmMMSCH_GPUIOV_CMD_STATUS_IP_1 0x0051184#define mmMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX 0185#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 0x0052186#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX 0187#define mmMMSCH_GPUIOV_CNTXT_IP 0x0053188#define mmMMSCH_GPUIOV_CNTXT_IP_BASE_IDX 0189#define mmMMSCH_GPUIOV_SCH_BLOCK_2 0x0054190#define mmMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX 0191#define mmMMSCH_GPUIOV_CMD_CONTROL_2 0x0055192#define mmMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX 0193#define mmMMSCH_GPUIOV_CMD_STATUS_2 0x0056194#define mmMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX 0195#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2 0x0057196#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX 0197#define mmMMSCH_GPUIOV_ACTIVE_FCNS_2 0x0058198#define mmMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX 0199#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2 0x0059200#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX 0201#define mmMMSCH_GPUIOV_DW6_2 0x005a202#define mmMMSCH_GPUIOV_DW6_2_BASE_IDX 0203#define mmMMSCH_GPUIOV_DW7_2 0x005b204#define mmMMSCH_GPUIOV_DW7_2_BASE_IDX 0205#define mmMMSCH_GPUIOV_DW8_2 0x005c206#define mmMMSCH_GPUIOV_DW8_2_BASE_IDX 0207#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2 0x005d208#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX 0209#define mmMMSCH_GPUIOV_CMD_STATUS_IP_2 0x005e210#define mmMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX 0211#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 0x005f212#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX 0213#define mmMMSCH_VFID_FIFO_HEAD_2 0x0060214#define mmMMSCH_VFID_FIFO_HEAD_2_BASE_IDX 0215#define mmMMSCH_VFID_FIFO_TAIL_2 0x0061216#define mmMMSCH_VFID_FIFO_TAIL_2_BASE_IDX 0217#define mmMMSCH_VM_BUSY_STATUS_0 0x0062218#define mmMMSCH_VM_BUSY_STATUS_0_BASE_IDX 0219#define mmMMSCH_VM_BUSY_STATUS_1 0x0063220#define mmMMSCH_VM_BUSY_STATUS_1_BASE_IDX 0221#define mmMMSCH_VM_BUSY_STATUS_2 0x0064222#define mmMMSCH_VM_BUSY_STATUS_2_BASE_IDX 0223 224#define MMSCH_VERSION_MAJOR 2225#define MMSCH_VERSION_MINOR 0226#define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)227 228enum mmsch_v2_0_command_type {229 MMSCH_COMMAND__DIRECT_REG_WRITE = 0,230 MMSCH_COMMAND__DIRECT_REG_POLLING = 2,231 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,232 MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,233 MMSCH_COMMAND__END = 0xf234};235 236struct mmsch_v2_0_init_header {237 uint32_t version;238 uint32_t header_size;239 uint32_t vcn_init_status;240 uint32_t vcn_table_offset;241 uint32_t vcn_table_size;242};243 244struct mmsch_v2_0_cmd_direct_reg_header {245 uint32_t reg_offset : 28;246 uint32_t command_type : 4;247};248 249struct mmsch_v2_0_cmd_indirect_reg_header {250 uint32_t reg_offset : 20;251 uint32_t reg_idx_space : 8;252 uint32_t command_type : 4;253};254 255struct mmsch_v2_0_cmd_direct_write {256 struct mmsch_v2_0_cmd_direct_reg_header cmd_header;257 uint32_t reg_value;258};259 260struct mmsch_v2_0_cmd_direct_read_modify_write {261 struct mmsch_v2_0_cmd_direct_reg_header cmd_header;262 uint32_t write_data;263 uint32_t mask_value;264};265 266struct mmsch_v2_0_cmd_direct_polling {267 struct mmsch_v2_0_cmd_direct_reg_header cmd_header;268 uint32_t mask_value;269 uint32_t wait_value;270};271 272struct mmsch_v2_0_cmd_end {273 struct mmsch_v2_0_cmd_direct_reg_header cmd_header;274};275 276struct mmsch_v2_0_cmd_indirect_write {277 struct mmsch_v2_0_cmd_indirect_reg_header cmd_header;278 uint32_t reg_value;279};280 281static inline void mmsch_v2_0_insert_direct_wt(struct mmsch_v2_0_cmd_direct_write *direct_wt,282 uint32_t *init_table,283 uint32_t reg_offset,284 uint32_t value)285{286 direct_wt->cmd_header.reg_offset = reg_offset;287 direct_wt->reg_value = value;288 memcpy((void *)init_table, direct_wt, sizeof(struct mmsch_v2_0_cmd_direct_write));289}290 291static inline void mmsch_v2_0_insert_direct_rd_mod_wt(struct mmsch_v2_0_cmd_direct_read_modify_write *direct_rd_mod_wt,292 uint32_t *init_table,293 uint32_t reg_offset,294 uint32_t mask, uint32_t data)295{296 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;297 direct_rd_mod_wt->mask_value = mask;298 direct_rd_mod_wt->write_data = data;299 memcpy((void *)init_table, direct_rd_mod_wt,300 sizeof(struct mmsch_v2_0_cmd_direct_read_modify_write));301}302 303static inline void mmsch_v2_0_insert_direct_poll(struct mmsch_v2_0_cmd_direct_polling *direct_poll,304 uint32_t *init_table,305 uint32_t reg_offset,306 uint32_t mask, uint32_t wait)307{308 direct_poll->cmd_header.reg_offset = reg_offset;309 direct_poll->mask_value = mask;310 direct_poll->wait_value = wait;311 memcpy((void *)init_table, direct_poll, sizeof(struct mmsch_v2_0_cmd_direct_polling));312}313 314#define MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \315 mmsch_v2_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \316 init_table, (reg), \317 (mask), (data)); \318 init_table += sizeof(struct mmsch_v2_0_cmd_direct_read_modify_write)/4; \319 table_size += sizeof(struct mmsch_v2_0_cmd_direct_read_modify_write)/4; \320}321 322#define MMSCH_V2_0_INSERT_DIRECT_WT(reg, value) { \323 mmsch_v2_0_insert_direct_wt(&direct_wt, \324 init_table, (reg), \325 (value)); \326 init_table += sizeof(struct mmsch_v2_0_cmd_direct_write)/4; \327 table_size += sizeof(struct mmsch_v2_0_cmd_direct_write)/4; \328}329 330#define MMSCH_V2_0_INSERT_DIRECT_POLL(reg, mask, wait) { \331 mmsch_v2_0_insert_direct_poll(&direct_poll, \332 init_table, (reg), \333 (mask), (wait)); \334 init_table += sizeof(struct mmsch_v2_0_cmd_direct_polling)/4; \335 table_size += sizeof(struct mmsch_v2_0_cmd_direct_polling)/4; \336}337 338#endif339