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1/*2 * Copyright 2014 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include "amdgpu.h"25#include "nbio/nbio_2_3_offset.h"26#include "nbio/nbio_2_3_sh_mask.h"27#include "gc/gc_10_1_0_offset.h"28#include "gc/gc_10_1_0_sh_mask.h"29#include "soc15.h"30#include "navi10_ih.h"31#include "soc15_common.h"32#include "mxgpu_nv.h"33 34#include "amdgpu_reset.h"35 36static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev)37{38 WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);39}40 41static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool val)42{43 WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);44}45 46/*47 * this peek_msg could *only* be called in IRQ routine becuase in IRQ routine48 * RCV_MSG_VALID filed of BIF_BX_PF_MAILBOX_CONTROL must already be set to 149 * by host.50 *51 * if called no in IRQ routine, this peek_msg cannot guaranteed to return the52 * correct value since it doesn't return the RCV_DW0 under the case that53 * RCV_MSG_VALID is set by host.54 */55static enum idh_event xgpu_nv_mailbox_peek_msg(struct amdgpu_device *adev)56{57 return RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);58}59 60 61static int xgpu_nv_mailbox_rcv_msg(struct amdgpu_device *adev,62 enum idh_event event)63{64 u32 reg;65 66 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);67 if (reg != event)68 return -ENOENT;69 70 xgpu_nv_mailbox_send_ack(adev);71 72 return 0;73}74 75static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev)76{77 return RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2;78}79 80static int xgpu_nv_poll_ack(struct amdgpu_device *adev)81{82 int timeout = NV_MAILBOX_POLL_ACK_TIMEDOUT;83 u8 reg;84 85 do {86 reg = RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE);87 if (reg & 2)88 return 0;89 90 mdelay(5);91 timeout -= 5;92 } while (timeout > 1);93 94 dev_err(adev->dev, "Doesn't get TRN_MSG_ACK from pf in %d msec \n", NV_MAILBOX_POLL_ACK_TIMEDOUT);95 96 return -ETIME;97}98 99static int xgpu_nv_poll_msg(struct amdgpu_device *adev, enum idh_event event)100{101 int r;102 uint64_t timeout, now;103 104 now = (uint64_t)ktime_to_ms(ktime_get());105 timeout = now + NV_MAILBOX_POLL_MSG_TIMEDOUT;106 107 do {108 r = xgpu_nv_mailbox_rcv_msg(adev, event);109 if (!r) {110 dev_dbg(adev->dev, "rcv_msg 0x%x after %llu ms\n", event, NV_MAILBOX_POLL_MSG_TIMEDOUT - timeout + now);111 return 0;112 }113 114 msleep(10);115 now = (uint64_t)ktime_to_ms(ktime_get());116 } while (timeout > now);117 118 dev_dbg(adev->dev, "nv_poll_msg timed out\n");119 120 return -ETIME;121}122 123static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev,124 enum idh_request req, u32 data1, u32 data2, u32 data3)125{126 int r;127 uint8_t trn;128 129 /* IMPORTANT:130 * clear TRN_MSG_VALID valid to clear host's RCV_MSG_ACK131 * and with host's RCV_MSG_ACK cleared hw automatically clear host's RCV_MSG_ACK132 * which lead to VF's TRN_MSG_ACK cleared, otherwise below xgpu_nv_poll_ack()133 * will return immediatly134 */135 do {136 xgpu_nv_mailbox_set_valid(adev, false);137 trn = xgpu_nv_peek_ack(adev);138 if (trn) {139 dev_err_ratelimited(adev->dev, "trn=%x ACK should not assert! wait again !\n", trn);140 msleep(1);141 }142 } while (trn);143 144 dev_dbg(adev->dev, "trans_msg req = 0x%x, data1 = 0x%x\n", req, data1);145 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, req);146 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW1, data1);147 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW2, data2);148 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW3, data3);149 xgpu_nv_mailbox_set_valid(adev, true);150 151 /* start to poll ack */152 r = xgpu_nv_poll_ack(adev);153 if (r)154 dev_err(adev->dev, "Doesn't get ack from pf, continue\n");155 156 xgpu_nv_mailbox_set_valid(adev, false);157}158 159static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev,160 enum idh_request req, u32 data1, u32 data2, u32 data3)161{162 int r, retry = 1;163 enum idh_event event = -1;164 165send_request:166 xgpu_nv_mailbox_trans_msg(adev, req, data1, data2, data3);167 168 switch (req) {169 case IDH_REQ_GPU_INIT_ACCESS:170 case IDH_REQ_GPU_FINI_ACCESS:171 case IDH_REQ_GPU_RESET_ACCESS:172 event = IDH_READY_TO_ACCESS_GPU;173 break;174 case IDH_REQ_GPU_INIT_DATA:175 event = IDH_REQ_GPU_INIT_DATA_READY;176 break;177 case IDH_RAS_POISON:178 if (data1 != 0)179 event = IDH_RAS_POISON_READY;180 break;181 default:182 break;183 }184 185 if (event != -1) {186 r = xgpu_nv_poll_msg(adev, event);187 if (r) {188 if (retry++ < 5)189 goto send_request;190 191 if (req != IDH_REQ_GPU_INIT_DATA) {192 dev_err(adev->dev, "Doesn't get msg:%d from pf, error=%d\n", event, r);193 return r;194 } else /* host doesn't support REQ_GPU_INIT_DATA handshake */195 adev->virt.req_init_data_ver = 0;196 } else {197 if (req == IDH_REQ_GPU_INIT_DATA) {198 adev->virt.req_init_data_ver =199 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1);200 201 /* assume V1 in case host doesn't set version number */202 if (adev->virt.req_init_data_ver < 1)203 adev->virt.req_init_data_ver = 1;204 }205 }206 207 /* Retrieve checksum from mailbox2 */208 if (req == IDH_REQ_GPU_INIT_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) {209 adev->virt.fw_reserve.checksum_key =210 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2);211 }212 }213 214 return 0;215}216 217static int xgpu_nv_send_access_requests(struct amdgpu_device *adev,218 enum idh_request req)219{220 return xgpu_nv_send_access_requests_with_param(adev,221 req, 0, 0, 0);222}223 224static int xgpu_nv_request_reset(struct amdgpu_device *adev)225{226 int ret, i = 0;227 228 while (i < NV_MAILBOX_POLL_MSG_REP_MAX) {229 ret = xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);230 if (!ret)231 break;232 i++;233 }234 235 return ret;236}237 238static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev,239 bool init)240{241 enum idh_request req;242 243 req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;244 return xgpu_nv_send_access_requests(adev, req);245}246 247static int xgpu_nv_release_full_gpu_access(struct amdgpu_device *adev,248 bool init)249{250 enum idh_request req;251 int r = 0;252 253 req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;254 r = xgpu_nv_send_access_requests(adev, req);255 256 return r;257}258 259static int xgpu_nv_request_init_data(struct amdgpu_device *adev)260{261 return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_INIT_DATA);262}263 264static int xgpu_nv_mailbox_ack_irq(struct amdgpu_device *adev,265 struct amdgpu_irq_src *source,266 struct amdgpu_iv_entry *entry)267{268 dev_dbg(adev->dev, "get ack intr and do nothing.\n");269 return 0;270}271 272static int xgpu_nv_set_mailbox_ack_irq(struct amdgpu_device *adev,273 struct amdgpu_irq_src *source,274 unsigned type,275 enum amdgpu_interrupt_state state)276{277 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);278 279 if (state == AMDGPU_IRQ_STATE_ENABLE)280 tmp |= 2;281 else282 tmp &= ~2;283 284 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);285 286 return 0;287}288 289static void xgpu_nv_ready_to_reset(struct amdgpu_device *adev)290{291 xgpu_nv_mailbox_trans_msg(adev, IDH_READY_TO_RESET, 0, 0, 0);292}293 294static int xgpu_nv_wait_reset(struct amdgpu_device *adev)295{296 int timeout = NV_MAILBOX_POLL_FLR_TIMEDOUT;297 do {298 if (xgpu_nv_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL) {299 dev_dbg(adev->dev, "Got NV IDH_FLR_NOTIFICATION_CMPL after %d ms\n", NV_MAILBOX_POLL_FLR_TIMEDOUT - timeout);300 return 0;301 }302 msleep(10);303 timeout -= 10;304 } while (timeout > 1);305 306 dev_dbg(adev->dev, "waiting NV IDH_FLR_NOTIFICATION_CMPL timeout\n");307 return -ETIME;308}309 310static void xgpu_nv_mailbox_flr_work(struct work_struct *work)311{312 struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);313 struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);314 315 amdgpu_virt_fini_data_exchange(adev);316 317 /* Trigger recovery for world switch failure if no TDR */318 if (amdgpu_device_should_recover_gpu(adev)319 && (!amdgpu_device_has_job_running(adev) ||320 adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT ||321 adev->gfx_timeout == MAX_SCHEDULE_TIMEOUT ||322 adev->compute_timeout == MAX_SCHEDULE_TIMEOUT ||323 adev->video_timeout == MAX_SCHEDULE_TIMEOUT)) {324 struct amdgpu_reset_context reset_context;325 memset(&reset_context, 0, sizeof(reset_context));326 327 reset_context.method = AMD_RESET_METHOD_NONE;328 reset_context.reset_req_dev = adev;329 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);330 set_bit(AMDGPU_HOST_FLR, &reset_context.flags);331 332 amdgpu_device_gpu_recover(adev, NULL, &reset_context);333 }334}335 336static int xgpu_nv_set_mailbox_rcv_irq(struct amdgpu_device *adev,337 struct amdgpu_irq_src *src,338 unsigned type,339 enum amdgpu_interrupt_state state)340{341 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);342 343 if (state == AMDGPU_IRQ_STATE_ENABLE)344 tmp |= 1;345 else346 tmp &= ~1;347 348 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);349 350 return 0;351}352 353static int xgpu_nv_mailbox_rcv_irq(struct amdgpu_device *adev,354 struct amdgpu_irq_src *source,355 struct amdgpu_iv_entry *entry)356{357 enum idh_event event = xgpu_nv_mailbox_peek_msg(adev);358 359 switch (event) {360 case IDH_FLR_NOTIFICATION:361 if (amdgpu_sriov_runtime(adev))362 WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,363 &adev->virt.flr_work),364 "Failed to queue work! at %s",365 __func__);366 break;367 /* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore368 * it byfar since that polling thread will handle it,369 * other msg like flr complete is not handled here.370 */371 case IDH_CLR_MSG_BUF:372 case IDH_FLR_NOTIFICATION_CMPL:373 case IDH_READY_TO_ACCESS_GPU:374 default:375 break;376 }377 378 return 0;379}380 381static const struct amdgpu_irq_src_funcs xgpu_nv_mailbox_ack_irq_funcs = {382 .set = xgpu_nv_set_mailbox_ack_irq,383 .process = xgpu_nv_mailbox_ack_irq,384};385 386static const struct amdgpu_irq_src_funcs xgpu_nv_mailbox_rcv_irq_funcs = {387 .set = xgpu_nv_set_mailbox_rcv_irq,388 .process = xgpu_nv_mailbox_rcv_irq,389};390 391void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev)392{393 adev->virt.ack_irq.num_types = 1;394 adev->virt.ack_irq.funcs = &xgpu_nv_mailbox_ack_irq_funcs;395 adev->virt.rcv_irq.num_types = 1;396 adev->virt.rcv_irq.funcs = &xgpu_nv_mailbox_rcv_irq_funcs;397}398 399int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev)400{401 int r;402 403 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);404 if (r)405 return r;406 407 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);408 if (r) {409 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);410 return r;411 }412 413 return 0;414}415 416int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev)417{418 int r;419 420 r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);421 if (r)422 return r;423 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);424 if (r) {425 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);426 return r;427 }428 429 INIT_WORK(&adev->virt.flr_work, xgpu_nv_mailbox_flr_work);430 431 return 0;432}433 434void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev)435{436 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);437 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);438}439 440static void xgpu_nv_ras_poison_handler(struct amdgpu_device *adev,441 enum amdgpu_ras_block block)442{443 if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) {444 xgpu_nv_send_access_requests(adev, IDH_RAS_POISON);445 } else {446 amdgpu_virt_fini_data_exchange(adev);447 xgpu_nv_send_access_requests_with_param(adev,448 IDH_RAS_POISON, block, 0, 0);449 }450}451 452static bool xgpu_nv_rcvd_ras_intr(struct amdgpu_device *adev)453{454 enum idh_event msg = xgpu_nv_mailbox_peek_msg(adev);455 456 return (msg == IDH_RAS_ERROR_DETECTED || msg == 0xFFFFFFFF);457}458 459const struct amdgpu_virt_ops xgpu_nv_virt_ops = {460 .req_full_gpu = xgpu_nv_request_full_gpu_access,461 .rel_full_gpu = xgpu_nv_release_full_gpu_access,462 .req_init_data = xgpu_nv_request_init_data,463 .reset_gpu = xgpu_nv_request_reset,464 .ready_to_reset = xgpu_nv_ready_to_reset,465 .wait_reset = xgpu_nv_wait_reset,466 .trans_msg = xgpu_nv_mailbox_trans_msg,467 .ras_poison_handler = xgpu_nv_ras_poison_handler,468 .rcvd_ras_intr = xgpu_nv_rcvd_ras_intr,469};470