85 lines · c
1/*2 * Copyright 2014 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#ifndef __MXGPU_NV_H__25#define __MXGPU_NV_H__26 27#define NV_MAILBOX_POLL_ACK_TIMEDOUT 50028#define NV_MAILBOX_POLL_MSG_TIMEDOUT 1500029#define NV_MAILBOX_POLL_FLR_TIMEDOUT 1000030#define NV_MAILBOX_POLL_MSG_REP_MAX 1131 32enum idh_request {33 IDH_REQ_GPU_INIT_ACCESS = 1,34 IDH_REL_GPU_INIT_ACCESS,35 IDH_REQ_GPU_FINI_ACCESS,36 IDH_REL_GPU_FINI_ACCESS,37 IDH_REQ_GPU_RESET_ACCESS,38 IDH_REQ_GPU_INIT_DATA,39 40 IDH_LOG_VF_ERROR = 200,41 IDH_READY_TO_RESET = 201,42 IDH_RAS_POISON = 202,43};44 45enum idh_event {46 IDH_CLR_MSG_BUF = 0,47 IDH_READY_TO_ACCESS_GPU,48 IDH_FLR_NOTIFICATION,49 IDH_FLR_NOTIFICATION_CMPL,50 IDH_SUCCESS,51 IDH_FAIL,52 IDH_QUERY_ALIVE,53 IDH_REQ_GPU_INIT_DATA_READY,54 IDH_RAS_POISON_READY,55 IDH_PF_SOFT_FLR_NOTIFICATION,56 IDH_RAS_ERROR_DETECTED,57 IDH_TEXT_MESSAGE = 255,58};59 60extern const struct amdgpu_virt_ops xgpu_nv_virt_ops;61 62void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev);63int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev);64int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev);65void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev);66 67#define mmMAILBOX_CONTROL 0xE5E68 69#define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (mmMAILBOX_CONTROL * 4)70#define NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE (NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE + 1)71 72#define mmMAILBOX_MSGBUF_TRN_DW0 0xE5673#define mmMAILBOX_MSGBUF_TRN_DW1 0xE5774#define mmMAILBOX_MSGBUF_TRN_DW2 0xE5875#define mmMAILBOX_MSGBUF_TRN_DW3 0xE5976 77#define mmMAILBOX_MSGBUF_RCV_DW0 0xE5A78#define mmMAILBOX_MSGBUF_RCV_DW1 0xE5B79#define mmMAILBOX_MSGBUF_RCV_DW2 0xE5C80#define mmMAILBOX_MSGBUF_RCV_DW3 0xE5D81 82#define mmMAILBOX_INT_CNTL 0xE5F83 84#endif85