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1/*2 * Copyright (C) 2019 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included12 * in all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.20 *21 */22 23#ifndef __NAVI10_SDMA_PKT_OPEN_H_24#define __NAVI10_SDMA_PKT_OPEN_H_25 26#define SDMA_OP_NOP 027#define SDMA_OP_COPY 128#define SDMA_OP_WRITE 229#define SDMA_OP_INDIRECT 430#define SDMA_OP_FENCE 531#define SDMA_OP_TRAP 632#define SDMA_OP_SEM 733#define SDMA_OP_POLL_REGMEM 834#define SDMA_OP_COND_EXE 935#define SDMA_OP_ATOMIC 1036#define SDMA_OP_CONST_FILL 1137#define SDMA_OP_PTEPDE 1238#define SDMA_OP_TIMESTAMP 1339#define SDMA_OP_SRBM_WRITE 1440#define SDMA_OP_PRE_EXE 1541#define SDMA_OP_GPUVM_INV 1642#define SDMA_OP_GCR_REQ 1743#define SDMA_OP_DUMMY_TRAP 3244#define SDMA_SUBOP_TIMESTAMP_SET 045#define SDMA_SUBOP_TIMESTAMP_GET 146#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 247#define SDMA_SUBOP_COPY_LINEAR 048#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 449#define SDMA_SUBOP_COPY_TILED 150#define SDMA_SUBOP_COPY_TILED_SUB_WIND 551#define SDMA_SUBOP_COPY_T2T_SUB_WIND 652#define SDMA_SUBOP_COPY_SOA 353#define SDMA_SUBOP_COPY_DIRTY_PAGE 754#define SDMA_SUBOP_COPY_LINEAR_PHY 855#define SDMA_SUBOP_COPY_LINEAR_BC 1656#define SDMA_SUBOP_COPY_TILED_BC 1757#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC 2058#define SDMA_SUBOP_COPY_TILED_SUB_WIND_BC 2159#define SDMA_SUBOP_COPY_T2T_SUB_WIND_BC 2260#define SDMA_SUBOP_WRITE_LINEAR 061#define SDMA_SUBOP_WRITE_TILED 162#define SDMA_SUBOP_WRITE_TILED_BC 1763#define SDMA_SUBOP_PTEPDE_GEN 064#define SDMA_SUBOP_PTEPDE_COPY 165#define SDMA_SUBOP_PTEPDE_RMW 266#define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 367#define SDMA_SUBOP_DATA_FILL_MULTI 168#define SDMA_SUBOP_POLL_REG_WRITE_MEM 169#define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 270#define SDMA_SUBOP_POLL_MEM_VERIFY 371#define HEADER_AGENT_DISPATCH 472#define HEADER_BARRIER 573#define SDMA_OP_AQL_COPY 074#define SDMA_OP_AQL_BARRIER_OR 075 76#define SDMA_GCR_RANGE_IS_PA (1 << 18)77#define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16)78#define SDMA_GCR_GL2_WB (1 << 15)79#define SDMA_GCR_GL2_INV (1 << 14)80#define SDMA_GCR_GL2_DISCARD (1 << 13)81#define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11)82#define SDMA_GCR_GL2_US (1 << 10)83#define SDMA_GCR_GL1_INV (1 << 9)84#define SDMA_GCR_GLV_INV (1 << 8)85#define SDMA_GCR_GLK_INV (1 << 7)86#define SDMA_GCR_GLK_WB (1 << 6)87#define SDMA_GCR_GLM_INV (1 << 5)88#define SDMA_GCR_GLM_WB (1 << 4)89#define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2)90#define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0)91 92/*define for op field*/93#define SDMA_PKT_HEADER_op_offset 094#define SDMA_PKT_HEADER_op_mask 0x000000FF95#define SDMA_PKT_HEADER_op_shift 096#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift)97 98/*define for sub_op field*/99#define SDMA_PKT_HEADER_sub_op_offset 0100#define SDMA_PKT_HEADER_sub_op_mask 0x000000FF101#define SDMA_PKT_HEADER_sub_op_shift 8102#define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift)103 104/*105** Definitions for SDMA_PKT_COPY_LINEAR packet106*/107 108/*define for HEADER word*/109/*define for op field*/110#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0111#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF112#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0113#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift)114 115/*define for sub_op field*/116#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0117#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF118#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8119#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift)120 121/*define for encrypt field*/122#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0123#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001124#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16125#define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift)126 127/*define for tmz field*/128#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0129#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001130#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18131#define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift)132 133/*define for backwards field*/134#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset 0135#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask 0x00000001136#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift 25137#define SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask) << SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift)138 139/*define for broadcast field*/140#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0141#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001142#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27143#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift)144 145/*define for COUNT word*/146/*define for count field*/147#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1148#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF149#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0150#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift)151 152/*define for PARAMETER word*/153/*define for dst_sw field*/154#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2155#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003156#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16157#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift)158 159/*define for src_sw field*/160#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2161#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003162#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24163#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift)164 165/*define for SRC_ADDR_LO word*/166/*define for src_addr_31_0 field*/167#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3168#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF169#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0170#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)171 172/*define for SRC_ADDR_HI word*/173/*define for src_addr_63_32 field*/174#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4175#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF176#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0177#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)178 179/*define for DST_ADDR_LO word*/180/*define for dst_addr_31_0 field*/181#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5182#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF183#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0184#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)185 186/*define for DST_ADDR_HI word*/187/*define for dst_addr_63_32 field*/188#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6189#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF190#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0191#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)192 193 194/*195** Definitions for SDMA_PKT_COPY_LINEAR_BC packet196*/197 198/*define for HEADER word*/199/*define for op field*/200#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset 0201#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask 0x000000FF202#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift 0203#define SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift)204 205/*define for sub_op field*/206#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset 0207#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask 0x000000FF208#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift 8209#define SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift)210 211/*define for COUNT word*/212/*define for count field*/213#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset 1214#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask 0x003FFFFF215#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift 0216#define SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift)217 218/*define for PARAMETER word*/219/*define for dst_sw field*/220#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset 2221#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask 0x00000003222#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift 16223#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift)224 225/*define for dst_ha field*/226#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset 2227#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask 0x00000001228#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift 22229#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift)230 231/*define for src_sw field*/232#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset 2233#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask 0x00000003234#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift 24235#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift)236 237/*define for src_ha field*/238#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset 2239#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask 0x00000001240#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift 30241#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift)242 243/*define for SRC_ADDR_LO word*/244/*define for src_addr_31_0 field*/245#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset 3246#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF247#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift 0248#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift)249 250/*define for SRC_ADDR_HI word*/251/*define for src_addr_63_32 field*/252#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset 4253#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF254#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift 0255#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift)256 257/*define for DST_ADDR_LO word*/258/*define for dst_addr_31_0 field*/259#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset 5260#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF261#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift 0262#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift)263 264/*define for DST_ADDR_HI word*/265/*define for dst_addr_63_32 field*/266#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset 6267#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF268#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift 0269#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift)270 271 272/*273** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet274*/275 276/*define for HEADER word*/277/*define for op field*/278#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0279#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF280#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0281#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift)282 283/*define for sub_op field*/284#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0285#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF286#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8287#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift)288 289/*define for tmz field*/290#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0291#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001292#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18293#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift)294 295/*define for all field*/296#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0297#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001298#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31299#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift)300 301/*define for COUNT word*/302/*define for count field*/303#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1304#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF305#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0306#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift)307 308/*define for PARAMETER word*/309/*define for dst_mtype field*/310#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset 2311#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask 0x00000007312#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift 3313#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift)314 315/*define for dst_l2_policy field*/316#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset 2317#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask 0x00000003318#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift 6319#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift)320 321/*define for src_mtype field*/322#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset 2323#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask 0x00000007324#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift 11325#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift)326 327/*define for src_l2_policy field*/328#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset 2329#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask 0x00000003330#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift 14331#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift)332 333/*define for dst_sw field*/334#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2335#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003336#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 16337#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift)338 339/*define for dst_gcc field*/340#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2341#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001342#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19343#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift)344 345/*define for dst_sys field*/346#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2347#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001348#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20349#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift)350 351/*define for dst_snoop field*/352#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2353#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001354#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22355#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift)356 357/*define for dst_gpa field*/358#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2359#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001360#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23361#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift)362 363/*define for src_sw field*/364#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2365#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003366#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24367#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift)368 369/*define for src_sys field*/370#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2371#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001372#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28373#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift)374 375/*define for src_snoop field*/376#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2377#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001378#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30379#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift)380 381/*define for src_gpa field*/382#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2383#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001384#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31385#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift)386 387/*define for SRC_ADDR_LO word*/388/*define for src_addr_31_0 field*/389#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3390#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF391#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0392#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift)393 394/*define for SRC_ADDR_HI word*/395/*define for src_addr_63_32 field*/396#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4397#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF398#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0399#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift)400 401/*define for DST_ADDR_LO word*/402/*define for dst_addr_31_0 field*/403#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5404#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF405#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0406#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift)407 408/*define for DST_ADDR_HI word*/409/*define for dst_addr_63_32 field*/410#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6411#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF412#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0413#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift)414 415 416/*417** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet418*/419 420/*define for HEADER word*/421/*define for op field*/422#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0423#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF424#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0425#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift)426 427/*define for sub_op field*/428#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0429#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF430#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8431#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift)432 433/*define for tmz field*/434#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0435#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001436#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18437#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift)438 439/*define for COUNT word*/440/*define for count field*/441#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1442#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF443#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0444#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift)445 446/*define for PARAMETER word*/447/*define for dst_mtype field*/448#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset 2449#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask 0x00000007450#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift 3451#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift)452 453/*define for dst_l2_policy field*/454#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset 2455#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask 0x00000003456#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift 6457#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift)458 459/*define for src_mtype field*/460#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset 2461#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask 0x00000007462#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift 11463#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift)464 465/*define for src_l2_policy field*/466#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset 2467#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask 0x00000003468#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift 14469#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift)470 471/*define for dst_sw field*/472#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2473#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003474#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 16475#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift)476 477/*define for dst_gcc field*/478#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2479#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001480#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19481#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift)482 483/*define for dst_sys field*/484#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2485#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001486#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20487#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift)488 489/*define for dst_log field*/490#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2491#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001492#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21493#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift)494 495/*define for dst_snoop field*/496#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2497#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001498#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22499#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift)500 501/*define for dst_gpa field*/502#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2503#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001504#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23505#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift)506 507/*define for src_sw field*/508#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2509#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003510#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24511#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift)512 513/*define for src_gcc field*/514#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2515#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001516#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27517#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift)518 519/*define for src_sys field*/520#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2521#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001522#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28523#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift)524 525/*define for src_snoop field*/526#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2527#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001528#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30529#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift)530 531/*define for src_gpa field*/532#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2533#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001534#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31535#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift)536 537/*define for SRC_ADDR_LO word*/538/*define for src_addr_31_0 field*/539#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3540#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF541#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0542#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)543 544/*define for SRC_ADDR_HI word*/545/*define for src_addr_63_32 field*/546#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4547#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF548#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0549#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)550 551/*define for DST_ADDR_LO word*/552/*define for dst_addr_31_0 field*/553#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5554#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF555#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0556#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)557 558/*define for DST_ADDR_HI word*/559/*define for dst_addr_63_32 field*/560#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6561#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF562#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0563#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)564 565 566/*567** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet568*/569 570/*define for HEADER word*/571/*define for op field*/572#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0573#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF574#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0575#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift)576 577/*define for sub_op field*/578#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0579#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF580#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8581#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift)582 583/*define for encrypt field*/584#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0585#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001586#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16587#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift)588 589/*define for tmz field*/590#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0591#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001592#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18593#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift)594 595/*define for broadcast field*/596#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0597#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001598#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27599#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift)600 601/*define for COUNT word*/602/*define for count field*/603#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1604#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF605#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0606#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift)607 608/*define for PARAMETER word*/609/*define for dst2_sw field*/610#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2611#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003612#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8613#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift)614 615/*define for dst1_sw field*/616#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2617#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003618#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16619#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift)620 621/*define for src_sw field*/622#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2623#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003624#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24625#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift)626 627/*define for SRC_ADDR_LO word*/628/*define for src_addr_31_0 field*/629#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3630#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF631#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0632#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)633 634/*define for SRC_ADDR_HI word*/635/*define for src_addr_63_32 field*/636#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4637#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF638#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0639#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)640 641/*define for DST1_ADDR_LO word*/642/*define for dst1_addr_31_0 field*/643#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5644#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF645#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0646#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift)647 648/*define for DST1_ADDR_HI word*/649/*define for dst1_addr_63_32 field*/650#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6651#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF652#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0653#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift)654 655/*define for DST2_ADDR_LO word*/656/*define for dst2_addr_31_0 field*/657#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7658#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF659#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0660#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift)661 662/*define for DST2_ADDR_HI word*/663/*define for dst2_addr_63_32 field*/664#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8665#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF666#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0667#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift)668 669 670/*671** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet672*/673 674/*define for HEADER word*/675/*define for op field*/676#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0677#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF678#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0679#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift)680 681/*define for sub_op field*/682#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0683#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF684#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8685#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift)686 687/*define for tmz field*/688#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0689#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001690#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18691#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift)692 693/*define for elementsize field*/694#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0695#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007696#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29697#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift)698 699/*define for SRC_ADDR_LO word*/700/*define for src_addr_31_0 field*/701#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1702#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF703#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0704#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift)705 706/*define for SRC_ADDR_HI word*/707/*define for src_addr_63_32 field*/708#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2709#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF710#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0711#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift)712 713/*define for DW_3 word*/714/*define for src_x field*/715#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3716#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF717#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0718#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift)719 720/*define for src_y field*/721#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3722#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF723#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16724#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift)725 726/*define for DW_4 word*/727/*define for src_z field*/728#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4729#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x00001FFF730#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0731#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift)732 733/*define for src_pitch field*/734#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4735#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF736#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13737#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift)738 739/*define for DW_5 word*/740/*define for src_slice_pitch field*/741#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5742#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF743#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0744#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift)745 746/*define for DST_ADDR_LO word*/747/*define for dst_addr_31_0 field*/748#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6749#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF750#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0751#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift)752 753/*define for DST_ADDR_HI word*/754/*define for dst_addr_63_32 field*/755#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7756#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF757#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0758#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift)759 760/*define for DW_8 word*/761/*define for dst_x field*/762#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8763#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF764#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0765#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift)766 767/*define for dst_y field*/768#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8769#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF770#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16771#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift)772 773/*define for DW_9 word*/774/*define for dst_z field*/775#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9776#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x00001FFF777#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0778#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift)779 780/*define for dst_pitch field*/781#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9782#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF783#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13784#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift)785 786/*define for DW_10 word*/787/*define for dst_slice_pitch field*/788#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10789#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF790#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0791#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift)792 793/*define for DW_11 word*/794/*define for rect_x field*/795#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11796#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF797#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0798#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift)799 800/*define for rect_y field*/801#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11802#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF803#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16804#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift)805 806/*define for DW_12 word*/807/*define for rect_z field*/808#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12809#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x00001FFF810#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0811#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift)812 813/*define for dst_sw field*/814#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12815#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003816#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16817#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift)818 819/*define for src_sw field*/820#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12821#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003822#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24823#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift)824 825 826/*827** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_BC packet828*/829 830/*define for HEADER word*/831/*define for op field*/832#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset 0833#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask 0x000000FF834#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift 0835#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift)836 837/*define for sub_op field*/838#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset 0839#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF840#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift 8841#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift)842 843/*define for elementsize field*/844#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset 0845#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask 0x00000007846#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift 29847#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift)848 849/*define for SRC_ADDR_LO word*/850/*define for src_addr_31_0 field*/851#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset 1852#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF853#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift 0854#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift)855 856/*define for SRC_ADDR_HI word*/857/*define for src_addr_63_32 field*/858#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset 2859#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF860#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift 0861#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift)862 863/*define for DW_3 word*/864/*define for src_x field*/865#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset 3866#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask 0x00003FFF867#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift 0868#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift)869 870/*define for src_y field*/871#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset 3872#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask 0x00003FFF873#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift 16874#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift)875 876/*define for DW_4 word*/877/*define for src_z field*/878#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset 4879#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask 0x000007FF880#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift 0881#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift)882 883/*define for src_pitch field*/884#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset 4885#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask 0x00003FFF886#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift 13887#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift)888 889/*define for DW_5 word*/890/*define for src_slice_pitch field*/891#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset 5892#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask 0x0FFFFFFF893#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift 0894#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift)895 896/*define for DST_ADDR_LO word*/897/*define for dst_addr_31_0 field*/898#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset 6899#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF900#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift 0901#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift)902 903/*define for DST_ADDR_HI word*/904/*define for dst_addr_63_32 field*/905#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset 7906#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF907#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift 0908#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift)909 910/*define for DW_8 word*/911/*define for dst_x field*/912#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset 8913#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask 0x00003FFF914#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift 0915#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift)916 917/*define for dst_y field*/918#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset 8919#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask 0x00003FFF920#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift 16921#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift)922 923/*define for DW_9 word*/924/*define for dst_z field*/925#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset 9926#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask 0x000007FF927#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift 0928#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift)929 930/*define for dst_pitch field*/931#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset 9932#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask 0x00003FFF933#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift 13934#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift)935 936/*define for DW_10 word*/937/*define for dst_slice_pitch field*/938#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset 10939#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask 0x0FFFFFFF940#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift 0941#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift)942 943/*define for DW_11 word*/944/*define for rect_x field*/945#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset 11946#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask 0x00003FFF947#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift 0948#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift)949 950/*define for rect_y field*/951#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset 11952#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask 0x00003FFF953#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift 16954#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift)955 956/*define for DW_12 word*/957/*define for rect_z field*/958#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset 12959#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask 0x000007FF960#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift 0961#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift)962 963/*define for dst_sw field*/964#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset 12965#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask 0x00000003966#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift 16967#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift)968 969/*define for dst_ha field*/970#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset 12971#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask 0x00000001972#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift 22973#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift)974 975/*define for src_sw field*/976#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset 12977#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask 0x00000003978#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift 24979#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift)980 981/*define for src_ha field*/982#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset 12983#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask 0x00000001984#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift 30985#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift)986 987 988/*989** Definitions for SDMA_PKT_COPY_TILED packet990*/991 992/*define for HEADER word*/993/*define for op field*/994#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0995#define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF996#define SDMA_PKT_COPY_TILED_HEADER_op_shift 0997#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift)998 999/*define for sub_op field*/1000#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 01001#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF1002#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 81003#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift)1004 1005/*define for encrypt field*/1006#define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 01007#define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x000000011008#define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 161009#define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift)1010 1011/*define for tmz field*/1012#define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 01013#define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x000000011014#define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 181015#define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift)1016 1017/*define for detile field*/1018#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 01019#define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x000000011020#define SDMA_PKT_COPY_TILED_HEADER_detile_shift 311021#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift)1022 1023/*define for TILED_ADDR_LO word*/1024/*define for tiled_addr_31_0 field*/1025#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 11026#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF1027#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 01028#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift)1029 1030/*define for TILED_ADDR_HI word*/1031/*define for tiled_addr_63_32 field*/1032#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 21033#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF1034#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 01035#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift)1036 1037/*define for DW_3 word*/1038/*define for width field*/1039#define SDMA_PKT_COPY_TILED_DW_3_width_offset 31040#define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF1041#define SDMA_PKT_COPY_TILED_DW_3_width_shift 01042#define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift)1043 1044/*define for DW_4 word*/1045/*define for height field*/1046#define SDMA_PKT_COPY_TILED_DW_4_height_offset 41047#define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF1048#define SDMA_PKT_COPY_TILED_DW_4_height_shift 01049#define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift)1050 1051/*define for depth field*/1052#define SDMA_PKT_COPY_TILED_DW_4_depth_offset 41053#define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x00001FFF1054#define SDMA_PKT_COPY_TILED_DW_4_depth_shift 161055#define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift)1056 1057/*define for DW_5 word*/1058/*define for element_size field*/1059#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 51060#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x000000071061#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 01062#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift)1063 1064/*define for swizzle_mode field*/1065#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 51066#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F1067#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 31068#define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift)1069 1070/*define for dimension field*/1071#define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 51072#define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x000000031073#define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 91074#define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift)1075 1076/*define for mip_max field*/1077#define SDMA_PKT_COPY_TILED_DW_5_mip_max_offset 51078#define SDMA_PKT_COPY_TILED_DW_5_mip_max_mask 0x0000000F1079#define SDMA_PKT_COPY_TILED_DW_5_mip_max_shift 161080#define SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mip_max_mask) << SDMA_PKT_COPY_TILED_DW_5_mip_max_shift)1081 1082/*define for DW_6 word*/1083/*define for x field*/1084#define SDMA_PKT_COPY_TILED_DW_6_x_offset 61085#define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF1086#define SDMA_PKT_COPY_TILED_DW_6_x_shift 01087#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift)1088 1089/*define for y field*/1090#define SDMA_PKT_COPY_TILED_DW_6_y_offset 61091#define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF1092#define SDMA_PKT_COPY_TILED_DW_6_y_shift 161093#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift)1094 1095/*define for DW_7 word*/1096/*define for z field*/1097#define SDMA_PKT_COPY_TILED_DW_7_z_offset 71098#define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00001FFF1099#define SDMA_PKT_COPY_TILED_DW_7_z_shift 01100#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift)1101 1102/*define for linear_sw field*/1103#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 71104#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x000000031105#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 161106#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift)1107 1108/*define for linear_cc field*/1109#define SDMA_PKT_COPY_TILED_DW_7_linear_cc_offset 71110#define SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask 0x000000011111#define SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift 201112#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_CC(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift)1113 1114/*define for tile_sw field*/1115#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 71116#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x000000031117#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 241118#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift)1119 1120/*define for LINEAR_ADDR_LO word*/1121/*define for linear_addr_31_0 field*/1122#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 81123#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF1124#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 01125#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift)1126 1127/*define for LINEAR_ADDR_HI word*/1128/*define for linear_addr_63_32 field*/1129#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 91130#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF1131#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 01132#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift)1133 1134/*define for LINEAR_PITCH word*/1135/*define for linear_pitch field*/1136#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 101137#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF1138#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 01139#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift)1140 1141/*define for LINEAR_SLICE_PITCH word*/1142/*define for linear_slice_pitch field*/1143#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 111144#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF1145#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 01146#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift)1147 1148/*define for COUNT word*/1149/*define for count field*/1150#define SDMA_PKT_COPY_TILED_COUNT_count_offset 121151#define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x003FFFFF1152#define SDMA_PKT_COPY_TILED_COUNT_count_shift 01153#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift)1154 1155 1156/*1157** Definitions for SDMA_PKT_COPY_TILED_BC packet1158*/1159 1160/*define for HEADER word*/1161/*define for op field*/1162#define SDMA_PKT_COPY_TILED_BC_HEADER_op_offset 01163#define SDMA_PKT_COPY_TILED_BC_HEADER_op_mask 0x000000FF1164#define SDMA_PKT_COPY_TILED_BC_HEADER_op_shift 01165#define SDMA_PKT_COPY_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_op_shift)1166 1167/*define for sub_op field*/1168#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset 01169#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask 0x000000FF1170#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift 81171#define SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift)1172 1173/*define for detile field*/1174#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset 01175#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask 0x000000011176#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift 311177#define SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift)1178 1179/*define for TILED_ADDR_LO word*/1180/*define for tiled_addr_31_0 field*/1181#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 11182#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF1183#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 01184#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift)1185 1186/*define for TILED_ADDR_HI word*/1187/*define for tiled_addr_63_32 field*/1188#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 21189#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF1190#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 01191#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift)1192 1193/*define for DW_3 word*/1194/*define for width field*/1195#define SDMA_PKT_COPY_TILED_BC_DW_3_width_offset 31196#define SDMA_PKT_COPY_TILED_BC_DW_3_width_mask 0x00003FFF1197#define SDMA_PKT_COPY_TILED_BC_DW_3_width_shift 01198#define SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_3_width_mask) << SDMA_PKT_COPY_TILED_BC_DW_3_width_shift)1199 1200/*define for DW_4 word*/1201/*define for height field*/1202#define SDMA_PKT_COPY_TILED_BC_DW_4_height_offset 41203#define SDMA_PKT_COPY_TILED_BC_DW_4_height_mask 0x00003FFF1204#define SDMA_PKT_COPY_TILED_BC_DW_4_height_shift 01205#define SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_height_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_height_shift)1206 1207/*define for depth field*/1208#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset 41209#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask 0x000007FF1210#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift 161211#define SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift)1212 1213/*define for DW_5 word*/1214/*define for element_size field*/1215#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset 51216#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask 0x000000071217#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift 01218#define SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift)1219 1220/*define for array_mode field*/1221#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset 51222#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask 0x0000000F1223#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift 31224#define SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift)1225 1226/*define for mit_mode field*/1227#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset 51228#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask 0x000000071229#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift 81230#define SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift)1231 1232/*define for tilesplit_size field*/1233#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset 51234#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask 0x000000071235#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift 111236#define SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift)1237 1238/*define for bank_w field*/1239#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset 51240#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask 0x000000031241#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift 151242#define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift)1243 1244/*define for bank_h field*/1245#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset 51246#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask 0x000000031247#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift 181248#define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift)1249 1250/*define for num_bank field*/1251#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset 51252#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask 0x000000031253#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift 211254#define SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift)1255 1256/*define for mat_aspt field*/1257#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset 51258#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask 0x000000031259#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift 241260#define SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift)1261 1262/*define for pipe_config field*/1263#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset 51264#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask 0x0000001F1265#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift 261266#define SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift)1267 1268/*define for DW_6 word*/1269/*define for x field*/1270#define SDMA_PKT_COPY_TILED_BC_DW_6_x_offset 61271#define SDMA_PKT_COPY_TILED_BC_DW_6_x_mask 0x00003FFF1272#define SDMA_PKT_COPY_TILED_BC_DW_6_x_shift 01273#define SDMA_PKT_COPY_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_x_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_x_shift)1274 1275/*define for y field*/1276#define SDMA_PKT_COPY_TILED_BC_DW_6_y_offset 61277#define SDMA_PKT_COPY_TILED_BC_DW_6_y_mask 0x00003FFF1278#define SDMA_PKT_COPY_TILED_BC_DW_6_y_shift 161279#define SDMA_PKT_COPY_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_y_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_y_shift)1280 1281/*define for DW_7 word*/1282/*define for z field*/1283#define SDMA_PKT_COPY_TILED_BC_DW_7_z_offset 71284#define SDMA_PKT_COPY_TILED_BC_DW_7_z_mask 0x000007FF1285#define SDMA_PKT_COPY_TILED_BC_DW_7_z_shift 01286#define SDMA_PKT_COPY_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_z_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_z_shift)1287 1288/*define for linear_sw field*/1289#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset 71290#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask 0x000000031291#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift 161292#define SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift)1293 1294/*define for tile_sw field*/1295#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset 71296#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask 0x000000031297#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift 241298#define SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift)1299 1300/*define for LINEAR_ADDR_LO word*/1301/*define for linear_addr_31_0 field*/1302#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 81303#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF1304#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 01305#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift)1306 1307/*define for LINEAR_ADDR_HI word*/1308/*define for linear_addr_63_32 field*/1309#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 91310#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF1311#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 01312#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift)1313 1314/*define for LINEAR_PITCH word*/1315/*define for linear_pitch field*/1316#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset 101317#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF1318#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift 01319#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift)1320 1321/*define for COUNT word*/1322/*define for count field*/1323#define SDMA_PKT_COPY_TILED_BC_COUNT_count_offset 111324#define SDMA_PKT_COPY_TILED_BC_COUNT_count_mask 0x000FFFFF1325#define SDMA_PKT_COPY_TILED_BC_COUNT_count_shift 21326#define SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_BC_COUNT_count_mask) << SDMA_PKT_COPY_TILED_BC_COUNT_count_shift)1327 1328 1329/*1330** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet1331*/1332 1333/*define for HEADER word*/1334/*define for op field*/1335#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 01336#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF1337#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 01338#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift)1339 1340/*define for sub_op field*/1341#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 01342#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF1343#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 81344#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift)1345 1346/*define for encrypt field*/1347#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 01348#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x000000011349#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 161350#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift)1351 1352/*define for tmz field*/1353#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 01354#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x000000011355#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 181356#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift)1357 1358/*define for videocopy field*/1359#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 01360#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x000000011361#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 261362#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift)1363 1364/*define for broadcast field*/1365#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 01366#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x000000011367#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 271368#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift)1369 1370/*define for TILED_ADDR_LO_0 word*/1371/*define for tiled_addr0_31_0 field*/1372#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 11373#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF1374#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 01375#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift)1376 1377/*define for TILED_ADDR_HI_0 word*/1378/*define for tiled_addr0_63_32 field*/1379#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 21380#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF1381#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 01382#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift)1383 1384/*define for TILED_ADDR_LO_1 word*/1385/*define for tiled_addr1_31_0 field*/1386#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 31387#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF1388#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 01389#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift)1390 1391/*define for TILED_ADDR_HI_1 word*/1392/*define for tiled_addr1_63_32 field*/1393#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 41394#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF1395#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 01396#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift)1397 1398/*define for DW_5 word*/1399/*define for width field*/1400#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 51401#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF1402#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 01403#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift)1404 1405/*define for DW_6 word*/1406/*define for height field*/1407#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 61408#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF1409#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 01410#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift)1411 1412/*define for depth field*/1413#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 61414#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x00001FFF1415#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 161416#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift)1417 1418/*define for DW_7 word*/1419/*define for element_size field*/1420#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 71421#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x000000071422#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 01423#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift)1424 1425/*define for swizzle_mode field*/1426#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 71427#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F1428#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 31429#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift)1430 1431/*define for dimension field*/1432#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 71433#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x000000031434#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 91435#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift)1436 1437/*define for mip_max field*/1438#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset 71439#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask 0x0000000F1440#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift 161441#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift)1442 1443/*define for DW_8 word*/1444/*define for x field*/1445#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 81446#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF1447#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 01448#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift)1449 1450/*define for y field*/1451#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 81452#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF1453#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 161454#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift)1455 1456/*define for DW_9 word*/1457/*define for z field*/1458#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 91459#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00001FFF1460#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 01461#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift)1462 1463/*define for DW_10 word*/1464/*define for dst2_sw field*/1465#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 101466#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x000000031467#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 81468#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift)1469 1470/*define for linear_sw field*/1471#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 101472#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x000000031473#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 161474#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift)1475 1476/*define for tile_sw field*/1477#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 101478#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x000000031479#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 241480#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift)1481 1482/*define for LINEAR_ADDR_LO word*/1483/*define for linear_addr_31_0 field*/1484#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 111485#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF1486#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 01487#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift)1488 1489/*define for LINEAR_ADDR_HI word*/1490/*define for linear_addr_63_32 field*/1491#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 121492#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF1493#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 01494#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift)1495 1496/*define for LINEAR_PITCH word*/1497/*define for linear_pitch field*/1498#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 131499#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF1500#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 01501#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift)1502 1503/*define for LINEAR_SLICE_PITCH word*/1504/*define for linear_slice_pitch field*/1505#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 141506#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF1507#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 01508#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift)1509 1510/*define for COUNT word*/1511/*define for count field*/1512#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 151513#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x003FFFFF1514#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 01515#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift)1516 1517 1518/*1519** Definitions for SDMA_PKT_COPY_T2T packet1520*/1521 1522/*define for HEADER word*/1523/*define for op field*/1524#define SDMA_PKT_COPY_T2T_HEADER_op_offset 01525#define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF1526#define SDMA_PKT_COPY_T2T_HEADER_op_shift 01527#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift)1528 1529/*define for sub_op field*/1530#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 01531#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF1532#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 81533#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift)1534 1535/*define for tmz field*/1536#define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 01537#define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x000000011538#define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 181539#define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift)1540 1541/*define for dcc field*/1542#define SDMA_PKT_COPY_T2T_HEADER_dcc_offset 01543#define SDMA_PKT_COPY_T2T_HEADER_dcc_mask 0x000000011544#define SDMA_PKT_COPY_T2T_HEADER_dcc_shift 191545#define SDMA_PKT_COPY_T2T_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_shift)1546 1547/*define for dcc_dir field*/1548#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset 01549#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask 0x000000011550#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift 311551#define SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift)1552 1553/*define for SRC_ADDR_LO word*/1554/*define for src_addr_31_0 field*/1555#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 11556#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF1557#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 01558#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift)1559 1560/*define for SRC_ADDR_HI word*/1561/*define for src_addr_63_32 field*/1562#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 21563#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF1564#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 01565#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift)1566 1567/*define for DW_3 word*/1568/*define for src_x field*/1569#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 31570#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF1571#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 01572#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift)1573 1574/*define for src_y field*/1575#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 31576#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF1577#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 161578#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift)1579 1580/*define for DW_4 word*/1581/*define for src_z field*/1582#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 41583#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x00001FFF1584#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 01585#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift)1586 1587/*define for src_width field*/1588#define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 41589#define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF1590#define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 161591#define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift)1592 1593/*define for DW_5 word*/1594/*define for src_height field*/1595#define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 51596#define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF1597#define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 01598#define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift)1599 1600/*define for src_depth field*/1601#define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 51602#define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x00001FFF1603#define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 161604#define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift)1605 1606/*define for DW_6 word*/1607/*define for src_element_size field*/1608#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 61609#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x000000071610#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 01611#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift)1612 1613/*define for src_swizzle_mode field*/1614#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 61615#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F1616#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 31617#define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift)1618 1619/*define for src_dimension field*/1620#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 61621#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x000000031622#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 91623#define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift)1624 1625/*define for src_mip_max field*/1626#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset 61627#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask 0x0000000F1628#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift 161629#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift)1630 1631/*define for src_mip_id field*/1632#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset 61633#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask 0x0000000F1634#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift 201635#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift)1636 1637/*define for DST_ADDR_LO word*/1638/*define for dst_addr_31_0 field*/1639#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 71640#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF1641#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 01642#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift)1643 1644/*define for DST_ADDR_HI word*/1645/*define for dst_addr_63_32 field*/1646#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 81647#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF1648#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 01649#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift)1650 1651/*define for DW_9 word*/1652/*define for dst_x field*/1653#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 91654#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF1655#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 01656#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift)1657 1658/*define for dst_y field*/1659#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 91660#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF1661#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 161662#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift)1663 1664/*define for DW_10 word*/1665/*define for dst_z field*/1666#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 101667#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x00001FFF1668#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 01669#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift)1670 1671/*define for dst_width field*/1672#define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 101673#define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF1674#define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 161675#define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift)1676 1677/*define for DW_11 word*/1678/*define for dst_height field*/1679#define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 111680#define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF1681#define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 01682#define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift)1683 1684/*define for dst_depth field*/1685#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 111686#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x00001FFF1687#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 161688#define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift)1689 1690/*define for DW_12 word*/1691/*define for dst_element_size field*/1692#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 121693#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x000000071694#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 01695#define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift)1696 1697/*define for dst_swizzle_mode field*/1698#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 121699#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F1700#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 31701#define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift)1702 1703/*define for dst_dimension field*/1704#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 121705#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x000000031706#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 91707#define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift)1708 1709/*define for dst_mip_max field*/1710#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset 121711#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask 0x0000000F1712#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift 161713#define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift)1714 1715/*define for dst_mip_id field*/1716#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset 121717#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask 0x0000000F1718#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift 201719#define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift)1720 1721/*define for DW_13 word*/1722/*define for rect_x field*/1723#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 131724#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF1725#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 01726#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift)1727 1728/*define for rect_y field*/1729#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 131730#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF1731#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 161732#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift)1733 1734/*define for DW_14 word*/1735/*define for rect_z field*/1736#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 141737#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x00001FFF1738#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 01739#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift)1740 1741/*define for dst_sw field*/1742#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 141743#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x000000031744#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 161745#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift)1746 1747/*define for src_sw field*/1748#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 141749#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x000000031750#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 241751#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift)1752 1753/*define for META_ADDR_LO word*/1754/*define for meta_addr_31_0 field*/1755#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset 151756#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF1757#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift 01758#define SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift)1759 1760/*define for META_ADDR_HI word*/1761/*define for meta_addr_63_32 field*/1762#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset 161763#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF1764#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift 01765#define SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift)1766 1767/*define for META_CONFIG word*/1768/*define for data_format field*/1769#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset 171770#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask 0x0000007F1771#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift 01772#define SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift)1773 1774/*define for color_transform_disable field*/1775#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset 171776#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask 0x000000011777#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift 71778#define SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift)1779 1780/*define for alpha_is_on_msb field*/1781#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset 171782#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask 0x000000011783#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift 81784#define SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift)1785 1786/*define for number_type field*/1787#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset 171788#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask 0x000000071789#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift 91790#define SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift)1791 1792/*define for surface_type field*/1793#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset 171794#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask 0x000000031795#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift 121796#define SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift)1797 1798/*define for max_comp_block_size field*/1799#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset 171800#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask 0x000000031801#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift 241802#define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift)1803 1804/*define for max_uncomp_block_size field*/1805#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset 171806#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask 0x000000031807#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift 261808#define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift)1809 1810/*define for write_compress_enable field*/1811#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset 171812#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask 0x000000011813#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift 281814#define SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift)1815 1816/*define for meta_tmz field*/1817#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset 171818#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask 0x000000011819#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift 291820#define SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift)1821 1822 1823/*1824** Definitions for SDMA_PKT_COPY_T2T_BC packet1825*/1826 1827/*define for HEADER word*/1828/*define for op field*/1829#define SDMA_PKT_COPY_T2T_BC_HEADER_op_offset 01830#define SDMA_PKT_COPY_T2T_BC_HEADER_op_mask 0x000000FF1831#define SDMA_PKT_COPY_T2T_BC_HEADER_op_shift 01832#define SDMA_PKT_COPY_T2T_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_op_shift)1833 1834/*define for sub_op field*/1835#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset 01836#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask 0x000000FF1837#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift 81838#define SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift)1839 1840/*define for SRC_ADDR_LO word*/1841/*define for src_addr_31_0 field*/1842#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset 11843#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF1844#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift 01845#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift)1846 1847/*define for SRC_ADDR_HI word*/1848/*define for src_addr_63_32 field*/1849#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset 21850#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF1851#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift 01852#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift)1853 1854/*define for DW_3 word*/1855/*define for src_x field*/1856#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset 31857#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask 0x00003FFF1858#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift 01859#define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift)1860 1861/*define for src_y field*/1862#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset 31863#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask 0x00003FFF1864#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift 161865#define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift)1866 1867/*define for DW_4 word*/1868/*define for src_z field*/1869#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset 41870#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask 0x000007FF1871#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift 01872#define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift)1873 1874/*define for src_width field*/1875#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset 41876#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask 0x00003FFF1877#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift 161878#define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift)1879 1880/*define for DW_5 word*/1881/*define for src_height field*/1882#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset 51883#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask 0x00003FFF1884#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift 01885#define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift)1886 1887/*define for src_depth field*/1888#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset 51889#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask 0x000007FF1890#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift 161891#define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift)1892 1893/*define for DW_6 word*/1894/*define for src_element_size field*/1895#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset 61896#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask 0x000000071897#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift 01898#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift)1899 1900/*define for src_array_mode field*/1901#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset 61902#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask 0x0000000F1903#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift 31904#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift)1905 1906/*define for src_mit_mode field*/1907#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset 61908#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask 0x000000071909#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift 81910#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift)1911 1912/*define for src_tilesplit_size field*/1913#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset 61914#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask 0x000000071915#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift 111916#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift)1917 1918/*define for src_bank_w field*/1919#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset 61920#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask 0x000000031921#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift 151922#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift)1923 1924/*define for src_bank_h field*/1925#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset 61926#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask 0x000000031927#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift 181928#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift)1929 1930/*define for src_num_bank field*/1931#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset 61932#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask 0x000000031933#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift 211934#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift)1935 1936/*define for src_mat_aspt field*/1937#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset 61938#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask 0x000000031939#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift 241940#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift)1941 1942/*define for src_pipe_config field*/1943#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset 61944#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask 0x0000001F1945#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift 261946#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift)1947 1948/*define for DST_ADDR_LO word*/1949/*define for dst_addr_31_0 field*/1950#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset 71951#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF1952#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift 01953#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift)1954 1955/*define for DST_ADDR_HI word*/1956/*define for dst_addr_63_32 field*/1957#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset 81958#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF1959#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift 01960#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift)1961 1962/*define for DW_9 word*/1963/*define for dst_x field*/1964#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset 91965#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask 0x00003FFF1966#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift 01967#define SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift)1968 1969/*define for dst_y field*/1970#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset 91971#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask 0x00003FFF1972#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift 161973#define SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift)1974 1975/*define for DW_10 word*/1976/*define for dst_z field*/1977#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset 101978#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask 0x000007FF1979#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift 01980#define SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift)1981 1982/*define for dst_width field*/1983#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset 101984#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask 0x00003FFF1985#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift 161986#define SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift)1987 1988/*define for DW_11 word*/1989/*define for dst_height field*/1990#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset 111991#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask 0x00003FFF1992#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift 01993#define SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift)1994 1995/*define for dst_depth field*/1996#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset 111997#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask 0x00000FFF1998#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift 161999#define SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift)2000 2001/*define for DW_12 word*/2002/*define for dst_element_size field*/2003#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset 122004#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask 0x000000072005#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift 02006#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift)2007 2008/*define for dst_array_mode field*/2009#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset 122010#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask 0x0000000F2011#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift 32012#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift)2013 2014/*define for dst_mit_mode field*/2015#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset 122016#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask 0x000000072017#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift 82018#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift)2019 2020/*define for dst_tilesplit_size field*/2021#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset 122022#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask 0x000000072023#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift 112024#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift)2025 2026/*define for dst_bank_w field*/2027#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset 122028#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask 0x000000032029#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift 152030#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift)2031 2032/*define for dst_bank_h field*/2033#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset 122034#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask 0x000000032035#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift 182036#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift)2037 2038/*define for dst_num_bank field*/2039#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset 122040#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask 0x000000032041#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift 212042#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift)2043 2044/*define for dst_mat_aspt field*/2045#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset 122046#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask 0x000000032047#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift 242048#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift)2049 2050/*define for dst_pipe_config field*/2051#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset 122052#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask 0x0000001F2053#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift 262054#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift)2055 2056/*define for DW_13 word*/2057/*define for rect_x field*/2058#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset 132059#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask 0x00003FFF2060#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift 02061#define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift)2062 2063/*define for rect_y field*/2064#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset 132065#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask 0x00003FFF2066#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift 162067#define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift)2068 2069/*define for DW_14 word*/2070/*define for rect_z field*/2071#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset 142072#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask 0x000007FF2073#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift 02074#define SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift)2075 2076/*define for dst_sw field*/2077#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset 142078#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask 0x000000032079#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift 162080#define SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift)2081 2082/*define for src_sw field*/2083#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset 142084#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask 0x000000032085#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift 242086#define SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift)2087 2088 2089/*2090** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet2091*/2092 2093/*define for HEADER word*/2094/*define for op field*/2095#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 02096#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF2097#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 02098#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift)2099 2100/*define for sub_op field*/2101#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 02102#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF2103#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 82104#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift)2105 2106/*define for tmz field*/2107#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 02108#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x000000012109#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 182110#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift)2111 2112/*define for dcc field*/2113#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset 02114#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask 0x000000012115#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift 192116#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift)2117 2118/*define for detile field*/2119#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 02120#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x000000012121#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 312122#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift)2123 2124/*define for TILED_ADDR_LO word*/2125/*define for tiled_addr_31_0 field*/2126#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 12127#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF2128#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 02129#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift)2130 2131/*define for TILED_ADDR_HI word*/2132/*define for tiled_addr_63_32 field*/2133#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 22134#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF2135#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 02136#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift)2137 2138/*define for DW_3 word*/2139/*define for tiled_x field*/2140#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 32141#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF2142#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 02143#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift)2144 2145/*define for tiled_y field*/2146#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 32147#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF2148#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 162149#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift)2150 2151/*define for DW_4 word*/2152/*define for tiled_z field*/2153#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 42154#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x00001FFF2155#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 02156#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift)2157 2158/*define for width field*/2159#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 42160#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF2161#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 162162#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift)2163 2164/*define for DW_5 word*/2165/*define for height field*/2166#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 52167#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF2168#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 02169#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift)2170 2171/*define for depth field*/2172#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 52173#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x00001FFF2174#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 162175#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift)2176 2177/*define for DW_6 word*/2178/*define for element_size field*/2179#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 62180#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x000000072181#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 02182#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift)2183 2184/*define for swizzle_mode field*/2185#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 62186#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F2187#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 32188#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift)2189 2190/*define for dimension field*/2191#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 62192#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x000000032193#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 92194#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift)2195 2196/*define for mip_max field*/2197#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset 62198#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask 0x0000000F2199#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift 162200#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift)2201 2202/*define for mip_id field*/2203#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset 62204#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask 0x0000000F2205#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift 202206#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift)2207 2208/*define for LINEAR_ADDR_LO word*/2209/*define for linear_addr_31_0 field*/2210#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 72211#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF2212#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 02213#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift)2214 2215/*define for LINEAR_ADDR_HI word*/2216/*define for linear_addr_63_32 field*/2217#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 82218#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF2219#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 02220#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift)2221 2222/*define for DW_9 word*/2223/*define for linear_x field*/2224#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 92225#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF2226#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 02227#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift)2228 2229/*define for linear_y field*/2230#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 92231#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF2232#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 162233#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift)2234 2235/*define for DW_10 word*/2236/*define for linear_z field*/2237#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 102238#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x00001FFF2239#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 02240#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift)2241 2242/*define for linear_pitch field*/2243#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 102244#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF2245#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 162246#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift)2247 2248/*define for DW_11 word*/2249/*define for linear_slice_pitch field*/2250#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 112251#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF2252#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 02253#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift)2254 2255/*define for DW_12 word*/2256/*define for rect_x field*/2257#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 122258#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF2259#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 02260#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift)2261 2262/*define for rect_y field*/2263#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 122264#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF2265#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 162266#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift)2267 2268/*define for DW_13 word*/2269/*define for rect_z field*/2270#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 132271#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x00001FFF2272#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 02273#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift)2274 2275/*define for linear_sw field*/2276#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 132277#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x000000032278#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 162279#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift)2280 2281/*define for tile_sw field*/2282#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 132283#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x000000032284#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 242285#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift)2286 2287/*define for META_ADDR_LO word*/2288/*define for meta_addr_31_0 field*/2289#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset 142290#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF2291#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift 02292#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift)2293 2294/*define for META_ADDR_HI word*/2295/*define for meta_addr_63_32 field*/2296#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset 152297#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF2298#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift 02299#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift)2300 2301/*define for META_CONFIG word*/2302/*define for data_format field*/2303#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset 162304#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask 0x0000007F2305#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift 02306#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift)2307 2308/*define for color_transform_disable field*/2309#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset 162310#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask 0x000000012311#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift 72312#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift)2313 2314/*define for alpha_is_on_msb field*/2315#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset 162316#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask 0x000000012317#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift 82318#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift)2319 2320/*define for number_type field*/2321#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset 162322#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask 0x000000072323#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift 92324#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift)2325 2326/*define for surface_type field*/2327#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset 162328#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask 0x000000032329#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift 122330#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift)2331 2332/*define for max_comp_block_size field*/2333#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset 162334#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask 0x000000032335#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift 242336#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift)2337 2338/*define for max_uncomp_block_size field*/2339#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset 162340#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask 0x000000032341#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift 262342#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift)2343 2344/*define for write_compress_enable field*/2345#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset 162346#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask 0x000000012347#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift 282348#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift)2349 2350/*define for meta_tmz field*/2351#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset 162352#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask 0x000000012353#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift 292354#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift)2355 2356 2357/*2358** Definitions for SDMA_PKT_COPY_TILED_SUBWIN_BC packet2359*/2360 2361/*define for HEADER word*/2362/*define for op field*/2363#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset 02364#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask 0x000000FF2365#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift 02366#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift)2367 2368/*define for sub_op field*/2369#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset 02370#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF2371#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift 82372#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift)2373 2374/*define for detile field*/2375#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset 02376#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask 0x000000012377#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift 312378#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift)2379 2380/*define for TILED_ADDR_LO word*/2381/*define for tiled_addr_31_0 field*/2382#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 12383#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF2384#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 02385#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift)2386 2387/*define for TILED_ADDR_HI word*/2388/*define for tiled_addr_63_32 field*/2389#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 22390#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF2391#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 02392#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift)2393 2394/*define for DW_3 word*/2395/*define for tiled_x field*/2396#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset 32397#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask 0x00003FFF2398#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift 02399#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift)2400 2401/*define for tiled_y field*/2402#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset 32403#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask 0x00003FFF2404#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift 162405#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift)2406 2407/*define for DW_4 word*/2408/*define for tiled_z field*/2409#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset 42410#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask 0x000007FF2411#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift 02412#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift)2413 2414/*define for width field*/2415#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset 42416#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask 0x00003FFF2417#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift 162418#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift)2419 2420/*define for DW_5 word*/2421/*define for height field*/2422#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset 52423#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask 0x00003FFF2424#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift 02425#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift)2426 2427/*define for depth field*/2428#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset 52429#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask 0x000007FF2430#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift 162431#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift)2432 2433/*define for DW_6 word*/2434/*define for element_size field*/2435#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset 62436#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask 0x000000072437#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift 02438#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift)2439 2440/*define for array_mode field*/2441#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset 62442#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask 0x0000000F2443#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift 32444#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift)2445 2446/*define for mit_mode field*/2447#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset 62448#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask 0x000000072449#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift 82450#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift)2451 2452/*define for tilesplit_size field*/2453#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset 62454#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask 0x000000072455#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift 112456#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift)2457 2458/*define for bank_w field*/2459#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset 62460#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask 0x000000032461#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift 152462#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift)2463 2464/*define for bank_h field*/2465#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset 62466#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask 0x000000032467#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift 182468#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift)2469 2470/*define for num_bank field*/2471#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset 62472#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask 0x000000032473#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift 212474#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift)2475 2476/*define for mat_aspt field*/2477#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset 62478#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask 0x000000032479#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift 242480#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x) ((x & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift)2481 2482/*define for pipe_config field*/2483#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset 62484#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask 0x0000001F2485#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift 262486#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift)2487 2488/*define for LINEAR_ADDR_LO word*/2489/*define for linear_addr_31_0 field*/2490#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 72491#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF2492#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 02493#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift)2494 2495/*define for LINEAR_ADDR_HI word*/2496/*define for linear_addr_63_32 field*/2497#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 82498#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF2499#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 02500#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift)2501 2502/*define for DW_9 word*/2503/*define for linear_x field*/2504#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset 92505#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask 0x00003FFF2506#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift 02507#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift)2508 2509/*define for linear_y field*/2510#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset 92511#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask 0x00003FFF2512#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift 162513#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift)2514 2515/*define for DW_10 word*/2516/*define for linear_z field*/2517#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset 102518#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask 0x000007FF2519#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift 02520#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift)2521 2522/*define for linear_pitch field*/2523#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset 102524#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask 0x00003FFF2525#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift 162526#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift)2527 2528/*define for DW_11 word*/2529/*define for linear_slice_pitch field*/2530#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset 112531#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask 0x0FFFFFFF2532#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift 02533#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift)2534 2535/*define for DW_12 word*/2536/*define for rect_x field*/2537#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset 122538#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask 0x00003FFF2539#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift 02540#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift)2541 2542/*define for rect_y field*/2543#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset 122544#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask 0x00003FFF2545#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift 162546#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift)2547 2548/*define for DW_13 word*/2549/*define for rect_z field*/2550#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset 132551#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask 0x000007FF2552#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift 02553#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift)2554 2555/*define for linear_sw field*/2556#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset 132557#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask 0x000000032558#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift 162559#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift)2560 2561/*define for tile_sw field*/2562#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset 132563#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask 0x000000032564#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift 242565#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift)2566 2567 2568/*2569** Definitions for SDMA_PKT_COPY_STRUCT packet2570*/2571 2572/*define for HEADER word*/2573/*define for op field*/2574#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 02575#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF2576#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 02577#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift)2578 2579/*define for sub_op field*/2580#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 02581#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF2582#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 82583#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift)2584 2585/*define for tmz field*/2586#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 02587#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x000000012588#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 182589#define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift)2590 2591/*define for detile field*/2592#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 02593#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x000000012594#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 312595#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift)2596 2597/*define for SB_ADDR_LO word*/2598/*define for sb_addr_31_0 field*/2599#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 12600#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF2601#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 02602#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift)2603 2604/*define for SB_ADDR_HI word*/2605/*define for sb_addr_63_32 field*/2606#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 22607#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF2608#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 02609#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift)2610 2611/*define for START_INDEX word*/2612/*define for start_index field*/2613#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 32614#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF2615#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 02616#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift)2617 2618/*define for COUNT word*/2619/*define for count field*/2620#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 42621#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF2622#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 02623#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift)2624 2625/*define for DW_5 word*/2626/*define for stride field*/2627#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 52628#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF2629#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 02630#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift)2631 2632/*define for linear_sw field*/2633#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 52634#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x000000032635#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 162636#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift)2637 2638/*define for struct_sw field*/2639#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 52640#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x000000032641#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 242642#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift)2643 2644/*define for LINEAR_ADDR_LO word*/2645/*define for linear_addr_31_0 field*/2646#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 62647#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF2648#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 02649#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift)2650 2651/*define for LINEAR_ADDR_HI word*/2652/*define for linear_addr_63_32 field*/2653#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 72654#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF2655#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 02656#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift)2657 2658 2659/*2660** Definitions for SDMA_PKT_WRITE_UNTILED packet2661*/2662 2663/*define for HEADER word*/2664/*define for op field*/2665#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 02666#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF2667#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 02668#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift)2669 2670/*define for sub_op field*/2671#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 02672#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF2673#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 82674#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift)2675 2676/*define for encrypt field*/2677#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 02678#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x000000012679#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 162680#define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift)2681 2682/*define for tmz field*/2683#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 02684#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x000000012685#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 182686#define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift)2687 2688/*define for DST_ADDR_LO word*/2689/*define for dst_addr_31_0 field*/2690#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 12691#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF2692#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 02693#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift)2694 2695/*define for DST_ADDR_HI word*/2696/*define for dst_addr_63_32 field*/2697#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 22698#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF2699#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 02700#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift)2701 2702/*define for DW_3 word*/2703/*define for count field*/2704#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 32705#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF2706#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 02707#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift)2708 2709/*define for sw field*/2710#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 32711#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x000000032712#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 242713#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift)2714 2715/*define for DATA0 word*/2716/*define for data0 field*/2717#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 42718#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF2719#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 02720#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift)2721 2722 2723/*2724** Definitions for SDMA_PKT_WRITE_TILED packet2725*/2726 2727/*define for HEADER word*/2728/*define for op field*/2729#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 02730#define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF2731#define SDMA_PKT_WRITE_TILED_HEADER_op_shift 02732#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift)2733 2734/*define for sub_op field*/2735#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 02736#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF2737#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 82738#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift)2739 2740/*define for encrypt field*/2741#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 02742#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x000000012743#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 162744#define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift)2745 2746/*define for tmz field*/2747#define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 02748#define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x000000012749#define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 182750#define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift)2751 2752/*define for DST_ADDR_LO word*/2753/*define for dst_addr_31_0 field*/2754#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 12755#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF2756#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 02757#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift)2758 2759/*define for DST_ADDR_HI word*/2760/*define for dst_addr_63_32 field*/2761#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 22762#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF2763#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 02764#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift)2765 2766/*define for DW_3 word*/2767/*define for width field*/2768#define SDMA_PKT_WRITE_TILED_DW_3_width_offset 32769#define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF2770#define SDMA_PKT_WRITE_TILED_DW_3_width_shift 02771#define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift)2772 2773/*define for DW_4 word*/2774/*define for height field*/2775#define SDMA_PKT_WRITE_TILED_DW_4_height_offset 42776#define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF2777#define SDMA_PKT_WRITE_TILED_DW_4_height_shift 02778#define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift)2779 2780/*define for depth field*/2781#define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 42782#define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x00001FFF2783#define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 162784#define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift)2785 2786/*define for DW_5 word*/2787/*define for element_size field*/2788#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 52789#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x000000072790#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 02791#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift)2792 2793/*define for swizzle_mode field*/2794#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 52795#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F2796#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 32797#define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift)2798 2799/*define for dimension field*/2800#define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 52801#define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x000000032802#define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 92803#define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift)2804 2805/*define for mip_max field*/2806#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset 52807#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask 0x0000000F2808#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift 162809#define SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask) << SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift)2810 2811/*define for DW_6 word*/2812/*define for x field*/2813#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 62814#define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF2815#define SDMA_PKT_WRITE_TILED_DW_6_x_shift 02816#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift)2817 2818/*define for y field*/2819#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 62820#define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF2821#define SDMA_PKT_WRITE_TILED_DW_6_y_shift 162822#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift)2823 2824/*define for DW_7 word*/2825/*define for z field*/2826#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 72827#define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00001FFF2828#define SDMA_PKT_WRITE_TILED_DW_7_z_shift 02829#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift)2830 2831/*define for sw field*/2832#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 72833#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x000000032834#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 242835#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift)2836 2837/*define for COUNT word*/2838/*define for count field*/2839#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 82840#define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF2841#define SDMA_PKT_WRITE_TILED_COUNT_count_shift 02842#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift)2843 2844/*define for DATA0 word*/2845/*define for data0 field*/2846#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 92847#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF2848#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 02849#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift)2850 2851 2852/*2853** Definitions for SDMA_PKT_WRITE_TILED_BC packet2854*/2855 2856/*define for HEADER word*/2857/*define for op field*/2858#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset 02859#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask 0x000000FF2860#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift 02861#define SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift)2862 2863/*define for sub_op field*/2864#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset 02865#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask 0x000000FF2866#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift 82867#define SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift)2868 2869/*define for DST_ADDR_LO word*/2870/*define for dst_addr_31_0 field*/2871#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset 12872#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF2873#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift 02874#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift)2875 2876/*define for DST_ADDR_HI word*/2877/*define for dst_addr_63_32 field*/2878#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset 22879#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF2880#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift 02881#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift)2882 2883/*define for DW_3 word*/2884/*define for width field*/2885#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset 32886#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask 0x00003FFF2887#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift 02888#define SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift)2889 2890/*define for DW_4 word*/2891/*define for height field*/2892#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset 42893#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask 0x00003FFF2894#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift 02895#define SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift)2896 2897/*define for depth field*/2898#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset 42899#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask 0x000007FF2900#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift 162901#define SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift)2902 2903/*define for DW_5 word*/2904/*define for element_size field*/2905#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset 52906#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask 0x000000072907#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift 02908#define SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift)2909 2910/*define for array_mode field*/2911#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset 52912#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask 0x0000000F2913#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift 32914#define SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift)2915 2916/*define for mit_mode field*/2917#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset 52918#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask 0x000000072919#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift 82920#define SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift)2921 2922/*define for tilesplit_size field*/2923#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset 52924#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask 0x000000072925#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift 112926#define SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift)2927 2928/*define for bank_w field*/2929#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset 52930#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask 0x000000032931#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift 152932#define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift)2933 2934/*define for bank_h field*/2935#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset 52936#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask 0x000000032937#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift 182938#define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift)2939 2940/*define for num_bank field*/2941#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset 52942#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask 0x000000032943#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift 212944#define SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift)2945 2946/*define for mat_aspt field*/2947#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset 52948#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask 0x000000032949#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift 242950#define SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift)2951 2952/*define for pipe_config field*/2953#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset 52954#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask 0x0000001F2955#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift 262956#define SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift)2957 2958/*define for DW_6 word*/2959/*define for x field*/2960#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset 62961#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask 0x00003FFF2962#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift 02963#define SDMA_PKT_WRITE_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift)2964 2965/*define for y field*/2966#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset 62967#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask 0x00003FFF2968#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift 162969#define SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift)2970 2971/*define for DW_7 word*/2972/*define for z field*/2973#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset 72974#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask 0x000007FF2975#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift 02976#define SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift)2977 2978/*define for sw field*/2979#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset 72980#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask 0x000000032981#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift 242982#define SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift)2983 2984/*define for COUNT word*/2985/*define for count field*/2986#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset 82987#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask 0x000FFFFF2988#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift 22989#define SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift)2990 2991/*define for DATA0 word*/2992/*define for data0 field*/2993#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset 92994#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask 0xFFFFFFFF2995#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift 02996#define SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift)2997 2998 2999/*3000** Definitions for SDMA_PKT_PTEPDE_COPY packet3001*/3002 3003/*define for HEADER word*/3004/*define for op field*/3005#define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 03006#define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF3007#define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 03008#define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift)3009 3010/*define for sub_op field*/3011#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 03012#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF3013#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 83014#define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift)3015 3016/*define for tmz field*/3017#define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset 03018#define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask 0x000000013019#define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift 183020#define SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift)3021 3022/*define for ptepde_op field*/3023#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 03024#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x000000013025#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 313026#define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift)3027 3028/*define for SRC_ADDR_LO word*/3029/*define for src_addr_31_0 field*/3030#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 13031#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF3032#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 03033#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift)3034 3035/*define for SRC_ADDR_HI word*/3036/*define for src_addr_63_32 field*/3037#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 23038#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF3039#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 03040#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift)3041 3042/*define for DST_ADDR_LO word*/3043/*define for dst_addr_31_0 field*/3044#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 33045#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF3046#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 03047#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift)3048 3049/*define for DST_ADDR_HI word*/3050/*define for dst_addr_63_32 field*/3051#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 43052#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF3053#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 03054#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift)3055 3056/*define for MASK_DW0 word*/3057/*define for mask_dw0 field*/3058#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 53059#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF3060#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 03061#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift)3062 3063/*define for MASK_DW1 word*/3064/*define for mask_dw1 field*/3065#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 63066#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF3067#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 03068#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift)3069 3070/*define for COUNT word*/3071/*define for count field*/3072#define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 73073#define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF3074#define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 03075#define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift)3076 3077 3078/*3079** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet3080*/3081 3082/*define for HEADER word*/3083/*define for op field*/3084#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 03085#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF3086#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 03087#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift)3088 3089/*define for sub_op field*/3090#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 03091#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF3092#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 83093#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift)3094 3095/*define for pte_size field*/3096#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 03097#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x000000033098#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 283099#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift)3100 3101/*define for direction field*/3102#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 03103#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x000000013104#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 303105#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift)3106 3107/*define for ptepde_op field*/3108#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 03109#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x000000013110#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 313111#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift)3112 3113/*define for SRC_ADDR_LO word*/3114/*define for src_addr_31_0 field*/3115#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 13116#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF3117#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 03118#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift)3119 3120/*define for SRC_ADDR_HI word*/3121/*define for src_addr_63_32 field*/3122#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 23123#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF3124#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 03125#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift)3126 3127/*define for DST_ADDR_LO word*/3128/*define for dst_addr_31_0 field*/3129#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 33130#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF3131#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 03132#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift)3133 3134/*define for DST_ADDR_HI word*/3135/*define for dst_addr_63_32 field*/3136#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 43137#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF3138#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 03139#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift)3140 3141/*define for MASK_BIT_FOR_DW word*/3142/*define for mask_first_xfer field*/3143#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 53144#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF3145#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 03146#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift)3147 3148/*define for mask_last_xfer field*/3149#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 53150#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF3151#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 83152#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift)3153 3154/*define for COUNT_IN_32B_XFER word*/3155/*define for count field*/3156#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 63157#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF3158#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 03159#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift)3160 3161 3162/*3163** Definitions for SDMA_PKT_PTEPDE_RMW packet3164*/3165 3166/*define for HEADER word*/3167/*define for op field*/3168#define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 03169#define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF3170#define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 03171#define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift)3172 3173/*define for sub_op field*/3174#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 03175#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF3176#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 83177#define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift)3178 3179/*define for mtype field*/3180#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset 03181#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask 0x000000073182#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift 163183#define SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift)3184 3185/*define for gcc field*/3186#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 03187#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x000000013188#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 193189#define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift)3190 3191/*define for sys field*/3192#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 03193#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x000000013194#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 203195#define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift)3196 3197/*define for snp field*/3198#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 03199#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x000000013200#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 223201#define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift)3202 3203/*define for gpa field*/3204#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 03205#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x000000013206#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 233207#define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift)3208 3209/*define for l2_policy field*/3210#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset 03211#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask 0x000000033212#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift 243213#define SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift)3214 3215/*define for ADDR_LO word*/3216/*define for addr_31_0 field*/3217#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 13218#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF3219#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 03220#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift)3221 3222/*define for ADDR_HI word*/3223/*define for addr_63_32 field*/3224#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 23225#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF3226#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 03227#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift)3228 3229/*define for MASK_LO word*/3230/*define for mask_31_0 field*/3231#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 33232#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF3233#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 03234#define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift)3235 3236/*define for MASK_HI word*/3237/*define for mask_63_32 field*/3238#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 43239#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF3240#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 03241#define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift)3242 3243/*define for VALUE_LO word*/3244/*define for value_31_0 field*/3245#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 53246#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF3247#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 03248#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift)3249 3250/*define for VALUE_HI word*/3251/*define for value_63_32 field*/3252#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 63253#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF3254#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 03255#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift)3256 3257 3258/*3259** Definitions for SDMA_PKT_WRITE_INCR packet3260*/3261 3262/*define for HEADER word*/3263/*define for op field*/3264#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 03265#define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF3266#define SDMA_PKT_WRITE_INCR_HEADER_op_shift 03267#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift)3268 3269/*define for sub_op field*/3270#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 03271#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF3272#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 83273#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift)3274 3275/*define for DST_ADDR_LO word*/3276/*define for dst_addr_31_0 field*/3277#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 13278#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF3279#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 03280#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift)3281 3282/*define for DST_ADDR_HI word*/3283/*define for dst_addr_63_32 field*/3284#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 23285#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF3286#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 03287#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift)3288 3289/*define for MASK_DW0 word*/3290/*define for mask_dw0 field*/3291#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 33292#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF3293#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 03294#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift)3295 3296/*define for MASK_DW1 word*/3297/*define for mask_dw1 field*/3298#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 43299#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF3300#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 03301#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift)3302 3303/*define for INIT_DW0 word*/3304/*define for init_dw0 field*/3305#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 53306#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF3307#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 03308#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift)3309 3310/*define for INIT_DW1 word*/3311/*define for init_dw1 field*/3312#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 63313#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF3314#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 03315#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift)3316 3317/*define for INCR_DW0 word*/3318/*define for incr_dw0 field*/3319#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 73320#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF3321#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 03322#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift)3323 3324/*define for INCR_DW1 word*/3325/*define for incr_dw1 field*/3326#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 83327#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF3328#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 03329#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift)3330 3331/*define for COUNT word*/3332/*define for count field*/3333#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 93334#define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF3335#define SDMA_PKT_WRITE_INCR_COUNT_count_shift 03336#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift)3337 3338 3339/*3340** Definitions for SDMA_PKT_INDIRECT packet3341*/3342 3343/*define for HEADER word*/3344/*define for op field*/3345#define SDMA_PKT_INDIRECT_HEADER_op_offset 03346#define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF3347#define SDMA_PKT_INDIRECT_HEADER_op_shift 03348#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift)3349 3350/*define for sub_op field*/3351#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 03352#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF3353#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 83354#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift)3355 3356/*define for vmid field*/3357#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 03358#define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F3359#define SDMA_PKT_INDIRECT_HEADER_vmid_shift 163360#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift)3361 3362/*define for priv field*/3363#define SDMA_PKT_INDIRECT_HEADER_priv_offset 03364#define SDMA_PKT_INDIRECT_HEADER_priv_mask 0x000000013365#define SDMA_PKT_INDIRECT_HEADER_priv_shift 313366#define SDMA_PKT_INDIRECT_HEADER_PRIV(x) (((x) & SDMA_PKT_INDIRECT_HEADER_priv_mask) << SDMA_PKT_INDIRECT_HEADER_priv_shift)3367 3368/*define for BASE_LO word*/3369/*define for ib_base_31_0 field*/3370#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 13371#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF3372#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 03373#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift)3374 3375/*define for BASE_HI word*/3376/*define for ib_base_63_32 field*/3377#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 23378#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF3379#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 03380#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift)3381 3382/*define for IB_SIZE word*/3383/*define for ib_size field*/3384#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 33385#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF3386#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 03387#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift)3388 3389/*define for CSA_ADDR_LO word*/3390/*define for csa_addr_31_0 field*/3391#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 43392#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF3393#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 03394#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift)3395 3396/*define for CSA_ADDR_HI word*/3397/*define for csa_addr_63_32 field*/3398#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 53399#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF3400#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 03401#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift)3402 3403 3404/*3405** Definitions for SDMA_PKT_SEMAPHORE packet3406*/3407 3408/*define for HEADER word*/3409/*define for op field*/3410#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 03411#define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF3412#define SDMA_PKT_SEMAPHORE_HEADER_op_shift 03413#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift)3414 3415/*define for sub_op field*/3416#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 03417#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF3418#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 83419#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift)3420 3421/*define for write_one field*/3422#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 03423#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x000000013424#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 293425#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift)3426 3427/*define for signal field*/3428#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 03429#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x000000013430#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 303431#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift)3432 3433/*define for mailbox field*/3434#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 03435#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x000000013436#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 313437#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift)3438 3439/*define for ADDR_LO word*/3440/*define for addr_31_0 field*/3441#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 13442#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF3443#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 03444#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift)3445 3446/*define for ADDR_HI word*/3447/*define for addr_63_32 field*/3448#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 23449#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF3450#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 03451#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift)3452 3453 3454/*3455** Definitions for SDMA_PKT_FENCE packet3456*/3457 3458/*define for HEADER word*/3459/*define for op field*/3460#define SDMA_PKT_FENCE_HEADER_op_offset 03461#define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF3462#define SDMA_PKT_FENCE_HEADER_op_shift 03463#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift)3464 3465/*define for sub_op field*/3466#define SDMA_PKT_FENCE_HEADER_sub_op_offset 03467#define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF3468#define SDMA_PKT_FENCE_HEADER_sub_op_shift 83469#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift)3470 3471/*define for mtype field*/3472#define SDMA_PKT_FENCE_HEADER_mtype_offset 03473#define SDMA_PKT_FENCE_HEADER_mtype_mask 0x000000073474#define SDMA_PKT_FENCE_HEADER_mtype_shift 163475#define SDMA_PKT_FENCE_HEADER_MTYPE(x) (((x) & SDMA_PKT_FENCE_HEADER_mtype_mask) << SDMA_PKT_FENCE_HEADER_mtype_shift)3476 3477/*define for gcc field*/3478#define SDMA_PKT_FENCE_HEADER_gcc_offset 03479#define SDMA_PKT_FENCE_HEADER_gcc_mask 0x000000013480#define SDMA_PKT_FENCE_HEADER_gcc_shift 193481#define SDMA_PKT_FENCE_HEADER_GCC(x) (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEADER_gcc_shift)3482 3483/*define for sys field*/3484#define SDMA_PKT_FENCE_HEADER_sys_offset 03485#define SDMA_PKT_FENCE_HEADER_sys_mask 0x000000013486#define SDMA_PKT_FENCE_HEADER_sys_shift 203487#define SDMA_PKT_FENCE_HEADER_SYS(x) (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEADER_sys_shift)3488 3489/*define for snp field*/3490#define SDMA_PKT_FENCE_HEADER_snp_offset 03491#define SDMA_PKT_FENCE_HEADER_snp_mask 0x000000013492#define SDMA_PKT_FENCE_HEADER_snp_shift 223493#define SDMA_PKT_FENCE_HEADER_SNP(x) (((x) & SDMA_PKT_FENCE_HEADER_snp_mask) << SDMA_PKT_FENCE_HEADER_snp_shift)3494 3495/*define for gpa field*/3496#define SDMA_PKT_FENCE_HEADER_gpa_offset 03497#define SDMA_PKT_FENCE_HEADER_gpa_mask 0x000000013498#define SDMA_PKT_FENCE_HEADER_gpa_shift 233499#define SDMA_PKT_FENCE_HEADER_GPA(x) (((x) & SDMA_PKT_FENCE_HEADER_gpa_mask) << SDMA_PKT_FENCE_HEADER_gpa_shift)3500 3501/*define for l2_policy field*/3502#define SDMA_PKT_FENCE_HEADER_l2_policy_offset 03503#define SDMA_PKT_FENCE_HEADER_l2_policy_mask 0x000000033504#define SDMA_PKT_FENCE_HEADER_l2_policy_shift 243505#define SDMA_PKT_FENCE_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_l2_policy_mask) << SDMA_PKT_FENCE_HEADER_l2_policy_shift)3506 3507/*define for ADDR_LO word*/3508/*define for addr_31_0 field*/3509#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 13510#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF3511#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 03512#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift)3513 3514/*define for ADDR_HI word*/3515/*define for addr_63_32 field*/3516#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 23517#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF3518#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 03519#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift)3520 3521/*define for DATA word*/3522/*define for data field*/3523#define SDMA_PKT_FENCE_DATA_data_offset 33524#define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF3525#define SDMA_PKT_FENCE_DATA_data_shift 03526#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift)3527 3528 3529/*3530** Definitions for SDMA_PKT_SRBM_WRITE packet3531*/3532 3533/*define for HEADER word*/3534/*define for op field*/3535#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 03536#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF3537#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 03538#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift)3539 3540/*define for sub_op field*/3541#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 03542#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF3543#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 83544#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift)3545 3546/*define for byte_en field*/3547#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 03548#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F3549#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 283550#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift)3551 3552/*define for ADDR word*/3553/*define for addr field*/3554#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 13555#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF3556#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 03557#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift)3558 3559/*define for apertureid field*/3560#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset 13561#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask 0x00000FFF3562#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift 203563#define SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask) << SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift)3564 3565/*define for DATA word*/3566/*define for data field*/3567#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 23568#define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF3569#define SDMA_PKT_SRBM_WRITE_DATA_data_shift 03570#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift)3571 3572 3573/*3574** Definitions for SDMA_PKT_PRE_EXE packet3575*/3576 3577/*define for HEADER word*/3578/*define for op field*/3579#define SDMA_PKT_PRE_EXE_HEADER_op_offset 03580#define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF3581#define SDMA_PKT_PRE_EXE_HEADER_op_shift 03582#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift)3583 3584/*define for sub_op field*/3585#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 03586#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF3587#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 83588#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift)3589 3590/*define for dev_sel field*/3591#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 03592#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF3593#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 163594#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift)3595 3596/*define for EXEC_COUNT word*/3597/*define for exec_count field*/3598#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 13599#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF3600#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 03601#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift)3602 3603 3604/*3605** Definitions for SDMA_PKT_COND_EXE packet3606*/3607 3608/*define for HEADER word*/3609/*define for op field*/3610#define SDMA_PKT_COND_EXE_HEADER_op_offset 03611#define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF3612#define SDMA_PKT_COND_EXE_HEADER_op_shift 03613#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift)3614 3615/*define for sub_op field*/3616#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 03617#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF3618#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 83619#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift)3620 3621/*define for ADDR_LO word*/3622/*define for addr_31_0 field*/3623#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 13624#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF3625#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 03626#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift)3627 3628/*define for ADDR_HI word*/3629/*define for addr_63_32 field*/3630#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 23631#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF3632#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 03633#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift)3634 3635/*define for REFERENCE word*/3636/*define for reference field*/3637#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 33638#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF3639#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 03640#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift)3641 3642/*define for EXEC_COUNT word*/3643/*define for exec_count field*/3644#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 43645#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF3646#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 03647#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift)3648 3649 3650/*3651** Definitions for SDMA_PKT_CONSTANT_FILL packet3652*/3653 3654/*define for HEADER word*/3655/*define for op field*/3656#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 03657#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF3658#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 03659#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift)3660 3661/*define for sub_op field*/3662#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 03663#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF3664#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 83665#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift)3666 3667/*define for sw field*/3668#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 03669#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x000000033670#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 163671#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift)3672 3673/*define for fillsize field*/3674#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 03675#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x000000033676#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 303677#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift)3678 3679/*define for DST_ADDR_LO word*/3680/*define for dst_addr_31_0 field*/3681#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 13682#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF3683#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 03684#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift)3685 3686/*define for DST_ADDR_HI word*/3687/*define for dst_addr_63_32 field*/3688#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 23689#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF3690#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 03691#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift)3692 3693/*define for DATA word*/3694/*define for src_data_31_0 field*/3695#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 33696#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF3697#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 03698#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift)3699 3700/*define for COUNT word*/3701/*define for count field*/3702#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 43703#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF3704#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 03705#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift)3706 3707 3708/*3709** Definitions for SDMA_PKT_DATA_FILL_MULTI packet3710*/3711 3712/*define for HEADER word*/3713/*define for op field*/3714#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 03715#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF3716#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 03717#define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift)3718 3719/*define for sub_op field*/3720#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 03721#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF3722#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 83723#define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift)3724 3725/*define for memlog_clr field*/3726#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 03727#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x000000013728#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 313729#define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift)3730 3731/*define for BYTE_STRIDE word*/3732/*define for byte_stride field*/3733#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 13734#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF3735#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 03736#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift)3737 3738/*define for DMA_COUNT word*/3739/*define for dma_count field*/3740#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 23741#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF3742#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 03743#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift)3744 3745/*define for DST_ADDR_LO word*/3746/*define for dst_addr_31_0 field*/3747#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 33748#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF3749#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 03750#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift)3751 3752/*define for DST_ADDR_HI word*/3753/*define for dst_addr_63_32 field*/3754#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 43755#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF3756#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 03757#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift)3758 3759/*define for BYTE_COUNT word*/3760/*define for count field*/3761#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 53762#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF3763#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 03764#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift)3765 3766 3767/*3768** Definitions for SDMA_PKT_POLL_REGMEM packet3769*/3770 3771/*define for HEADER word*/3772/*define for op field*/3773#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 03774#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF3775#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 03776#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift)3777 3778/*define for sub_op field*/3779#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 03780#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF3781#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 83782#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift)3783 3784/*define for hdp_flush field*/3785#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 03786#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x000000013787#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 263788#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift)3789 3790/*define for func field*/3791#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 03792#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x000000073793#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 283794#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift)3795 3796/*define for mem_poll field*/3797#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 03798#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x000000013799#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 313800#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift)3801 3802/*define for ADDR_LO word*/3803/*define for addr_31_0 field*/3804#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 13805#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF3806#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 03807#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift)3808 3809/*define for ADDR_HI word*/3810/*define for addr_63_32 field*/3811#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 23812#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF3813#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 03814#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift)3815 3816/*define for VALUE word*/3817/*define for value field*/3818#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 33819#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF3820#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 03821#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift)3822 3823/*define for MASK word*/3824/*define for mask field*/3825#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 43826#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF3827#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 03828#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift)3829 3830/*define for DW5 word*/3831/*define for interval field*/3832#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 53833#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF3834#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 03835#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift)3836 3837/*define for retry_count field*/3838#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 53839#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF3840#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 163841#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift)3842 3843 3844/*3845** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet3846*/3847 3848/*define for HEADER word*/3849/*define for op field*/3850#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 03851#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF3852#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 03853#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift)3854 3855/*define for sub_op field*/3856#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 03857#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF3858#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 83859#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift)3860 3861/*define for SRC_ADDR word*/3862/*define for addr_31_2 field*/3863#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 13864#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF3865#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 23866#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift)3867 3868/*define for DST_ADDR_LO word*/3869/*define for addr_31_0 field*/3870#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 23871#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF3872#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 03873#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift)3874 3875/*define for DST_ADDR_HI word*/3876/*define for addr_63_32 field*/3877#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 33878#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF3879#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 03880#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift)3881 3882 3883/*3884** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet3885*/3886 3887/*define for HEADER word*/3888/*define for op field*/3889#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 03890#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF3891#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 03892#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift)3893 3894/*define for sub_op field*/3895#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 03896#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF3897#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 83898#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift)3899 3900/*define for ea field*/3901#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 03902#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x000000033903#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 163904#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift)3905 3906/*define for DST_ADDR_LO word*/3907/*define for addr_31_0 field*/3908#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 13909#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF3910#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 03911#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift)3912 3913/*define for DST_ADDR_HI word*/3914/*define for addr_63_32 field*/3915#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 23916#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF3917#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 03918#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift)3919 3920/*define for START_PAGE word*/3921/*define for addr_31_4 field*/3922#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 33923#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF3924#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 43925#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift)3926 3927/*define for PAGE_NUM word*/3928/*define for page_num_31_0 field*/3929#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 43930#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF3931#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 03932#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift)3933 3934 3935/*3936** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet3937*/3938 3939/*define for HEADER word*/3940/*define for op field*/3941#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 03942#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF3943#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 03944#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift)3945 3946/*define for sub_op field*/3947#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 03948#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF3949#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 83950#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift)3951 3952/*define for mode field*/3953#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 03954#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x000000013955#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 313956#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift)3957 3958/*define for PATTERN word*/3959/*define for pattern field*/3960#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 13961#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF3962#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 03963#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift)3964 3965/*define for CMP0_ADDR_START_LO word*/3966/*define for cmp0_start_31_0 field*/3967#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 23968#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF3969#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 03970#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift)3971 3972/*define for CMP0_ADDR_START_HI word*/3973/*define for cmp0_start_63_32 field*/3974#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 33975#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF3976#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 03977#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift)3978 3979/*define for CMP0_ADDR_END_LO word*/3980/*define for cmp1_end_31_0 field*/3981#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset 43982#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF3983#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 03984#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift)3985 3986/*define for CMP0_ADDR_END_HI word*/3987/*define for cmp1_end_63_32 field*/3988#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset 53989#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF3990#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 03991#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift)3992 3993/*define for CMP1_ADDR_START_LO word*/3994/*define for cmp1_start_31_0 field*/3995#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 63996#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF3997#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 03998#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift)3999 4000/*define for CMP1_ADDR_START_HI word*/4001/*define for cmp1_start_63_32 field*/4002#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 74003#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF4004#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 04005#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift)4006 4007/*define for CMP1_ADDR_END_LO word*/4008/*define for cmp1_end_31_0 field*/4009#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 84010#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF4011#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 04012#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift)4013 4014/*define for CMP1_ADDR_END_HI word*/4015/*define for cmp1_end_63_32 field*/4016#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 94017#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF4018#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 04019#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift)4020 4021/*define for REC_ADDR_LO word*/4022/*define for rec_31_0 field*/4023#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 104024#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF4025#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 04026#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift)4027 4028/*define for REC_ADDR_HI word*/4029/*define for rec_63_32 field*/4030#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 114031#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF4032#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 04033#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift)4034 4035/*define for RESERVED word*/4036/*define for reserved field*/4037#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 124038#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF4039#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 04040#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift)4041 4042 4043/*4044** Definitions for SDMA_PKT_ATOMIC packet4045*/4046 4047/*define for HEADER word*/4048/*define for op field*/4049#define SDMA_PKT_ATOMIC_HEADER_op_offset 04050#define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF4051#define SDMA_PKT_ATOMIC_HEADER_op_shift 04052#define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift)4053 4054/*define for loop field*/4055#define SDMA_PKT_ATOMIC_HEADER_loop_offset 04056#define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x000000014057#define SDMA_PKT_ATOMIC_HEADER_loop_shift 164058#define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift)4059 4060/*define for tmz field*/4061#define SDMA_PKT_ATOMIC_HEADER_tmz_offset 04062#define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x000000014063#define SDMA_PKT_ATOMIC_HEADER_tmz_shift 184064#define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift)4065 4066/*define for atomic_op field*/4067#define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 04068#define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F4069#define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 254070#define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift)4071 4072/*define for ADDR_LO word*/4073/*define for addr_31_0 field*/4074#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 14075#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF4076#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 04077#define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift)4078 4079/*define for ADDR_HI word*/4080/*define for addr_63_32 field*/4081#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 24082#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF4083#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 04084#define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift)4085 4086/*define for SRC_DATA_LO word*/4087/*define for src_data_31_0 field*/4088#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 34089#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF4090#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 04091#define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift)4092 4093/*define for SRC_DATA_HI word*/4094/*define for src_data_63_32 field*/4095#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 44096#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF4097#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 04098#define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift)4099 4100/*define for CMP_DATA_LO word*/4101/*define for cmp_data_31_0 field*/4102#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 54103#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF4104#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 04105#define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift)4106 4107/*define for CMP_DATA_HI word*/4108/*define for cmp_data_63_32 field*/4109#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 64110#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF4111#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 04112#define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift)4113 4114/*define for LOOP_INTERVAL word*/4115/*define for loop_interval field*/4116#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 74117#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF4118#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 04119#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift)4120 4121 4122/*4123** Definitions for SDMA_PKT_TIMESTAMP_SET packet4124*/4125 4126/*define for HEADER word*/4127/*define for op field*/4128#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 04129#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF4130#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 04131#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift)4132 4133/*define for sub_op field*/4134#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 04135#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF4136#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 84137#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift)4138 4139/*define for INIT_DATA_LO word*/4140/*define for init_data_31_0 field*/4141#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 14142#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF4143#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 04144#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift)4145 4146/*define for INIT_DATA_HI word*/4147/*define for init_data_63_32 field*/4148#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 24149#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF4150#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 04151#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift)4152 4153 4154/*4155** Definitions for SDMA_PKT_TIMESTAMP_GET packet4156*/4157 4158/*define for HEADER word*/4159/*define for op field*/4160#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 04161#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF4162#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 04163#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift)4164 4165/*define for sub_op field*/4166#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 04167#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF4168#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 84169#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift)4170 4171/*define for WRITE_ADDR_LO word*/4172/*define for write_addr_31_3 field*/4173#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 14174#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF4175#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 34176#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift)4177 4178/*define for WRITE_ADDR_HI word*/4179/*define for write_addr_63_32 field*/4180#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 24181#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF4182#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 04183#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift)4184 4185 4186/*4187** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet4188*/4189 4190/*define for HEADER word*/4191/*define for op field*/4192#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 04193#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF4194#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 04195#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift)4196 4197/*define for sub_op field*/4198#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 04199#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF4200#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 84201#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift)4202 4203/*define for WRITE_ADDR_LO word*/4204/*define for write_addr_31_3 field*/4205#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 14206#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF4207#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 34208#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift)4209 4210/*define for WRITE_ADDR_HI word*/4211/*define for write_addr_63_32 field*/4212#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 24213#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF4214#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 04215#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift)4216 4217 4218/*4219** Definitions for SDMA_PKT_TRAP packet4220*/4221 4222/*define for HEADER word*/4223/*define for op field*/4224#define SDMA_PKT_TRAP_HEADER_op_offset 04225#define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF4226#define SDMA_PKT_TRAP_HEADER_op_shift 04227#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift)4228 4229/*define for sub_op field*/4230#define SDMA_PKT_TRAP_HEADER_sub_op_offset 04231#define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF4232#define SDMA_PKT_TRAP_HEADER_sub_op_shift 84233#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift)4234 4235/*define for INT_CONTEXT word*/4236/*define for int_context field*/4237#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 14238#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF4239#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 04240#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift)4241 4242 4243/*4244** Definitions for SDMA_PKT_DUMMY_TRAP packet4245*/4246 4247/*define for HEADER word*/4248/*define for op field*/4249#define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 04250#define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF4251#define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 04252#define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift)4253 4254/*define for sub_op field*/4255#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 04256#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF4257#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 84258#define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift)4259 4260/*define for INT_CONTEXT word*/4261/*define for int_context field*/4262#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 14263#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF4264#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 04265#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift)4266 4267 4268/*4269** Definitions for SDMA_PKT_GPUVM_INV packet4270*/4271 4272/*define for HEADER word*/4273/*define for op field*/4274#define SDMA_PKT_GPUVM_INV_HEADER_op_offset 04275#define SDMA_PKT_GPUVM_INV_HEADER_op_mask 0x000000FF4276#define SDMA_PKT_GPUVM_INV_HEADER_op_shift 04277#define SDMA_PKT_GPUVM_INV_HEADER_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_op_shift)4278 4279/*define for sub_op field*/4280#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset 04281#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask 0x000000FF4282#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift 84283#define SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift)4284 4285/*define for PAYLOAD1 word*/4286/*define for per_vmid_inv_req field*/4287#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset 14288#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask 0x0000FFFF4289#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift 04290#define SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift)4291 4292/*define for flush_type field*/4293#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset 14294#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask 0x000000074295#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift 164296#define SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift)4297 4298/*define for l2_ptes field*/4299#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset 14300#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask 0x000000014301#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift 194302#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift)4303 4304/*define for l2_pde0 field*/4305#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset 14306#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask 0x000000014307#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift 204308#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift)4309 4310/*define for l2_pde1 field*/4311#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset 14312#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask 0x000000014313#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift 214314#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift)4315 4316/*define for l2_pde2 field*/4317#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset 14318#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask 0x000000014319#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift 224320#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift)4321 4322/*define for l1_ptes field*/4323#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset 14324#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask 0x000000014325#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift 234326#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift)4327 4328/*define for clr_protection_fault_status_addr field*/4329#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset 14330#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask 0x000000014331#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift 244332#define SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift)4333 4334/*define for log_request field*/4335#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset 14336#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask 0x000000014337#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift 254338#define SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift)4339 4340/*define for four_kilobytes field*/4341#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset 14342#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask 0x000000014343#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift 264344#define SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift)4345 4346/*define for PAYLOAD2 word*/4347/*define for s field*/4348#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset 24349#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask 0x000000014350#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift 04351#define SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift)4352 4353/*define for page_va_42_12 field*/4354#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset 24355#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask 0x7FFFFFFF4356#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift 14357#define SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift)4358 4359/*define for PAYLOAD3 word*/4360/*define for page_va_47_43 field*/4361#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset 34362#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask 0x0000003F4363#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift 04364#define SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift)4365 4366 4367/*4368** Definitions for SDMA_PKT_GCR_REQ packet4369*/4370 4371/*define for HEADER word*/4372/*define for op field*/4373#define SDMA_PKT_GCR_REQ_HEADER_op_offset 04374#define SDMA_PKT_GCR_REQ_HEADER_op_mask 0x000000FF4375#define SDMA_PKT_GCR_REQ_HEADER_op_shift 04376#define SDMA_PKT_GCR_REQ_HEADER_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_op_mask) << SDMA_PKT_GCR_REQ_HEADER_op_shift)4377 4378/*define for sub_op field*/4379#define SDMA_PKT_GCR_REQ_HEADER_sub_op_offset 04380#define SDMA_PKT_GCR_REQ_HEADER_sub_op_mask 0x000000FF4381#define SDMA_PKT_GCR_REQ_HEADER_sub_op_shift 84382#define SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_sub_op_mask) << SDMA_PKT_GCR_REQ_HEADER_sub_op_shift)4383 4384/*define for PAYLOAD1 word*/4385/*define for base_va_31_7 field*/4386#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset 14387#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask 0x01FFFFFF4388#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift 74389#define SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift)4390 4391/*define for PAYLOAD2 word*/4392/*define for base_va_47_32 field*/4393#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset 24394#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask 0x0000FFFF4395#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift 04396#define SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift)4397 4398/*define for gcr_control_15_0 field*/4399#define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset 24400#define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask 0x0000FFFF4401#define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift 164402#define SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift)4403 4404/*define for PAYLOAD3 word*/4405/*define for gcr_control_18_16 field*/4406#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset 34407#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask 0x000000074408#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift 04409#define SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift)4410 4411/*define for limit_va_31_7 field*/4412#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset 34413#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask 0x01FFFFFF4414#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift 74415#define SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift)4416 4417/*define for PAYLOAD4 word*/4418/*define for limit_va_47_32 field*/4419#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset 44420#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask 0x0000FFFF4421#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift 04422#define SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift)4423 4424/*define for vmid field*/4425#define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset 44426#define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask 0x0000000F4427#define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift 244428#define SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift)4429 4430 4431/*4432** Definitions for SDMA_PKT_NOP packet4433*/4434 4435/*define for HEADER word*/4436/*define for op field*/4437#define SDMA_PKT_NOP_HEADER_op_offset 04438#define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF4439#define SDMA_PKT_NOP_HEADER_op_shift 04440#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift)4441 4442/*define for sub_op field*/4443#define SDMA_PKT_NOP_HEADER_sub_op_offset 04444#define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF4445#define SDMA_PKT_NOP_HEADER_sub_op_shift 84446#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift)4447 4448/*define for count field*/4449#define SDMA_PKT_NOP_HEADER_count_offset 04450#define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF4451#define SDMA_PKT_NOP_HEADER_count_shift 164452#define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift)4453 4454/*define for DATA0 word*/4455/*define for data0 field*/4456#define SDMA_PKT_NOP_DATA0_data0_offset 14457#define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF4458#define SDMA_PKT_NOP_DATA0_data0_shift 04459#define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift)4460 4461 4462/*4463** Definitions for SDMA_AQL_PKT_HEADER packet4464*/4465 4466/*define for HEADER word*/4467/*define for format field*/4468#define SDMA_AQL_PKT_HEADER_HEADER_format_offset 04469#define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF4470#define SDMA_AQL_PKT_HEADER_HEADER_format_shift 04471#define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift)4472 4473/*define for barrier field*/4474#define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 04475#define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x000000014476#define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 84477#define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift)4478 4479/*define for acquire_fence_scope field*/4480#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 04481#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x000000034482#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 94483#define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift)4484 4485/*define for release_fence_scope field*/4486#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 04487#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x000000034488#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 114489#define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift)4490 4491/*define for reserved field*/4492#define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 04493#define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x000000074494#define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 134495#define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift)4496 4497/*define for op field*/4498#define SDMA_AQL_PKT_HEADER_HEADER_op_offset 04499#define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F4500#define SDMA_AQL_PKT_HEADER_HEADER_op_shift 164501#define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift)4502 4503/*define for subop field*/4504#define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 04505#define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x000000074506#define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 204507#define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift)4508 4509 4510/*4511** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet4512*/4513 4514/*define for HEADER word*/4515/*define for format field*/4516#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 04517#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF4518#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 04519#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift)4520 4521/*define for barrier field*/4522#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 04523#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x000000014524#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 84525#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift)4526 4527/*define for acquire_fence_scope field*/4528#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 04529#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x000000034530#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 94531#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift)4532 4533/*define for release_fence_scope field*/4534#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 04535#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x000000034536#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 114537#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift)4538 4539/*define for reserved field*/4540#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 04541#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x000000074542#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 134543#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift)4544 4545/*define for op field*/4546#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 04547#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F4548#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 164549#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift)4550 4551/*define for subop field*/4552#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 04553#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x000000074554#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 204555#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift)4556 4557/*define for RESERVED_DW1 word*/4558/*define for reserved_dw1 field*/4559#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 14560#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF4561#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 04562#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift)4563 4564/*define for RETURN_ADDR_LO word*/4565/*define for return_addr_31_0 field*/4566#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 24567#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF4568#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 04569#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift)4570 4571/*define for RETURN_ADDR_HI word*/4572/*define for return_addr_63_32 field*/4573#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 34574#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF4575#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 04576#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift)4577 4578/*define for COUNT word*/4579/*define for count field*/4580#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 44581#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF4582#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 04583#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift)4584 4585/*define for PARAMETER word*/4586/*define for dst_sw field*/4587#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 54588#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x000000034589#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 164590#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift)4591 4592/*define for src_sw field*/4593#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 54594#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x000000034595#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 244596#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift)4597 4598/*define for SRC_ADDR_LO word*/4599/*define for src_addr_31_0 field*/4600#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 64601#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF4602#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 04603#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)4604 4605/*define for SRC_ADDR_HI word*/4606/*define for src_addr_63_32 field*/4607#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 74608#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF4609#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 04610#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)4611 4612/*define for DST_ADDR_LO word*/4613/*define for dst_addr_31_0 field*/4614#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 84615#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF4616#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 04617#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)4618 4619/*define for DST_ADDR_HI word*/4620/*define for dst_addr_63_32 field*/4621#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 94622#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF4623#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 04624#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)4625 4626/*define for RESERVED_DW10 word*/4627/*define for reserved_dw10 field*/4628#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 104629#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF4630#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 04631#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift)4632 4633/*define for RESERVED_DW11 word*/4634/*define for reserved_dw11 field*/4635#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 114636#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF4637#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 04638#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift)4639 4640/*define for RESERVED_DW12 word*/4641/*define for reserved_dw12 field*/4642#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 124643#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF4644#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 04645#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift)4646 4647/*define for RESERVED_DW13 word*/4648/*define for reserved_dw13 field*/4649#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 134650#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF4651#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 04652#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift)4653 4654/*define for COMPLETION_SIGNAL_LO word*/4655/*define for completion_signal_31_0 field*/4656#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 144657#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF4658#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 04659#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift)4660 4661/*define for COMPLETION_SIGNAL_HI word*/4662/*define for completion_signal_63_32 field*/4663#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 154664#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF4665#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 04666#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift)4667 4668 4669/*4670** Definitions for SDMA_AQL_PKT_BARRIER_OR packet4671*/4672 4673/*define for HEADER word*/4674/*define for format field*/4675#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 04676#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF4677#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 04678#define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift)4679 4680/*define for barrier field*/4681#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 04682#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x000000014683#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 84684#define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift)4685 4686/*define for acquire_fence_scope field*/4687#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 04688#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x000000034689#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 94690#define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift)4691 4692/*define for release_fence_scope field*/4693#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 04694#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x000000034695#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 114696#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift)4697 4698/*define for reserved field*/4699#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 04700#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x000000074701#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 134702#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift)4703 4704/*define for op field*/4705#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 04706#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F4707#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 164708#define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift)4709 4710/*define for subop field*/4711#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 04712#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x000000074713#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 204714#define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift)4715 4716/*define for RESERVED_DW1 word*/4717/*define for reserved_dw1 field*/4718#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 14719#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF4720#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 04721#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift)4722 4723/*define for DEPENDENT_ADDR_0_LO word*/4724/*define for dependent_addr_0_31_0 field*/4725#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 24726#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF4727#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 04728#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift)4729 4730/*define for DEPENDENT_ADDR_0_HI word*/4731/*define for dependent_addr_0_63_32 field*/4732#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 34733#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF4734#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 04735#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift)4736 4737/*define for DEPENDENT_ADDR_1_LO word*/4738/*define for dependent_addr_1_31_0 field*/4739#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 44740#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF4741#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 04742#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift)4743 4744/*define for DEPENDENT_ADDR_1_HI word*/4745/*define for dependent_addr_1_63_32 field*/4746#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 54747#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF4748#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 04749#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift)4750 4751/*define for DEPENDENT_ADDR_2_LO word*/4752/*define for dependent_addr_2_31_0 field*/4753#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 64754#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF4755#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 04756#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift)4757 4758/*define for DEPENDENT_ADDR_2_HI word*/4759/*define for dependent_addr_2_63_32 field*/4760#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 74761#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF4762#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 04763#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift)4764 4765/*define for DEPENDENT_ADDR_3_LO word*/4766/*define for dependent_addr_3_31_0 field*/4767#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 84768#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF4769#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 04770#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift)4771 4772/*define for DEPENDENT_ADDR_3_HI word*/4773/*define for dependent_addr_3_63_32 field*/4774#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 94775#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF4776#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 04777#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift)4778 4779/*define for DEPENDENT_ADDR_4_LO word*/4780/*define for dependent_addr_4_31_0 field*/4781#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 104782#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF4783#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 04784#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift)4785 4786/*define for DEPENDENT_ADDR_4_HI word*/4787/*define for dependent_addr_4_63_32 field*/4788#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 114789#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF4790#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 04791#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift)4792 4793/*define for RESERVED_DW12 word*/4794/*define for reserved_dw12 field*/4795#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset 124796#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF4797#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 04798#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift)4799 4800/*define for RESERVED_DW13 word*/4801/*define for reserved_dw13 field*/4802#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 134803#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF4804#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 04805#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift)4806 4807/*define for COMPLETION_SIGNAL_LO word*/4808/*define for completion_signal_31_0 field*/4809#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 144810#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF4811#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 04812#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift)4813 4814/*define for COMPLETION_SIGNAL_HI word*/4815/*define for completion_signal_63_32 field*/4816#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 154817#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF4818#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 04819#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift)4820 4821 4822#endif /* __NAVI10_SDMA_PKT_OPEN_H_ */4823