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1/*2 * Copyright 2018 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22 23#include <linux/firmware.h>24#include <linux/module.h>25#include <linux/vmalloc.h>26#include <drm/drm_drv.h>27 28#include "amdgpu.h"29#include "amdgpu_psp.h"30#include "amdgpu_ras.h"31#include "amdgpu_ucode.h"32#include "soc15_common.h"33#include "psp_v11_0.h"34 35#include "mp/mp_11_0_offset.h"36#include "mp/mp_11_0_sh_mask.h"37#include "gc/gc_9_0_offset.h"38#include "sdma0/sdma0_4_0_offset.h"39#include "nbio/nbio_7_4_offset.h"40 41#include "oss/osssys_4_0_offset.h"42#include "oss/osssys_4_0_sh_mask.h"43 44MODULE_FIRMWARE("amdgpu/vega20_sos.bin");45MODULE_FIRMWARE("amdgpu/vega20_asd.bin");46MODULE_FIRMWARE("amdgpu/vega20_ta.bin");47MODULE_FIRMWARE("amdgpu/navi10_sos.bin");48MODULE_FIRMWARE("amdgpu/navi10_asd.bin");49MODULE_FIRMWARE("amdgpu/navi10_ta.bin");50MODULE_FIRMWARE("amdgpu/navi14_sos.bin");51MODULE_FIRMWARE("amdgpu/navi14_asd.bin");52MODULE_FIRMWARE("amdgpu/navi14_ta.bin");53MODULE_FIRMWARE("amdgpu/navi12_sos.bin");54MODULE_FIRMWARE("amdgpu/navi12_asd.bin");55MODULE_FIRMWARE("amdgpu/navi12_ta.bin");56MODULE_FIRMWARE("amdgpu/navi12_cap.bin");57MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");58MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");59MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");60MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");61MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");62MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin");63MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");64MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");65MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");66MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");67MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");68MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin");69MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin");70MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin");71 72/* address block */73#define smnMP1_FIRMWARE_FLAGS 0x301002474/* navi10 reg offset define */75#define mmRLC_GPM_UCODE_ADDR_NV10 0x5b6176#define mmRLC_GPM_UCODE_DATA_NV10 0x5b6277#define mmSDMA0_UCODE_ADDR_NV10 0x588078#define mmSDMA0_UCODE_DATA_NV10 0x588179/* memory training timeout define */80#define MEM_TRAIN_SEND_MSG_TIMEOUT_US 300000081 82/* For large FW files the time to complete can be very long */83#define USBC_PD_POLLING_LIMIT_S 24084 85/* Read USB-PD from LFB */86#define GFX_CMD_USB_PD_USE_LFB 0x48087 88static int psp_v11_0_init_microcode(struct psp_context *psp)89{90 struct amdgpu_device *adev = psp->adev;91 char ucode_prefix[30];92 int err = 0;93 94 DRM_DEBUG("\n");95 96 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));97 98 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {99 case IP_VERSION(11, 0, 2):100 case IP_VERSION(11, 0, 4):101 err = psp_init_sos_microcode(psp, ucode_prefix);102 if (err)103 return err;104 err = psp_init_asd_microcode(psp, ucode_prefix);105 if (err)106 return err;107 err = psp_init_ta_microcode(psp, ucode_prefix);108 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;109 break;110 case IP_VERSION(11, 0, 0):111 case IP_VERSION(11, 0, 5):112 case IP_VERSION(11, 0, 9):113 err = psp_init_sos_microcode(psp, ucode_prefix);114 if (err)115 return err;116 err = psp_init_asd_microcode(psp, ucode_prefix);117 if (err)118 return err;119 err = psp_init_ta_microcode(psp, ucode_prefix);120 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;121 break;122 case IP_VERSION(11, 0, 7):123 case IP_VERSION(11, 0, 11):124 case IP_VERSION(11, 0, 12):125 case IP_VERSION(11, 0, 13):126 err = psp_init_sos_microcode(psp, ucode_prefix);127 if (err)128 return err;129 err = psp_init_ta_microcode(psp, ucode_prefix);130 break;131 case IP_VERSION(11, 5, 0):132 err = psp_init_asd_microcode(psp, ucode_prefix);133 if (err)134 return err;135 err = psp_init_toc_microcode(psp, ucode_prefix);136 break;137 default:138 BUG();139 }140 141 return err;142}143 144static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)145{146 struct amdgpu_device *adev = psp->adev;147 148 int ret;149 int retry_loop;150 151 for (retry_loop = 0; retry_loop < 10; retry_loop++) {152 /* Wait for bootloader to signify that is153 ready having bit 31 of C2PMSG_35 set to 1 */154 ret = psp_wait_for(psp,155 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),156 0x80000000,157 0x80000000,158 false);159 160 if (ret == 0)161 return 0;162 }163 164 return ret;165}166 167static bool psp_v11_0_is_sos_alive(struct psp_context *psp)168{169 struct amdgpu_device *adev = psp->adev;170 uint32_t sol_reg;171 172 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);173 174 return sol_reg != 0x0;175}176 177static int psp_v11_0_bootloader_load_component(struct psp_context *psp,178 struct psp_bin_desc *bin_desc,179 enum psp_bootloader_cmd bl_cmd)180{181 int ret;182 uint32_t psp_gfxdrv_command_reg = 0;183 struct amdgpu_device *adev = psp->adev;184 185 /* Check sOS sign of life register to confirm sys driver and sOS186 * are already been loaded.187 */188 if (psp_v11_0_is_sos_alive(psp))189 return 0;190 191 ret = psp_v11_0_wait_for_bootloader(psp);192 if (ret)193 return ret;194 195 /* Copy PSP System Driver binary to memory */196 psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes);197 198 /* Provide the sys driver to bootloader */199 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,200 (uint32_t)(psp->fw_pri_mc_addr >> 20));201 psp_gfxdrv_command_reg = bl_cmd;202 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,203 psp_gfxdrv_command_reg);204 205 ret = psp_v11_0_wait_for_bootloader(psp);206 207 return ret;208}209 210static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)211{212 return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);213}214 215static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)216{217 return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE);218}219 220static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)221{222 return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);223}224 225static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)226{227 int ret;228 unsigned int psp_gfxdrv_command_reg = 0;229 struct amdgpu_device *adev = psp->adev;230 231 /* Check sOS sign of life register to confirm sys driver and sOS232 * are already been loaded.233 */234 if (psp_v11_0_is_sos_alive(psp))235 return 0;236 237 ret = psp_v11_0_wait_for_bootloader(psp);238 if (ret)239 return ret;240 241 /* Copy Secure OS binary to PSP memory */242 psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);243 244 /* Provide the PSP secure OS to bootloader */245 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,246 (uint32_t)(psp->fw_pri_mc_addr >> 20));247 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;248 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,249 psp_gfxdrv_command_reg);250 251 /* there might be handshake issue with hardware which needs delay */252 mdelay(20);253 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),254 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),255 0, true);256 257 return ret;258}259 260static int psp_v11_0_ring_stop(struct psp_context *psp,261 enum psp_ring_type ring_type)262{263 int ret = 0;264 struct amdgpu_device *adev = psp->adev;265 266 /* Write the ring destroy command*/267 if (amdgpu_sriov_vf(adev))268 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,269 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);270 else271 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,272 GFX_CTRL_CMD_ID_DESTROY_RINGS);273 274 /* there might be handshake issue with hardware which needs delay */275 mdelay(20);276 277 /* Wait for response flag (bit 31) */278 if (amdgpu_sriov_vf(adev))279 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),280 0x80000000, 0x80000000, false);281 else282 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),283 0x80000000, 0x80000000, false);284 285 return ret;286}287 288static int psp_v11_0_ring_create(struct psp_context *psp,289 enum psp_ring_type ring_type)290{291 int ret = 0;292 unsigned int psp_ring_reg = 0;293 struct psp_ring *ring = &psp->km_ring;294 struct amdgpu_device *adev = psp->adev;295 296 if (amdgpu_sriov_vf(adev)) {297 ring->ring_wptr = 0;298 ret = psp_v11_0_ring_stop(psp, ring_type);299 if (ret) {300 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");301 return ret;302 }303 304 /* Write low address of the ring to C2PMSG_102 */305 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);306 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);307 /* Write high address of the ring to C2PMSG_103 */308 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);309 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);310 311 /* Write the ring initialization command to C2PMSG_101 */312 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,313 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);314 315 /* there might be handshake issue with hardware which needs delay */316 mdelay(20);317 318 /* Wait for response flag (bit 31) in C2PMSG_101 */319 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),320 0x80000000, 0x8000FFFF, false);321 322 } else {323 /* Wait for sOS ready for ring creation */324 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),325 0x80000000, 0x80000000, false);326 if (ret) {327 DRM_ERROR("Failed to wait for sOS ready for ring creation\n");328 return ret;329 }330 331 /* Write low address of the ring to C2PMSG_69 */332 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);333 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);334 /* Write high address of the ring to C2PMSG_70 */335 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);336 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);337 /* Write size of ring to C2PMSG_71 */338 psp_ring_reg = ring->ring_size;339 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);340 /* Write the ring initialization command to C2PMSG_64 */341 psp_ring_reg = ring_type;342 psp_ring_reg = psp_ring_reg << 16;343 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);344 345 /* there might be handshake issue with hardware which needs delay */346 mdelay(20);347 348 /* Wait for response flag (bit 31) in C2PMSG_64 */349 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),350 0x80000000, 0x8000FFFF, false);351 }352 353 return ret;354}355 356 357static int psp_v11_0_ring_destroy(struct psp_context *psp,358 enum psp_ring_type ring_type)359{360 int ret = 0;361 struct psp_ring *ring = &psp->km_ring;362 struct amdgpu_device *adev = psp->adev;363 364 ret = psp_v11_0_ring_stop(psp, ring_type);365 if (ret)366 DRM_ERROR("Fail to stop psp ring\n");367 368 amdgpu_bo_free_kernel(&adev->firmware.rbuf,369 &ring->ring_mem_mc_addr,370 (void **)&ring->ring_mem);371 372 return ret;373}374 375static int psp_v11_0_mode1_reset(struct psp_context *psp)376{377 int ret;378 uint32_t offset;379 struct amdgpu_device *adev = psp->adev;380 381 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);382 383 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);384 385 if (ret) {386 DRM_INFO("psp is not working correctly before mode1 reset!\n");387 return -EINVAL;388 }389 390 /*send the mode 1 reset command*/391 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);392 393 msleep(500);394 395 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);396 397 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);398 399 if (ret) {400 DRM_INFO("psp mode 1 reset failed!\n");401 return -EINVAL;402 }403 404 DRM_INFO("psp mode1 reset succeed \n");405 406 return 0;407}408 409static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)410{411 int ret;412 int i;413 uint32_t data_32;414 int max_wait;415 struct amdgpu_device *adev = psp->adev;416 417 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);418 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);419 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);420 421 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;422 for (i = 0; i < max_wait; i++) {423 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),424 0x80000000, 0x80000000, false);425 if (ret == 0)426 break;427 }428 if (i < max_wait)429 ret = 0;430 else431 ret = -ETIME;432 433 DRM_DEBUG("training %s %s, cost %d @ %d ms\n",434 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",435 (ret == 0) ? "succeed" : "failed",436 i, adev->usec_timeout/1000);437 return ret;438}439 440/*441 * save and restore process442 */443static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)444{445 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;446 uint32_t *pcache = (uint32_t *)ctx->sys_cache;447 struct amdgpu_device *adev = psp->adev;448 uint32_t p2c_header[4];449 uint32_t sz;450 void *buf;451 int ret, idx;452 453 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {454 DRM_DEBUG("Memory training is not supported.\n");455 return 0;456 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {457 DRM_ERROR("Memory training initialization failure.\n");458 return -EINVAL;459 }460 461 if (psp_v11_0_is_sos_alive(psp)) {462 DRM_DEBUG("SOS is alive, skip memory training.\n");463 return 0;464 }465 466 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);467 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",468 pcache[0], pcache[1], pcache[2], pcache[3],469 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);470 471 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {472 DRM_DEBUG("Short training depends on restore.\n");473 ops |= PSP_MEM_TRAIN_RESTORE;474 }475 476 if ((ops & PSP_MEM_TRAIN_RESTORE) &&477 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {478 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");479 ops |= PSP_MEM_TRAIN_SAVE;480 }481 482 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&483 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&484 pcache[3] == p2c_header[3])) {485 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");486 ops |= PSP_MEM_TRAIN_SAVE;487 }488 489 if ((ops & PSP_MEM_TRAIN_SAVE) &&490 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {491 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");492 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;493 }494 495 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {496 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;497 ops |= PSP_MEM_TRAIN_SAVE;498 }499 500 DRM_DEBUG("Memory training ops:%x.\n", ops);501 502 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {503 /*504 * Long training will encroach a certain amount on the bottom of VRAM;505 * save the content from the bottom of VRAM to system memory506 * before training, and restore it after training to avoid507 * VRAM corruption.508 */509 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;510 511 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {512 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",513 adev->gmc.visible_vram_size,514 adev->mman.aper_base_kaddr);515 return -EINVAL;516 }517 518 buf = vmalloc(sz);519 if (!buf) {520 DRM_ERROR("failed to allocate system memory.\n");521 return -ENOMEM;522 }523 524 if (drm_dev_enter(adev_to_drm(adev), &idx)) {525 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);526 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);527 if (ret) {528 DRM_ERROR("Send long training msg failed.\n");529 vfree(buf);530 drm_dev_exit(idx);531 return ret;532 }533 534 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);535 adev->hdp.funcs->flush_hdp(adev, NULL);536 vfree(buf);537 drm_dev_exit(idx);538 } else {539 vfree(buf);540 return -ENODEV;541 }542 }543 544 if (ops & PSP_MEM_TRAIN_SAVE) {545 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);546 }547 548 if (ops & PSP_MEM_TRAIN_RESTORE) {549 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);550 }551 552 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {553 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?554 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);555 if (ret) {556 DRM_ERROR("send training msg failed.\n");557 return ret;558 }559 }560 ctx->training_cnt++;561 return 0;562}563 564static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)565{566 uint32_t data;567 struct amdgpu_device *adev = psp->adev;568 569 if (amdgpu_sriov_vf(adev))570 data = psp->km_ring.ring_wptr;571 else572 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);573 574 return data;575}576 577static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)578{579 struct amdgpu_device *adev = psp->adev;580 581 if (amdgpu_sriov_vf(adev)) {582 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);583 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);584 psp->km_ring.ring_wptr = value;585 } else586 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);587}588 589static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)590{591 struct amdgpu_device *adev = psp->adev;592 uint32_t reg_status;593 int ret, i = 0;594 595 /*596 * LFB address which is aligned to 1MB address and has to be597 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P598 * register599 */600 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));601 602 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),603 0x80000000, 0x80000000, false);604 if (ret)605 return ret;606 607 /* Fireup interrupt so PSP can pick up the address */608 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));609 610 /* FW load takes very long time */611 do {612 msleep(1000);613 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);614 615 if (reg_status & 0x80000000)616 goto done;617 618 } while (++i < USBC_PD_POLLING_LIMIT_S);619 620 return -ETIME;621done:622 623 if ((reg_status & 0xFFFF) != 0) {624 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n",625 reg_status & 0xFFFF);626 return -EIO;627 }628 629 return 0;630}631 632static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)633{634 struct amdgpu_device *adev = psp->adev;635 int ret;636 637 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);638 639 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),640 0x80000000, 0x80000000, false);641 if (!ret)642 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);643 644 return ret;645}646 647static const struct psp_funcs psp_v11_0_funcs = {648 .init_microcode = psp_v11_0_init_microcode,649 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,650 .bootloader_load_spl = psp_v11_0_bootloader_load_spl,651 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,652 .bootloader_load_sos = psp_v11_0_bootloader_load_sos,653 .ring_create = psp_v11_0_ring_create,654 .ring_stop = psp_v11_0_ring_stop,655 .ring_destroy = psp_v11_0_ring_destroy,656 .mode1_reset = psp_v11_0_mode1_reset,657 .mem_training = psp_v11_0_memory_training,658 .ring_get_wptr = psp_v11_0_ring_get_wptr,659 .ring_set_wptr = psp_v11_0_ring_set_wptr,660 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,661 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw662};663 664void psp_v11_0_set_psp_funcs(struct psp_context *psp)665{666 psp->funcs = &psp_v11_0_funcs;667}668