292 lines · c
1/*2 * Copyright 2016 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23#ifndef SI_ENUMS_H24#define SI_ENUMS_H25 26#define VBLANK_INT_MASK (1 << 0)27#define DC_HPDx_INT_EN (1 << 16)28#define VBLANK_ACK (1 << 4)29#define VLINE_ACK (1 << 4)30 31#define CURSOR_WIDTH 6432#define CURSOR_HEIGHT 6433 34#define VGA_VSTATUS_CNTL 0xFFFCFFFF35#define PRIORITY_MARK_MASK 0x7fff36#define PRIORITY_OFF (1 << 16)37#define PRIORITY_ALWAYS_ON (1 << 20)38#define INTERLEAVE_EN (1 << 0)39 40#define LATENCY_WATERMARK_MASK(x) ((x) << 16)41#define DC_LB_MEMORY_CONFIG(x) ((x) << 20)42#define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)43 44#define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)45#define GRPH_ENDIAN_NONE 046#define GRPH_ENDIAN_8IN16 147#define GRPH_ENDIAN_8IN32 248#define GRPH_ENDIAN_8IN64 349#define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)50#define GRPH_RED_SEL_R 051#define GRPH_RED_SEL_G 152#define GRPH_RED_SEL_B 253#define GRPH_RED_SEL_A 354#define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)55#define GRPH_GREEN_SEL_G 056#define GRPH_GREEN_SEL_B 157#define GRPH_GREEN_SEL_A 258#define GRPH_GREEN_SEL_R 359#define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)60#define GRPH_BLUE_SEL_B 061#define GRPH_BLUE_SEL_A 162#define GRPH_BLUE_SEL_R 263#define GRPH_BLUE_SEL_G 364#define GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)65#define GRPH_ALPHA_SEL_A 066#define GRPH_ALPHA_SEL_R 167#define GRPH_ALPHA_SEL_G 268#define GRPH_ALPHA_SEL_B 369 70#define GRPH_DEPTH(x) (((x) & 0x3) << 0)71#define GRPH_DEPTH_8BPP 072#define GRPH_DEPTH_16BPP 173#define GRPH_DEPTH_32BPP 274 75#define GRPH_FORMAT(x) (((x) & 0x7) << 8)76#define GRPH_FORMAT_INDEXED 077#define GRPH_FORMAT_ARGB1555 078#define GRPH_FORMAT_ARGB565 179#define GRPH_FORMAT_ARGB4444 280#define GRPH_FORMAT_AI88 381#define GRPH_FORMAT_MONO16 482#define GRPH_FORMAT_BGRA5551 583#define GRPH_FORMAT_ARGB8888 084#define GRPH_FORMAT_ARGB2101010 185#define GRPH_FORMAT_32BPP_DIG 286#define GRPH_FORMAT_8B_ARGB2101010 387#define GRPH_FORMAT_BGRA1010102 488#define GRPH_FORMAT_8B_BGRA1010102 589#define GRPH_FORMAT_RGB111110 690#define GRPH_FORMAT_BGR101111 791 92#define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)93#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)94#define GRPH_ARRAY_LINEAR_GENERAL 095#define GRPH_ARRAY_LINEAR_ALIGNED 196#define GRPH_ARRAY_1D_TILED_THIN1 297#define GRPH_ARRAY_2D_TILED_THIN1 498#define GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)99#define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)100#define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)101#define GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)102#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)103#define GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)104 105#define CURSOR_EN (1 << 0)106#define CURSOR_MODE(x) (((x) & 0x3) << 8)107#define CURSOR_MONO 0108#define CURSOR_24_1 1109#define CURSOR_24_8_PRE_MULT 2110#define CURSOR_24_8_UNPRE_MULT 3111#define CURSOR_2X_MAGNIFY (1 << 16)112#define CURSOR_FORCE_MC_ON (1 << 20)113#define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)114#define CURSOR_URGENT_ALWAYS 0115#define CURSOR_URGENT_1_8 1116#define CURSOR_URGENT_1_4 2117#define CURSOR_URGENT_3_8 3118#define CURSOR_URGENT_1_2 4119#define CURSOR_UPDATE_PENDING (1 << 0)120#define CURSOR_UPDATE_TAKEN (1 << 1)121#define CURSOR_UPDATE_LOCK (1 << 16)122#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)123 124#define SI_CRTC0_REGISTER_OFFSET 0125#define SI_CRTC1_REGISTER_OFFSET 0x300126#define SI_CRTC2_REGISTER_OFFSET 0x2600127#define SI_CRTC3_REGISTER_OFFSET 0x2900128#define SI_CRTC4_REGISTER_OFFSET 0x2c00129#define SI_CRTC5_REGISTER_OFFSET 0x2f00130 131#define DMA0_REGISTER_OFFSET 0x000132#define DMA1_REGISTER_OFFSET 0x200133#define ES_AND_GS_AUTO 3134#define RADEON_PACKET_TYPE3 3135#define CE_PARTITION_BASE 3136#define BUF_SWAP_32BIT (2 << 16)137 138#define GFX_POWER_STATUS (1 << 1)139#define GFX_CLOCK_STATUS (1 << 2)140#define GFX_LS_STATUS (1 << 3)141#define RLC_BUSY_STATUS (1 << 0)142 143#define RLC_PUD(x) ((x) << 0)144#define RLC_PUD_MASK (0xff << 0)145#define RLC_PDD(x) ((x) << 8)146#define RLC_PDD_MASK (0xff << 8)147#define RLC_TTPD(x) ((x) << 16)148#define RLC_TTPD_MASK (0xff << 16)149#define RLC_MSD(x) ((x) << 24)150#define RLC_MSD_MASK (0xff << 24)151#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)152#define WRITE_DATA_DST_SEL(x) ((x) << 8)153#define EVENT_TYPE(x) ((x) << 0)154#define EVENT_INDEX(x) ((x) << 8)155#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)156#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)157#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)158 159#define GFX6_NUM_GFX_RINGS 1160#define GFX6_NUM_COMPUTE_RINGS 2161#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90162#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D163 164#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003165#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x02010002166#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02011003167 168#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \169 (((op) & 0xFF) << 8) | \170 ((n) & 0x3FFF) << 16)171#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)172#define PACKET3_NOP 0x10173#define PACKET3_SET_BASE 0x11174#define PACKET3_BASE_INDEX(x) ((x) << 0)175#define PACKET3_CLEAR_STATE 0x12176#define PACKET3_INDEX_BUFFER_SIZE 0x13177#define PACKET3_DISPATCH_DIRECT 0x15178#define PACKET3_DISPATCH_INDIRECT 0x16179#define PACKET3_ALLOC_GDS 0x1B180#define PACKET3_WRITE_GDS_RAM 0x1C181#define PACKET3_ATOMIC_GDS 0x1D182#define PACKET3_ATOMIC 0x1E183#define PACKET3_OCCLUSION_QUERY 0x1F184#define PACKET3_SET_PREDICATION 0x20185#define PACKET3_REG_RMW 0x21186#define PACKET3_COND_EXEC 0x22187#define PACKET3_PRED_EXEC 0x23188#define PACKET3_DRAW_INDIRECT 0x24189#define PACKET3_DRAW_INDEX_INDIRECT 0x25190#define PACKET3_INDEX_BASE 0x26191#define PACKET3_DRAW_INDEX_2 0x27192#define PACKET3_CONTEXT_CONTROL 0x28193#define PACKET3_INDEX_TYPE 0x2A194#define PACKET3_DRAW_INDIRECT_MULTI 0x2C195#define PACKET3_DRAW_INDEX_AUTO 0x2D196#define PACKET3_DRAW_INDEX_IMMD 0x2E197#define PACKET3_NUM_INSTANCES 0x2F198#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30199#define PACKET3_INDIRECT_BUFFER_CONST 0x31200#define PACKET3_INDIRECT_BUFFER 0x3F201#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34202#define PACKET3_DRAW_INDEX_OFFSET_2 0x35203#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36204#define PACKET3_WRITE_DATA 0x37205#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38206#define PACKET3_MEM_SEMAPHORE 0x39207#define PACKET3_MPEG_INDEX 0x3A208#define PACKET3_COPY_DW 0x3B209#define PACKET3_WAIT_REG_MEM 0x3C210#define PACKET3_MEM_WRITE 0x3D211#define PACKET3_COPY_DATA 0x40212#define PACKET3_CP_DMA 0x41213# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)214# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)215# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)216# define PACKET3_CP_DMA_CP_SYNC (1 << 31)217# define PACKET3_CP_DMA_DIS_WC (1 << 21)218# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)219# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)220# define PACKET3_CP_DMA_CMD_SAS (1 << 26)221# define PACKET3_CP_DMA_CMD_DAS (1 << 27)222# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)223# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)224# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)225#define PACKET3_PFP_SYNC_ME 0x42226#define PACKET3_SURFACE_SYNC 0x43227# define PACKET3_DEST_BASE_0_ENA (1 << 0)228# define PACKET3_DEST_BASE_1_ENA (1 << 1)229# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)230# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)231# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)232# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)233# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)234# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)235# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)236# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)237# define PACKET3_DB_DEST_BASE_ENA (1 << 14)238# define PACKET3_DEST_BASE_2_ENA (1 << 19)239# define PACKET3_DEST_BASE_3_ENA (1 << 21)240# define PACKET3_TCL1_ACTION_ENA (1 << 22)241# define PACKET3_TC_ACTION_ENA (1 << 23)242# define PACKET3_CB_ACTION_ENA (1 << 25)243# define PACKET3_DB_ACTION_ENA (1 << 26)244# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)245# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)246#define PACKET3_ME_INITIALIZE 0x44247#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)248#define PACKET3_COND_WRITE 0x45249#define PACKET3_EVENT_WRITE 0x46250#define PACKET3_EVENT_WRITE_EOP 0x47251#define PACKET3_EVENT_WRITE_EOS 0x48252#define PACKET3_PREAMBLE_CNTL 0x4A253# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)254# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)255#define PACKET3_ONE_REG_WRITE 0x57256#define PACKET3_LOAD_CONFIG_REG 0x5F257#define PACKET3_LOAD_CONTEXT_REG 0x60258#define PACKET3_LOAD_SH_REG 0x61259#define PACKET3_SET_CONFIG_REG 0x68260#define PACKET3_SET_CONFIG_REG_START 0x00002000261#define PACKET3_SET_CONFIG_REG_END 0x00002c00262#define PACKET3_SET_CONTEXT_REG 0x69263#define PACKET3_SET_CONTEXT_REG_START 0x000a000264#define PACKET3_SET_CONTEXT_REG_END 0x000a400265#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73266#define PACKET3_SET_RESOURCE_INDIRECT 0x74267#define PACKET3_SET_SH_REG 0x76268#define PACKET3_SET_SH_REG_START 0x00002c00269#define PACKET3_SET_SH_REG_END 0x00003000270#define PACKET3_SET_SH_REG_OFFSET 0x77271#define PACKET3_ME_WRITE 0x7A272#define PACKET3_SCRATCH_RAM_WRITE 0x7D273#define PACKET3_SCRATCH_RAM_READ 0x7E274#define PACKET3_CE_WRITE 0x7F275#define PACKET3_LOAD_CONST_RAM 0x80276#define PACKET3_WRITE_CONST_RAM 0x81277#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82278#define PACKET3_DUMP_CONST_RAM 0x83279#define PACKET3_INCREMENT_CE_COUNTER 0x84280#define PACKET3_INCREMENT_DE_COUNTER 0x85281#define PACKET3_WAIT_ON_CE_COUNTER 0x86282#define PACKET3_WAIT_ON_DE_COUNTER 0x87283#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88284#define PACKET3_SET_CE_DE_COUNTERS 0x89285#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A286#define PACKET3_SWITCH_BUFFER 0x8B287#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)288#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)289#define PACKET3_SEM_SEL_WAIT (0x7 << 29)290 291#endif292