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1/*2 * Copyright 2011 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: Alex Deucher23 */24#ifndef SI_H25#define SI_H26 27#define TAHITI_RB_BITMAP_WIDTH_PER_SH 228 29#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x1201100330#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x1201000231#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x0201000132 33#define SI_MAX_SH_GPRS 25634#define SI_MAX_TEMP_GPRS 1635#define SI_MAX_SH_THREADS 25636#define SI_MAX_SH_STACK_ENTRIES 409637#define SI_MAX_FRC_EOV_CNT 1638438#define SI_MAX_BACKENDS 839#define SI_MAX_BACKENDS_MASK 0xFF40#define SI_MAX_BACKENDS_PER_SE_MASK 0x0F41#define SI_MAX_SIMDS 1242#define SI_MAX_SIMDS_MASK 0x0FFF43#define SI_MAX_SIMDS_PER_SE_MASK 0x00FF44#define SI_MAX_PIPES 845#define SI_MAX_PIPES_MASK 0xFF46#define SI_MAX_PIPES_PER_SIMD_MASK 0x3F47#define SI_MAX_LDS_NUM 0xFFFF48#define SI_MAX_TCC 1649#define SI_MAX_TCC_MASK 0xFFFF50#define SI_MAX_CTLACKS_ASSERTION_WAIT 10051 52/* SMC IND accessor regs */53#define SMC_IND_INDEX_0 0x8054#define SMC_IND_DATA_0 0x8155 56#define SMC_IND_ACCESS_CNTL 0x8A57# define AUTO_INCREMENT_IND_0 (1 << 0)58#define SMC_MESSAGE_0 0x8B59#define SMC_RESP_0 0x8C60 61/* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */62#define SMC_CG_IND_START 0xc003000063#define SMC_CG_IND_END 0xc004000064 65#define CG_CGTT_LOCAL_0 0x40066#define CG_CGTT_LOCAL_1 0x40167 68/* SMC IND registers */69#define SMC_SYSCON_RESET_CNTL 0x8000000070# define RST_REG (1 << 0)71#define SMC_SYSCON_CLOCK_CNTL_0 0x8000000472# define CK_DISABLE (1 << 0)73# define CKEN (1 << 24)74 75#define VGA_HDP_CONTROL 0xCA76#define VGA_MEMORY_DISABLE (1 << 4)77 78#define DCCG_DISP_SLOW_SELECT_REG 0x13F79#define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)80#define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)81#define DCCG_DISP1_SLOW_SELECT_SHIFT 082#define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4)83#define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4)84#define DCCG_DISP2_SLOW_SELECT_SHIFT 485 86#define CG_SPLL_FUNC_CNTL 0x18087#define SPLL_RESET (1 << 0)88#define SPLL_SLEEP (1 << 1)89#define SPLL_BYPASS_EN (1 << 3)90#define SPLL_REF_DIV(x) ((x) << 4)91#define SPLL_REF_DIV_MASK (0x3f << 4)92#define SPLL_PDIV_A(x) ((x) << 20)93#define SPLL_PDIV_A_MASK (0x7f << 20)94#define SPLL_PDIV_A_SHIFT 2095#define CG_SPLL_FUNC_CNTL_2 0x18196#define SCLK_MUX_SEL(x) ((x) << 0)97#define SCLK_MUX_SEL_MASK (0x1ff << 0)98#define SPLL_CTLREQ_CHG (1 << 23)99#define SCLK_MUX_UPDATE (1 << 26)100#define CG_SPLL_FUNC_CNTL_3 0x182101#define SPLL_FB_DIV(x) ((x) << 0)102#define SPLL_FB_DIV_MASK (0x3ffffff << 0)103#define SPLL_FB_DIV_SHIFT 0104#define SPLL_DITHEN (1 << 28)105#define CG_SPLL_FUNC_CNTL_4 0x183106 107#define SPLL_STATUS 0x185108#define SPLL_CHG_STATUS (1 << 1)109#define SPLL_CNTL_MODE 0x186110#define SPLL_SW_DIR_CONTROL (1 << 0)111# define SPLL_REFCLK_SEL(x) ((x) << 26)112# define SPLL_REFCLK_SEL_MASK (3 << 26)113 114#define CG_SPLL_SPREAD_SPECTRUM 0x188115#define SSEN (1 << 0)116#define CLK_S(x) ((x) << 4)117#define CLK_S_MASK (0xfff << 4)118#define CLK_S_SHIFT 4119#define CG_SPLL_SPREAD_SPECTRUM_2 0x189120#define CLK_V(x) ((x) << 0)121#define CLK_V_MASK (0x3ffffff << 0)122#define CLK_V_SHIFT 0123 124#define CG_SPLL_AUTOSCALE_CNTL 0x18b125# define AUTOSCALE_ON_SS_CLEAR (1 << 9)126 127/* discrete uvd clocks */128#define CG_UPLL_FUNC_CNTL 0x18d129# define UPLL_RESET_MASK 0x00000001130# define UPLL_SLEEP_MASK 0x00000002131# define UPLL_BYPASS_EN_MASK 0x00000004132# define UPLL_CTLREQ_MASK 0x00000008133# define UPLL_VCO_MODE_MASK 0x00000600134# define UPLL_REF_DIV_MASK 0x003F0000135# define UPLL_CTLACK_MASK 0x40000000136# define UPLL_CTLACK2_MASK 0x80000000137#define CG_UPLL_FUNC_CNTL_2 0x18e138# define UPLL_PDIV_A(x) ((x) << 0)139# define UPLL_PDIV_A_MASK 0x0000007F140# define UPLL_PDIV_B(x) ((x) << 8)141# define UPLL_PDIV_B_MASK 0x00007F00142# define VCLK_SRC_SEL(x) ((x) << 20)143# define VCLK_SRC_SEL_MASK 0x01F00000144# define DCLK_SRC_SEL(x) ((x) << 25)145# define DCLK_SRC_SEL_MASK 0x3E000000146#define CG_UPLL_FUNC_CNTL_3 0x18f147# define UPLL_FB_DIV(x) ((x) << 0)148# define UPLL_FB_DIV_MASK 0x01FFFFFF149#define CG_UPLL_FUNC_CNTL_4 0x191150# define UPLL_SPARE_ISPARE9 0x00020000151#define CG_UPLL_FUNC_CNTL_5 0x192152# define RESET_ANTI_MUX_MASK 0x00000200153#define CG_UPLL_SPREAD_SPECTRUM 0x194154# define SSEN_MASK 0x00000001155 156#define MPLL_BYPASSCLK_SEL 0x197157# define MPLL_CLKOUT_SEL(x) ((x) << 8)158# define MPLL_CLKOUT_SEL_MASK 0xFF00159 160#define CG_CLKPIN_CNTL 0x198161# define XTALIN_DIVIDE (1 << 1)162# define BCLK_AS_XCLK (1 << 2)163#define CG_CLKPIN_CNTL_2 0x199164# define FORCE_BIF_REFCLK_EN (1 << 3)165# define MUX_TCLK_TO_XCLK (1 << 8)166 167#define THM_CLK_CNTL 0x19b168# define CMON_CLK_SEL(x) ((x) << 0)169# define CMON_CLK_SEL_MASK 0xFF170# define TMON_CLK_SEL(x) ((x) << 8)171# define TMON_CLK_SEL_MASK 0xFF00172#define MISC_CLK_CNTL 0x19c173# define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)174# define DEEP_SLEEP_CLK_SEL_MASK 0xFF175# define ZCLK_SEL(x) ((x) << 8)176# define ZCLK_SEL_MASK 0xFF00177 178#define CG_THERMAL_CTRL 0x1c0179#define DPM_EVENT_SRC(x) ((x) << 0)180#define DPM_EVENT_SRC_MASK (7 << 0)181#define DIG_THERM_DPM(x) ((x) << 14)182#define DIG_THERM_DPM_MASK 0x003FC000183#define DIG_THERM_DPM_SHIFT 14184#define CG_THERMAL_STATUS 0x1c1185#define FDO_PWM_DUTY(x) ((x) << 9)186#define FDO_PWM_DUTY_MASK (0xff << 9)187#define FDO_PWM_DUTY_SHIFT 9188#define CG_THERMAL_INT 0x1c2189#define DIG_THERM_INTH(x) ((x) << 8)190#define DIG_THERM_INTH_MASK 0x0000FF00191#define DIG_THERM_INTH_SHIFT 8192#define DIG_THERM_INTL(x) ((x) << 16)193#define DIG_THERM_INTL_MASK 0x00FF0000194#define DIG_THERM_INTL_SHIFT 16195#define THERM_INT_MASK_HIGH (1 << 24)196#define THERM_INT_MASK_LOW (1 << 25)197 198#define CG_MULT_THERMAL_CTRL 0x1c4199#define TEMP_SEL(x) ((x) << 20)200#define TEMP_SEL_MASK (0xff << 20)201#define TEMP_SEL_SHIFT 20202#define CG_MULT_THERMAL_STATUS 0x1c5203#define ASIC_MAX_TEMP(x) ((x) << 0)204#define ASIC_MAX_TEMP_MASK 0x000001ff205#define ASIC_MAX_TEMP_SHIFT 0206#define CTF_TEMP(x) ((x) << 9)207#define CTF_TEMP_MASK 0x0003fe00208#define CTF_TEMP_SHIFT 9209 210#define CG_FDO_CTRL0 0x1d5211#define FDO_STATIC_DUTY(x) ((x) << 0)212#define FDO_STATIC_DUTY_MASK 0x000000FF213#define FDO_STATIC_DUTY_SHIFT 0214#define CG_FDO_CTRL1 0x1d6215#define FMAX_DUTY100(x) ((x) << 0)216#define FMAX_DUTY100_MASK 0x000000FF217#define FMAX_DUTY100_SHIFT 0218#define CG_FDO_CTRL2 0x1d7219#define TMIN(x) ((x) << 0)220#define TMIN_MASK 0x000000FF221#define TMIN_SHIFT 0222#define FDO_PWM_MODE(x) ((x) << 11)223#define FDO_PWM_MODE_MASK (7 << 11)224#define FDO_PWM_MODE_SHIFT 11225#define TACH_PWM_RESP_RATE(x) ((x) << 25)226#define TACH_PWM_RESP_RATE_MASK (0x7f << 25)227#define TACH_PWM_RESP_RATE_SHIFT 25228 229#define CG_TACH_CTRL 0x1dc230# define EDGE_PER_REV(x) ((x) << 0)231# define EDGE_PER_REV_MASK (0x7 << 0)232# define EDGE_PER_REV_SHIFT 0233# define TARGET_PERIOD(x) ((x) << 3)234# define TARGET_PERIOD_MASK 0xfffffff8235# define TARGET_PERIOD_SHIFT 3236#define CG_TACH_STATUS 0x1dd237# define TACH_PERIOD(x) ((x) << 0)238# define TACH_PERIOD_MASK 0xffffffff239# define TACH_PERIOD_SHIFT 0240 241#define GENERAL_PWRMGT 0x1e0242# define GLOBAL_PWRMGT_EN (1 << 0)243# define STATIC_PM_EN (1 << 1)244# define THERMAL_PROTECTION_DIS (1 << 2)245# define THERMAL_PROTECTION_TYPE (1 << 3)246# define SW_SMIO_INDEX(x) ((x) << 6)247# define SW_SMIO_INDEX_MASK (1 << 6)248# define SW_SMIO_INDEX_SHIFT 6249# define VOLT_PWRMGT_EN (1 << 10)250# define DYN_SPREAD_SPECTRUM_EN (1 << 23)251#define CG_TPC 0x1e1252#define SCLK_PWRMGT_CNTL 0x1e2253# define SCLK_PWRMGT_OFF (1 << 0)254# define SCLK_LOW_D1 (1 << 1)255# define FIR_RESET (1 << 4)256# define FIR_FORCE_TREND_SEL (1 << 5)257# define FIR_TREND_MODE (1 << 6)258# define DYN_GFX_CLK_OFF_EN (1 << 7)259# define GFX_CLK_FORCE_ON (1 << 8)260# define GFX_CLK_REQUEST_OFF (1 << 9)261# define GFX_CLK_FORCE_OFF (1 << 10)262# define GFX_CLK_OFF_ACPI_D1 (1 << 11)263# define GFX_CLK_OFF_ACPI_D2 (1 << 12)264# define GFX_CLK_OFF_ACPI_D3 (1 << 13)265# define DYN_LIGHT_SLEEP_EN (1 << 14)266 267#define TARGET_AND_CURRENT_PROFILE_INDEX 0x1e6268# define CURRENT_STATE_INDEX_MASK (0xf << 4)269# define CURRENT_STATE_INDEX_SHIFT 4270 271#define CG_FTV 0x1ef272 273#define CG_FFCT_0 0x1f0274# define UTC_0(x) ((x) << 0)275# define UTC_0_MASK (0x3ff << 0)276# define DTC_0(x) ((x) << 10)277# define DTC_0_MASK (0x3ff << 10)278 279#define CG_BSP 0x1ff280# define BSP(x) ((x) << 0)281# define BSP_MASK (0xffff << 0)282# define BSU(x) ((x) << 16)283# define BSU_MASK (0xf << 16)284#define CG_AT 0x200285# define CG_R(x) ((x) << 0)286# define CG_R_MASK (0xffff << 0)287# define CG_L(x) ((x) << 16)288# define CG_L_MASK (0xffff << 16)289 290#define CG_GIT 0x201291# define CG_GICST(x) ((x) << 0)292# define CG_GICST_MASK (0xffff << 0)293# define CG_GIPOT(x) ((x) << 16)294# define CG_GIPOT_MASK (0xffff << 16)295 296#define CG_SSP 0x203297# define SST(x) ((x) << 0)298# define SST_MASK (0xffff << 0)299# define SSTU(x) ((x) << 16)300# define SSTU_MASK (0xf << 16)301 302#define CG_DISPLAY_GAP_CNTL 0x20a303# define DISP1_GAP(x) ((x) << 0)304# define DISP1_GAP_MASK (3 << 0)305# define DISP2_GAP(x) ((x) << 2)306# define DISP2_GAP_MASK (3 << 2)307# define VBI_TIMER_COUNT(x) ((x) << 4)308# define VBI_TIMER_COUNT_MASK (0x3fff << 4)309# define VBI_TIMER_UNIT(x) ((x) << 20)310# define VBI_TIMER_UNIT_MASK (7 << 20)311# define DISP1_GAP_MCHG(x) ((x) << 24)312# define DISP1_GAP_MCHG_MASK (3 << 24)313# define DISP2_GAP_MCHG(x) ((x) << 26)314# define DISP2_GAP_MCHG_MASK (3 << 26)315 316#define CG_ULV_CONTROL 0x21e317#define CG_ULV_PARAMETER 0x21f318 319#define SMC_SCRATCH0 0x221320 321#define CG_CAC_CTRL 0x22e322# define CAC_WINDOW(x) ((x) << 0)323# define CAC_WINDOW_MASK 0x00ffffff324 325#define DMIF_ADDR_CONFIG 0x2F5326 327#define DMIF_ADDR_CALC 0x300328 329#define PIPE0_DMIF_BUFFER_CONTROL 0x0328330# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)331# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)332 333#define SRBM_STATUS 0x394334#define GRBM_RQ_PENDING (1 << 5)335#define VMC_BUSY (1 << 8)336#define MCB_BUSY (1 << 9)337#define MCB_NON_DISPLAY_BUSY (1 << 10)338#define MCC_BUSY (1 << 11)339#define MCD_BUSY (1 << 12)340#define SEM_BUSY (1 << 14)341#define IH_BUSY (1 << 17)342 343#define SRBM_SOFT_RESET 0x398344#define SOFT_RESET_BIF (1 << 1)345#define SOFT_RESET_DC (1 << 5)346#define SOFT_RESET_DMA1 (1 << 6)347#define SOFT_RESET_GRBM (1 << 8)348#define SOFT_RESET_HDP (1 << 9)349#define SOFT_RESET_IH (1 << 10)350#define SOFT_RESET_MC (1 << 11)351#define SOFT_RESET_ROM (1 << 14)352#define SOFT_RESET_SEM (1 << 15)353#define SOFT_RESET_VMC (1 << 17)354#define SOFT_RESET_DMA (1 << 20)355#define SOFT_RESET_TST (1 << 21)356#define SOFT_RESET_REGBB (1 << 22)357#define SOFT_RESET_ORB (1 << 23)358 359#define CC_SYS_RB_BACKEND_DISABLE 0x3A0360#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3A1361 362#define SRBM_READ_ERROR 0x3A6363#define SRBM_INT_CNTL 0x3A8364#define SRBM_INT_ACK 0x3AA365 366#define SRBM_STATUS2 0x3B1367#define DMA_BUSY (1 << 5)368#define DMA1_BUSY (1 << 6)369 370#define VM_L2_CNTL 0x500371#define ENABLE_L2_CACHE (1 << 0)372#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)373#define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)374#define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)375#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)376#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)377#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)378#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)379#define VM_L2_CNTL2 0x501380#define INVALIDATE_ALL_L1_TLBS (1 << 0)381#define INVALIDATE_L2_CACHE (1 << 1)382#define INVALIDATE_CACHE_MODE(x) ((x) << 26)383#define INVALIDATE_PTE_AND_PDE_CACHES 0384#define INVALIDATE_ONLY_PTE_CACHES 1385#define INVALIDATE_ONLY_PDE_CACHES 2386#define VM_L2_CNTL3 0x502387#define BANK_SELECT(x) ((x) << 0)388#define L2_CACHE_UPDATE_MODE(x) ((x) << 6)389#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)390#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)391#define VM_L2_STATUS 0x503392#define L2_BUSY (1 << 0)393#define VM_CONTEXT0_CNTL 0x504394#define ENABLE_CONTEXT (1 << 0)395#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)396#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)397#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)398#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)399#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)400#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)401#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)402#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)403#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)404#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)405#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)406#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)407#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)408#define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)409#define VM_CONTEXT1_CNTL 0x505410#define VM_CONTEXT0_CNTL2 0x50C411#define VM_CONTEXT1_CNTL2 0x50D412#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50E413#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50F414#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510415#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511416#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512417#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513418#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514419#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515420 421#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f422#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537423#define PROTECTIONS_MASK (0xf << 0)424#define PROTECTIONS_SHIFT 0425 /* bit 0: range426 * bit 1: pde0427 * bit 2: valid428 * bit 3: read429 * bit 4: write430 */431#define MEMORY_CLIENT_ID_MASK (0xff << 12)432#define MEMORY_CLIENT_ID_SHIFT 12433#define MEMORY_CLIENT_RW_MASK (1 << 24)434#define MEMORY_CLIENT_RW_SHIFT 24435#define FAULT_VMID_MASK (0xf << 25)436#define FAULT_VMID_SHIFT 25437 438#define VM_INVALIDATE_REQUEST 0x51E439#define VM_INVALIDATE_RESPONSE 0x51F440 441#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546442#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547443 444#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54F445#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550446#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551447#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552448#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553449#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554450#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555451#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556452#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557453#define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558454 455#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55F456#define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560457 458#define VM_L2_CG 0x570459#define MC_CG_ENABLE (1 << 18)460#define MC_LS_ENABLE (1 << 19)461 462#define MC_SHARED_CHMAP 0x801463#define NOOFCHAN_SHIFT 12464#define NOOFCHAN_MASK 0x0000f000465#define MC_SHARED_CHREMAP 0x802466 467#define MC_VM_FB_LOCATION 0x809468#define MC_VM_AGP_TOP 0x80A469#define MC_VM_AGP_BOT 0x80B470#define MC_VM_AGP_BASE 0x80C471#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80D472#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80E473#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80F474 475#define MC_VM_MX_L1_TLB_CNTL 0x819476#define ENABLE_L1_TLB (1 << 0)477#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)478#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)479#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)480#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)481#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)482#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)483#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)484 485#define MC_SHARED_BLACKOUT_CNTL 0x82B486 487#define MC_HUB_MISC_HUB_CG 0x82E488#define MC_HUB_MISC_VM_CG 0x82F489 490#define MC_HUB_MISC_SIP_CG 0x830491 492#define MC_XPB_CLK_GAT 0x91E493 494#define MC_CITF_MISC_RD_CG 0x992495#define MC_CITF_MISC_WR_CG 0x993496#define MC_CITF_MISC_VM_CG 0x994497 498#define MC_ARB_RAMCFG 0x9D8499#define NOOFBANK_SHIFT 0500#define NOOFBANK_MASK 0x00000003501#define NOOFRANK_SHIFT 2502#define NOOFRANK_MASK 0x00000004503#define NOOFROWS_SHIFT 3504#define NOOFROWS_MASK 0x00000038505#define NOOFCOLS_SHIFT 6506#define NOOFCOLS_MASK 0x000000C0507#define CHANSIZE_SHIFT 8508#define CHANSIZE_MASK 0x00000100509#define CHANSIZE_OVERRIDE (1 << 11)510#define NOOFGROUPS_SHIFT 12511#define NOOFGROUPS_MASK 0x00001000512 513#define MC_ARB_DRAM_TIMING 0x9DD514#define MC_ARB_DRAM_TIMING2 0x9DE515 516#define MC_ARB_BURST_TIME 0xA02517#define STATE0(x) ((x) << 0)518#define STATE0_MASK (0x1f << 0)519#define STATE0_SHIFT 0520#define STATE1(x) ((x) << 5)521#define STATE1_MASK (0x1f << 5)522#define STATE1_SHIFT 5523#define STATE2(x) ((x) << 10)524#define STATE2_MASK (0x1f << 10)525#define STATE2_SHIFT 10526#define STATE3(x) ((x) << 15)527#define STATE3_MASK (0x1f << 15)528#define STATE3_SHIFT 15529 530#define MC_SEQ_TRAIN_WAKEUP_CNTL 0xA3A531#define TRAIN_DONE_D0 (1 << 30)532#define TRAIN_DONE_D1 (1 << 31)533 534#define MC_SEQ_SUP_CNTL 0xA32535#define RUN_MASK (1 << 0)536#define MC_SEQ_SUP_PGM 0xA33537#define MC_PMG_AUTO_CMD 0xA34538 539#define MC_IO_PAD_CNTL_D0 0xA74540#define MEM_FALL_OUT_CMD (1 << 8)541 542#define MC_SEQ_RAS_TIMING 0xA28543#define MC_SEQ_CAS_TIMING 0xA29544#define MC_SEQ_MISC_TIMING 0xA2A545#define MC_SEQ_MISC_TIMING2 0xA2B546#define MC_SEQ_PMG_TIMING 0xA2C547#define MC_SEQ_RD_CTL_D0 0xA2D548#define MC_SEQ_RD_CTL_D1 0xA2E549#define MC_SEQ_WR_CTL_D0 0xA2F550#define MC_SEQ_WR_CTL_D1 0xA30551 552#define MC_SEQ_MISC0 0xA80553#define MC_SEQ_MISC0_VEN_ID_SHIFT 8554#define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00555#define MC_SEQ_MISC0_VEN_ID_VALUE 3556#define MC_SEQ_MISC0_REV_ID_SHIFT 12557#define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000558#define MC_SEQ_MISC0_REV_ID_VALUE 1559#define MC_SEQ_MISC0_GDDR5_SHIFT 28560#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000561#define MC_SEQ_MISC0_GDDR5_VALUE 5562#define MC_SEQ_MISC1 0xA81563#define MC_SEQ_RESERVE_M 0xA82564#define MC_PMG_CMD_EMRS 0xA83565 566#define MC_SEQ_IO_DEBUG_INDEX 0xA91567#define MC_SEQ_IO_DEBUG_DATA 0xA92568 569#define MC_SEQ_MISC5 0xA95570#define MC_SEQ_MISC6 0xA96571 572#define MC_SEQ_MISC7 0xA99573 574#define MC_SEQ_RAS_TIMING_LP 0xA9B575#define MC_SEQ_CAS_TIMING_LP 0xA9C576#define MC_SEQ_MISC_TIMING_LP 0xA9D577#define MC_SEQ_MISC_TIMING2_LP 0xA9E578#define MC_SEQ_WR_CTL_D0_LP 0xA9F579#define MC_SEQ_WR_CTL_D1_LP 0xAA0580#define MC_SEQ_PMG_CMD_EMRS_LP 0xAA1581#define MC_SEQ_PMG_CMD_MRS_LP 0xAA2582 583#define MC_PMG_CMD_MRS 0xAAB584 585#define MC_SEQ_RD_CTL_D0_LP 0xAC7586#define MC_SEQ_RD_CTL_D1_LP 0xAC8587 588#define MC_PMG_CMD_MRS1 0xAD1589#define MC_SEQ_PMG_CMD_MRS1_LP 0xAD2590#define MC_SEQ_PMG_TIMING_LP 0xAD3591 592#define MC_SEQ_WR_CTL_2 0xAD5593#define MC_SEQ_WR_CTL_2_LP 0xAD6594#define MC_PMG_CMD_MRS2 0xAD7595#define MC_SEQ_PMG_CMD_MRS2_LP 0xAD8596 597#define MCLK_PWRMGT_CNTL 0xAE8598# define DLL_SPEED(x) ((x) << 0)599# define DLL_SPEED_MASK (0x1f << 0)600# define DLL_READY (1 << 6)601# define MC_INT_CNTL (1 << 7)602# define MRDCK0_PDNB (1 << 8)603# define MRDCK1_PDNB (1 << 9)604# define MRDCK0_RESET (1 << 16)605# define MRDCK1_RESET (1 << 17)606# define DLL_READY_READ (1 << 24)607#define DLL_CNTL 0xAE9608# define MRDCK0_BYPASS (1 << 24)609# define MRDCK1_BYPASS (1 << 25)610 611#define MPLL_CNTL_MODE 0xAEC612# define MPLL_MCLK_SEL (1 << 11)613#define MPLL_FUNC_CNTL 0xAED614#define BWCTRL(x) ((x) << 20)615#define BWCTRL_MASK (0xff << 20)616#define MPLL_FUNC_CNTL_1 0xAEE617#define VCO_MODE(x) ((x) << 0)618#define VCO_MODE_MASK (3 << 0)619#define CLKFRAC(x) ((x) << 4)620#define CLKFRAC_MASK (0xfff << 4)621#define CLKF(x) ((x) << 16)622#define CLKF_MASK (0xfff << 16)623#define MPLL_FUNC_CNTL_2 0xAEF624#define MPLL_AD_FUNC_CNTL 0xAF0625#define YCLK_POST_DIV(x) ((x) << 0)626#define YCLK_POST_DIV_MASK (7 << 0)627#define MPLL_DQ_FUNC_CNTL 0xAF1628#define YCLK_SEL(x) ((x) << 4)629#define YCLK_SEL_MASK (1 << 4)630 631#define MPLL_SS1 0xAF3632#define CLKV(x) ((x) << 0)633#define CLKV_MASK (0x3ffffff << 0)634#define MPLL_SS2 0xAF4635#define CLKS(x) ((x) << 0)636#define CLKS_MASK (0xfff << 0)637 638#define HDP_HOST_PATH_CNTL 0xB00639#define CLOCK_GATING_DIS (1 << 23)640#define HDP_NONSURFACE_BASE 0xB01641#define HDP_NONSURFACE_INFO 0xB02642#define HDP_NONSURFACE_SIZE 0xB03643 644#define HDP_DEBUG0 0xBCC645 646#define HDP_ADDR_CONFIG 0xBD2647#define HDP_MISC_CNTL 0xBD3648#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)649#define HDP_MEM_POWER_LS 0xBD4650#define HDP_LS_ENABLE (1 << 0)651 652#define ATC_MISC_CG 0xCD4653 654#define IH_RB_CNTL 0xF80655# define IH_RB_ENABLE (1 << 0)656# define IH_IB_SIZE(x) ((x) << 1) /* log2 */657# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)658# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)659# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */660# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)661# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)662#define IH_RB_BASE 0xF81663#define IH_RB_RPTR 0xF82664#define IH_RB_WPTR 0xF83665# define RB_OVERFLOW (1 << 0)666# define WPTR_OFFSET_MASK 0x3fffc667#define IH_RB_WPTR_ADDR_HI 0xF84668#define IH_RB_WPTR_ADDR_LO 0xF85669#define IH_CNTL 0xF86670# define ENABLE_INTR (1 << 0)671# define IH_MC_SWAP(x) ((x) << 1)672# define IH_MC_SWAP_NONE 0673# define IH_MC_SWAP_16BIT 1674# define IH_MC_SWAP_32BIT 2675# define IH_MC_SWAP_64BIT 3676# define RPTR_REARM (1 << 4)677# define MC_WRREQ_CREDIT(x) ((x) << 15)678# define MC_WR_CLEAN_CNT(x) ((x) << 20)679# define MC_VMID(x) ((x) << 25)680 681#define CONFIG_MEMSIZE 0x150A682 683#define INTERRUPT_CNTL 0x151A684# define IH_DUMMY_RD_OVERRIDE (1 << 0)685# define IH_DUMMY_RD_EN (1 << 1)686# define IH_REQ_NONSNOOP_EN (1 << 3)687# define GEN_IH_INT_EN (1 << 8)688#define INTERRUPT_CNTL2 0x151B689 690#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x1520691 692#define BIF_FB_EN 0x1524693#define FB_READ_EN (1 << 0)694#define FB_WRITE_EN (1 << 1)695 696#define HDP_REG_COHERENCY_FLUSH_CNTL 0x1528697 698/* DCE6 ELD audio interface */699#define AZ_F0_CODEC_ENDPOINT_INDEX 0x1780700# define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0)701# define AZ_ENDPOINT_REG_WRITE_EN (1 << 8)702#define AZ_F0_CODEC_ENDPOINT_DATA 0x1781703 704#define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25705#define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0)706#define SPEAKER_ALLOCATION_MASK (0x7f << 0)707#define SPEAKER_ALLOCATION_SHIFT 0708#define HDMI_CONNECTION (1 << 16)709#define DP_CONNECTION (1 << 17)710 711#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */712#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */713#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */714#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2B /* MP3 */715#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2C /* MPEG2 */716#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2D /* AAC */717#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2E /* DTS */718#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2F /* ATRAC */719#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (default) */720#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 /* Dolby Digital */721#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */722#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */723#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 /* DTS */724#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 /* WMA Pro */725# define MAX_CHANNELS(x) (((x) & 0x7) << 0)726/* max channels minus one. 7 = 8 channels */727# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)728# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)729# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */730/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO731 * bit0 = 32 kHz732 * bit1 = 44.1 kHz733 * bit2 = 48 kHz734 * bit3 = 88.2 kHz735 * bit4 = 96 kHz736 * bit5 = 176.4 kHz737 * bit6 = 192 kHz738 */739 740#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37741# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)742# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)743/* VIDEO_LIPSYNC, AUDIO_LIPSYNC744 * 0 = invalid745 * x = legal delay value746 * 255 = sync not supported747 */748#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38749# define HBR_CAPABLE (1 << 0) /* enabled by default */750 751#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a752# define MANUFACTURER_ID(x) (((x) & 0xffff) << 0)753# define PRODUCT_ID(x) (((x) & 0xffff) << 16)754#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b755# define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0)756#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c757# define PORT_ID0(x) (((x) & 0xffffffff) << 0)758#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d759# define PORT_ID1(x) (((x) & 0xffffffff) << 0)760#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e761# define DESCRIPTION0(x) (((x) & 0xff) << 0)762# define DESCRIPTION1(x) (((x) & 0xff) << 8)763# define DESCRIPTION2(x) (((x) & 0xff) << 16)764# define DESCRIPTION3(x) (((x) & 0xff) << 24)765#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f766# define DESCRIPTION4(x) (((x) & 0xff) << 0)767# define DESCRIPTION5(x) (((x) & 0xff) << 8)768# define DESCRIPTION6(x) (((x) & 0xff) << 16)769# define DESCRIPTION7(x) (((x) & 0xff) << 24)770#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40771# define DESCRIPTION8(x) (((x) & 0xff) << 0)772# define DESCRIPTION9(x) (((x) & 0xff) << 8)773# define DESCRIPTION10(x) (((x) & 0xff) << 16)774# define DESCRIPTION11(x) (((x) & 0xff) << 24)775#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41776# define DESCRIPTION12(x) (((x) & 0xff) << 0)777# define DESCRIPTION13(x) (((x) & 0xff) << 8)778# define DESCRIPTION14(x) (((x) & 0xff) << 16)779# define DESCRIPTION15(x) (((x) & 0xff) << 24)780#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42781# define DESCRIPTION16(x) (((x) & 0xff) << 0)782# define DESCRIPTION17(x) (((x) & 0xff) << 8)783 784#define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54785# define AUDIO_ENABLED (1 << 31)786 787#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56788#define PORT_CONNECTIVITY_MASK (3 << 30)789#define PORT_CONNECTIVITY_SHIFT 30790 791#define DC_LB_MEMORY_SPLIT 0x1AC3792#define DC_LB_MEMORY_CONFIG(x) ((x) << 20)793 794#define PRIORITY_A_CNT 0x1AC6795#define PRIORITY_MARK_MASK 0x7fff796#define PRIORITY_OFF (1 << 16)797#define PRIORITY_ALWAYS_ON (1 << 20)798#define PRIORITY_B_CNT 0x1AC7799 800#define DPG_PIPE_ARBITRATION_CONTROL3 0x1B32801# define LATENCY_WATERMARK_MASK(x) ((x) << 16)802#define DPG_PIPE_LATENCY_CONTROL 0x1B33803# define LATENCY_LOW_WATERMARK(x) ((x) << 0)804# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)805 806/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */807#define VLINE_STATUS 0x1AEE808# define VLINE_OCCURRED (1 << 0)809# define VLINE_ACK (1 << 4)810# define VLINE_STAT (1 << 12)811# define VLINE_INTERRUPT (1 << 16)812# define VLINE_INTERRUPT_TYPE (1 << 17)813/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */814#define VBLANK_STATUS 0x1AEF815# define VBLANK_OCCURRED (1 << 0)816# define VBLANK_ACK (1 << 4)817# define VBLANK_STAT (1 << 12)818# define VBLANK_INTERRUPT (1 << 16)819# define VBLANK_INTERRUPT_TYPE (1 << 17)820 821/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */822#define INT_MASK 0x1AD0823# define VBLANK_INT_MASK (1 << 0)824# define VLINE_INT_MASK (1 << 4)825 826#define DISP_INTERRUPT_STATUS 0x183D827# define LB_D1_VLINE_INTERRUPT (1 << 2)828# define LB_D1_VBLANK_INTERRUPT (1 << 3)829# define DC_HPD1_INTERRUPT (1 << 17)830# define DC_HPD1_RX_INTERRUPT (1 << 18)831# define DACA_AUTODETECT_INTERRUPT (1 << 22)832# define DACB_AUTODETECT_INTERRUPT (1 << 23)833# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)834# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)835#define DISP_INTERRUPT_STATUS_CONTINUE 0x183E836# define LB_D2_VLINE_INTERRUPT (1 << 2)837# define LB_D2_VBLANK_INTERRUPT (1 << 3)838# define DC_HPD2_INTERRUPT (1 << 17)839# define DC_HPD2_RX_INTERRUPT (1 << 18)840# define DISP_TIMER_INTERRUPT (1 << 24)841#define DISP_INTERRUPT_STATUS_CONTINUE2 0x183F842# define LB_D3_VLINE_INTERRUPT (1 << 2)843# define LB_D3_VBLANK_INTERRUPT (1 << 3)844# define DC_HPD3_INTERRUPT (1 << 17)845# define DC_HPD3_RX_INTERRUPT (1 << 18)846#define DISP_INTERRUPT_STATUS_CONTINUE3 0x1840847# define LB_D4_VLINE_INTERRUPT (1 << 2)848# define LB_D4_VBLANK_INTERRUPT (1 << 3)849# define DC_HPD4_INTERRUPT (1 << 17)850# define DC_HPD4_RX_INTERRUPT (1 << 18)851#define DISP_INTERRUPT_STATUS_CONTINUE4 0x1853852# define LB_D5_VLINE_INTERRUPT (1 << 2)853# define LB_D5_VBLANK_INTERRUPT (1 << 3)854# define DC_HPD5_INTERRUPT (1 << 17)855# define DC_HPD5_RX_INTERRUPT (1 << 18)856#define DISP_INTERRUPT_STATUS_CONTINUE5 0x1854857# define LB_D6_VLINE_INTERRUPT (1 << 2)858# define LB_D6_VBLANK_INTERRUPT (1 << 3)859# define DC_HPD6_INTERRUPT (1 << 17)860# define DC_HPD6_RX_INTERRUPT (1 << 18)861 862/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */863#define GRPH_INT_STATUS 0x1A16864# define GRPH_PFLIP_INT_OCCURRED (1 << 0)865# define GRPH_PFLIP_INT_CLEAR (1 << 8)866/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */867#define GRPH_INT_CONTROL 0x1A17868# define GRPH_PFLIP_INT_MASK (1 << 0)869# define GRPH_PFLIP_INT_TYPE (1 << 8)870 871#define DAC_AUTODETECT_INT_CONTROL 0x19F2872 873#define DC_HPD1_INT_STATUS 0x1807874#define DC_HPD2_INT_STATUS 0x180A875#define DC_HPD3_INT_STATUS 0x180D876#define DC_HPD4_INT_STATUS 0x1810877#define DC_HPD5_INT_STATUS 0x1813878#define DC_HPD6_INT_STATUS 0x1816879# define DC_HPDx_INT_STATUS (1 << 0)880# define DC_HPDx_SENSE (1 << 1)881# define DC_HPDx_RX_INT_STATUS (1 << 8)882 883#define DC_HPD1_INT_CONTROL 0x1808884#define DC_HPD2_INT_CONTROL 0x180B885#define DC_HPD3_INT_CONTROL 0x180E886#define DC_HPD4_INT_CONTROL 0x1811887#define DC_HPD5_INT_CONTROL 0x1814888#define DC_HPD6_INT_CONTROL 0x1817889# define DC_HPDx_INT_ACK (1 << 0)890# define DC_HPDx_INT_POLARITY (1 << 8)891# define DC_HPDx_INT_EN (1 << 16)892# define DC_HPDx_RX_INT_ACK (1 << 20)893# define DC_HPDx_RX_INT_EN (1 << 24)894 895#define DC_HPD1_CONTROL 0x1809896#define DC_HPD2_CONTROL 0x180C897#define DC_HPD3_CONTROL 0x180F898#define DC_HPD4_CONTROL 0x1812899#define DC_HPD5_CONTROL 0x1815900#define DC_HPD6_CONTROL 0x1818901# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)902# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)903# define DC_HPDx_EN (1 << 28)904 905#define DPG_PIPE_STUTTER_CONTROL 0x1B35906# define STUTTER_ENABLE (1 << 0)907 908/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */909#define CRTC_STATUS_FRAME_COUNT 0x1BA6910 911/* Audio clocks */912#define DCCG_AUDIO_DTO_SOURCE 0x05ac913# define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */914# define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */915 916#define DCCG_AUDIO_DTO0_PHASE 0x05b0917#define DCCG_AUDIO_DTO0_MODULE 0x05b4918#define DCCG_AUDIO_DTO1_PHASE 0x05c0919#define DCCG_AUDIO_DTO1_MODULE 0x05c4920 921#define AFMT_AUDIO_SRC_CONTROL 0x1c4f922#define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0)923/* AFMT_AUDIO_SRC_SELECT924 * 0 = stream0925 * 1 = stream1926 * 2 = stream2927 * 3 = stream3928 * 4 = stream4929 * 5 = stream5930 */931 932#define GRBM_CNTL 0x2000933#define GRBM_READ_TIMEOUT(x) ((x) << 0)934 935#define GRBM_STATUS2 0x2002936#define RLC_RQ_PENDING (1 << 0)937#define RLC_BUSY (1 << 8)938#define TC_BUSY (1 << 9)939 940#define GRBM_STATUS 0x2004941#define CMDFIFO_AVAIL_MASK 0x0000000F942#define RING2_RQ_PENDING (1 << 4)943#define SRBM_RQ_PENDING (1 << 5)944#define RING1_RQ_PENDING (1 << 6)945#define CF_RQ_PENDING (1 << 7)946#define PF_RQ_PENDING (1 << 8)947#define GDS_DMA_RQ_PENDING (1 << 9)948#define GRBM_EE_BUSY (1 << 10)949#define DB_CLEAN (1 << 12)950#define CB_CLEAN (1 << 13)951#define TA_BUSY (1 << 14)952#define GDS_BUSY (1 << 15)953#define VGT_BUSY (1 << 17)954#define IA_BUSY_NO_DMA (1 << 18)955#define IA_BUSY (1 << 19)956#define SX_BUSY (1 << 20)957#define SPI_BUSY (1 << 22)958#define BCI_BUSY (1 << 23)959#define SC_BUSY (1 << 24)960#define PA_BUSY (1 << 25)961#define DB_BUSY (1 << 26)962#define CP_COHERENCY_BUSY (1 << 28)963#define CP_BUSY (1 << 29)964#define CB_BUSY (1 << 30)965#define GUI_ACTIVE (1 << 31)966#define GRBM_STATUS_SE0 0x2005967#define GRBM_STATUS_SE1 0x2006968#define SE_DB_CLEAN (1 << 1)969#define SE_CB_CLEAN (1 << 2)970#define SE_BCI_BUSY (1 << 22)971#define SE_VGT_BUSY (1 << 23)972#define SE_PA_BUSY (1 << 24)973#define SE_TA_BUSY (1 << 25)974#define SE_SX_BUSY (1 << 26)975#define SE_SPI_BUSY (1 << 27)976#define SE_SC_BUSY (1 << 29)977#define SE_DB_BUSY (1 << 30)978#define SE_CB_BUSY (1 << 31)979 980#define GRBM_SOFT_RESET 0x2008981#define SOFT_RESET_CP (1 << 0)982#define SOFT_RESET_CB (1 << 1)983#define SOFT_RESET_RLC (1 << 2)984#define SOFT_RESET_DB (1 << 3)985#define SOFT_RESET_GDS (1 << 4)986#define SOFT_RESET_PA (1 << 5)987#define SOFT_RESET_SC (1 << 6)988#define SOFT_RESET_BCI (1 << 7)989#define SOFT_RESET_SPI (1 << 8)990#define SOFT_RESET_SX (1 << 10)991#define SOFT_RESET_TC (1 << 11)992#define SOFT_RESET_TA (1 << 12)993#define SOFT_RESET_VGT (1 << 14)994#define SOFT_RESET_IA (1 << 15)995 996#define GRBM_GFX_INDEX 0x200B997#define INSTANCE_INDEX(x) ((x) << 0)998#define SH_INDEX(x) ((x) << 8)999#define SE_INDEX(x) ((x) << 16)1000#define SH_BROADCAST_WRITES (1 << 29)1001#define INSTANCE_BROADCAST_WRITES (1 << 30)1002#define SE_BROADCAST_WRITES (1 << 31)1003 1004#define GRBM_INT_CNTL 0x20181005# define RDERR_INT_ENABLE (1 << 0)1006# define GUI_IDLE_INT_ENABLE (1 << 19)1007 1008#define CP_STRMOUT_CNTL 0x213F1009#define SCRATCH_REG0 0x21401010#define SCRATCH_REG1 0x21411011#define SCRATCH_REG2 0x21421012#define SCRATCH_REG3 0x21431013#define SCRATCH_REG4 0x21441014#define SCRATCH_REG5 0x21451015#define SCRATCH_REG6 0x21461016#define SCRATCH_REG7 0x21471017 1018#define SCRATCH_UMSK 0x21501019#define SCRATCH_ADDR 0x21511020 1021#define CP_SEM_WAIT_TIMER 0x216F1022 1023#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x21721024 1025#define CP_ME_CNTL 0x21B61026#define CP_CE_HALT (1 << 24)1027#define CP_PFP_HALT (1 << 26)1028#define CP_ME_HALT (1 << 28)1029 1030#define CP_COHER_CNTL2 0x217A1031 1032#define CP_RB2_RPTR 0x21BE1033#define CP_RB1_RPTR 0x21BF1034#define CP_RB0_RPTR 0x21C01035#define CP_RB_WPTR_DELAY 0x21C11036 1037#define CP_QUEUE_THRESHOLDS 0x21D81038#define ROQ_IB1_START(x) ((x) << 0)1039#define ROQ_IB2_START(x) ((x) << 8)1040#define CP_MEQ_THRESHOLDS 0x21D91041#define MEQ1_START(x) ((x) << 0)1042#define MEQ2_START(x) ((x) << 8)1043 1044#define CP_PERFMON_CNTL 0x21FF1045 1046#define VGT_VTX_VECT_EJECT_REG 0x222C1047 1048#define VGT_CACHE_INVALIDATION 0x22311049#define CACHE_INVALIDATION(x) ((x) << 0)1050#define VC_ONLY 01051#define TC_ONLY 11052#define VC_AND_TC 21053#define AUTO_INVLD_EN(x) ((x) << 6)1054#define NO_AUTO 01055#define ES_AUTO 11056#define GS_AUTO 21057#define ES_AND_GS_AUTO 31058#define VGT_ESGS_RING_SIZE 0x22321059#define VGT_GSVS_RING_SIZE 0x22331060 1061#define VGT_GS_VERTEX_REUSE 0x22351062 1063#define VGT_PRIMITIVE_TYPE 0x22561064#define VGT_INDEX_TYPE 0x22571065 1066#define VGT_NUM_INDICES 0x225C1067#define VGT_NUM_INSTANCES 0x225D1068 1069#define VGT_TF_RING_SIZE 0x22621070 1071#define VGT_HS_OFFCHIP_PARAM 0x226C1072 1073#define VGT_TF_MEMORY_BASE 0x226E1074 1075#define CC_GC_SHADER_ARRAY_CONFIG 0x226F1076#define INACTIVE_CUS_MASK 0xFFFF00001077#define INACTIVE_CUS_SHIFT 161078#define GC_USER_SHADER_ARRAY_CONFIG 0x22701079 1080#define PA_CL_ENHANCE 0x22851081#define CLIP_VTX_REORDER_ENA (1 << 0)1082#define NUM_CLIP_SEQ(x) ((x) << 1)1083 1084#define PA_SU_LINE_STIPPLE_VALUE 0x22981085 1086#define PA_SC_LINE_STIPPLE_STATE 0x22C41087 1088#define PA_SC_FORCE_EOV_MAX_CNTS 0x22C91089#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)1090#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)1091 1092#define PA_SC_FIFO_SIZE 0x22F31093#define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)1094#define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)1095#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)1096#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)1097 1098#define PA_SC_ENHANCE 0x22FC1099 1100#define SQ_CONFIG 0x23001101 1102#define SQC_CACHES 0x23021103 1104#define SQ_POWER_THROTTLE 0x23961105#define MIN_POWER(x) ((x) << 0)1106#define MIN_POWER_MASK (0x3fff << 0)1107#define MIN_POWER_SHIFT 01108#define MAX_POWER(x) ((x) << 16)1109#define MAX_POWER_MASK (0x3fff << 16)1110#define MAX_POWER_SHIFT 01111#define SQ_POWER_THROTTLE2 0x23971112#define MAX_POWER_DELTA(x) ((x) << 0)1113#define MAX_POWER_DELTA_MASK (0x3fff << 0)1114#define MAX_POWER_DELTA_SHIFT 01115#define STI_SIZE(x) ((x) << 16)1116#define STI_SIZE_MASK (0x3ff << 16)1117#define STI_SIZE_SHIFT 161118#define LTI_RATIO(x) ((x) << 27)1119#define LTI_RATIO_MASK (0xf << 27)1120#define LTI_RATIO_SHIFT 271121 1122#define SX_DEBUG_1 0x24181123 1124#define SPI_STATIC_THREAD_MGMT_1 0x24381125#define SPI_STATIC_THREAD_MGMT_2 0x24391126#define SPI_STATIC_THREAD_MGMT_3 0x243A1127#define SPI_PS_MAX_WAVE_ID 0x243B1128 1129#define SPI_CONFIG_CNTL 0x24401130 1131#define SPI_CONFIG_CNTL_1 0x244F1132#define VTX_DONE_DELAY(x) ((x) << 0)1133#define INTERP_ONE_PRIM_PER_ROW (1 << 4)1134 1135#define CGTS_TCC_DISABLE 0x24521136#define CGTS_USER_TCC_DISABLE 0x24531137#define TCC_DISABLE_MASK 0xFFFF00001138#define TCC_DISABLE_SHIFT 161139#define CGTS_SM_CTRL_REG 0x24541140#define OVERRIDE (1 << 21)1141#define LS_OVERRIDE (1 << 22)1142 1143#define SPI_LB_CU_MASK 0x24D51144 1145#define TA_CNTL_AUX 0x25421146 1147#define CC_RB_BACKEND_DISABLE 0x263D1148#define BACKEND_DISABLE(x) ((x) << 16)1149#define GB_ADDR_CONFIG 0x263E1150#define NUM_PIPES(x) ((x) << 0)1151#define NUM_PIPES_MASK 0x000000071152#define NUM_PIPES_SHIFT 01153#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)1154#define PIPE_INTERLEAVE_SIZE_MASK 0x000000701155#define PIPE_INTERLEAVE_SIZE_SHIFT 41156#define NUM_SHADER_ENGINES(x) ((x) << 12)1157#define NUM_SHADER_ENGINES_MASK 0x000030001158#define NUM_SHADER_ENGINES_SHIFT 121159#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)1160#define SHADER_ENGINE_TILE_SIZE_MASK 0x000700001161#define SHADER_ENGINE_TILE_SIZE_SHIFT 161162#define NUM_GPUS(x) ((x) << 20)1163#define NUM_GPUS_MASK 0x007000001164#define NUM_GPUS_SHIFT 201165#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)1166#define MULTI_GPU_TILE_SIZE_MASK 0x030000001167#define MULTI_GPU_TILE_SIZE_SHIFT 241168#define ROW_SIZE(x) ((x) << 28)1169#define ROW_SIZE_MASK 0x300000001170#define ROW_SIZE_SHIFT 281171 1172#define GB_TILE_MODE0 0x26441173# define MICRO_TILE_MODE(x) ((x) << 0)1174# define ADDR_SURF_DISPLAY_MICRO_TILING 01175# define ADDR_SURF_THIN_MICRO_TILING 11176# define ADDR_SURF_DEPTH_MICRO_TILING 21177# define ARRAY_MODE(x) ((x) << 2)1178# define ARRAY_LINEAR_GENERAL 01179# define ARRAY_LINEAR_ALIGNED 11180# define ARRAY_1D_TILED_THIN1 21181# define ARRAY_2D_TILED_THIN1 41182# define PIPE_CONFIG(x) ((x) << 6)1183# define ADDR_SURF_P2 01184# define ADDR_SURF_P4_8x16 41185# define ADDR_SURF_P4_16x16 51186# define ADDR_SURF_P4_16x32 61187# define ADDR_SURF_P4_32x32 71188# define ADDR_SURF_P8_16x16_8x16 81189# define ADDR_SURF_P8_16x32_8x16 91190# define ADDR_SURF_P8_32x32_8x16 101191# define ADDR_SURF_P8_16x32_16x16 111192# define ADDR_SURF_P8_32x32_16x16 121193# define ADDR_SURF_P8_32x32_16x32 131194# define ADDR_SURF_P8_32x64_32x32 141195# define TILE_SPLIT(x) ((x) << 11)1196# define ADDR_SURF_TILE_SPLIT_64B 01197# define ADDR_SURF_TILE_SPLIT_128B 11198# define ADDR_SURF_TILE_SPLIT_256B 21199# define ADDR_SURF_TILE_SPLIT_512B 31200# define ADDR_SURF_TILE_SPLIT_1KB 41201# define ADDR_SURF_TILE_SPLIT_2KB 51202# define ADDR_SURF_TILE_SPLIT_4KB 61203# define BANK_WIDTH(x) ((x) << 14)1204# define ADDR_SURF_BANK_WIDTH_1 01205# define ADDR_SURF_BANK_WIDTH_2 11206# define ADDR_SURF_BANK_WIDTH_4 21207# define ADDR_SURF_BANK_WIDTH_8 31208# define BANK_HEIGHT(x) ((x) << 16)1209# define ADDR_SURF_BANK_HEIGHT_1 01210# define ADDR_SURF_BANK_HEIGHT_2 11211# define ADDR_SURF_BANK_HEIGHT_4 21212# define ADDR_SURF_BANK_HEIGHT_8 31213# define MACRO_TILE_ASPECT(x) ((x) << 18)1214# define ADDR_SURF_MACRO_ASPECT_1 01215# define ADDR_SURF_MACRO_ASPECT_2 11216# define ADDR_SURF_MACRO_ASPECT_4 21217# define ADDR_SURF_MACRO_ASPECT_8 31218# define NUM_BANKS(x) ((x) << 20)1219# define ADDR_SURF_2_BANK 01220# define ADDR_SURF_4_BANK 11221# define ADDR_SURF_8_BANK 21222# define ADDR_SURF_16_BANK 31223#define GB_TILE_MODE1 0x26451224#define GB_TILE_MODE2 0x26461225#define GB_TILE_MODE3 0x26471226#define GB_TILE_MODE4 0x26481227#define GB_TILE_MODE5 0x26491228#define GB_TILE_MODE6 0x264a1229#define GB_TILE_MODE7 0x264b1230#define GB_TILE_MODE8 0x264c1231#define GB_TILE_MODE9 0x264d1232#define GB_TILE_MODE10 0x264e1233#define GB_TILE_MODE11 0x264f1234#define GB_TILE_MODE12 0x26501235#define GB_TILE_MODE13 0x26511236#define GB_TILE_MODE14 0x26521237#define GB_TILE_MODE15 0x26531238#define GB_TILE_MODE16 0x26541239#define GB_TILE_MODE17 0x26551240#define GB_TILE_MODE18 0x26561241#define GB_TILE_MODE19 0x26571242#define GB_TILE_MODE20 0x26581243#define GB_TILE_MODE21 0x26591244#define GB_TILE_MODE22 0x265a1245#define GB_TILE_MODE23 0x265b1246#define GB_TILE_MODE24 0x265c1247#define GB_TILE_MODE25 0x265d1248#define GB_TILE_MODE26 0x265e1249#define GB_TILE_MODE27 0x265f1250#define GB_TILE_MODE28 0x26601251#define GB_TILE_MODE29 0x26611252#define GB_TILE_MODE30 0x26621253#define GB_TILE_MODE31 0x26631254 1255#define CB_PERFCOUNTER0_SELECT0 0x26881256#define CB_PERFCOUNTER0_SELECT1 0x26891257#define CB_PERFCOUNTER1_SELECT0 0x268A1258#define CB_PERFCOUNTER1_SELECT1 0x268B1259#define CB_PERFCOUNTER2_SELECT0 0x268C1260#define CB_PERFCOUNTER2_SELECT1 0x268D1261#define CB_PERFCOUNTER3_SELECT0 0x268E1262#define CB_PERFCOUNTER3_SELECT1 0x268F1263 1264#define CB_CGTT_SCLK_CTRL 0x26981265 1266#define GC_USER_RB_BACKEND_DISABLE 0x26DF1267#define BACKEND_DISABLE_MASK 0x00FF00001268#define BACKEND_DISABLE_SHIFT 161269 1270#define TCP_CHAN_STEER_LO 0x2B031271#define TCP_CHAN_STEER_HI 0x2B941272 1273#define CP_RB0_BASE 0x30401274#define CP_RB0_CNTL 0x30411275#define RB_BUFSZ(x) ((x) << 0)1276#define RB_BLKSZ(x) ((x) << 8)1277#define BUF_SWAP_32BIT (2 << 16)1278#define RB_NO_UPDATE (1 << 27)1279#define RB_RPTR_WR_ENA (1 << 31)1280 1281#define CP_RB0_RPTR_ADDR 0x30431282#define CP_RB0_RPTR_ADDR_HI 0x30441283#define CP_RB0_WPTR 0x30451284 1285#define CP_PFP_UCODE_ADDR 0x30541286#define CP_PFP_UCODE_DATA 0x30551287#define CP_ME_RAM_RADDR 0x30561288#define CP_ME_RAM_WADDR 0x30571289#define CP_ME_RAM_DATA 0x30581290 1291#define CP_CE_UCODE_ADDR 0x305A1292#define CP_CE_UCODE_DATA 0x305B1293 1294#define CP_RB1_BASE 0x30601295#define CP_RB1_CNTL 0x30611296#define CP_RB1_RPTR_ADDR 0x30621297#define CP_RB1_RPTR_ADDR_HI 0x30631298#define CP_RB1_WPTR 0x30641299#define CP_RB2_BASE 0x30651300#define CP_RB2_CNTL 0x30661301#define CP_RB2_RPTR_ADDR 0x30671302#define CP_RB2_RPTR_ADDR_HI 0x30681303#define CP_RB2_WPTR 0x30691304#define CP_INT_CNTL_RING0 0x306A1305#define CP_INT_CNTL_RING1 0x306B1306#define CP_INT_CNTL_RING2 0x306C1307# define CNTX_BUSY_INT_ENABLE (1 << 19)1308# define CNTX_EMPTY_INT_ENABLE (1 << 20)1309# define WAIT_MEM_SEM_INT_ENABLE (1 << 21)1310# define TIME_STAMP_INT_ENABLE (1 << 26)1311# define CP_RINGID2_INT_ENABLE (1 << 29)1312# define CP_RINGID1_INT_ENABLE (1 << 30)1313# define CP_RINGID0_INT_ENABLE (1 << 31)1314#define CP_INT_STATUS_RING0 0x306D1315#define CP_INT_STATUS_RING1 0x306E1316#define CP_INT_STATUS_RING2 0x306F1317# define WAIT_MEM_SEM_INT_STAT (1 << 21)1318# define TIME_STAMP_INT_STAT (1 << 26)1319# define CP_RINGID2_INT_STAT (1 << 29)1320# define CP_RINGID1_INT_STAT (1 << 30)1321# define CP_RINGID0_INT_STAT (1 << 31)1322 1323#define CP_MEM_SLP_CNTL 0x30791324# define CP_MEM_LS_EN (1 << 0)1325 1326#define CP_DEBUG 0x307F1327 1328#define RLC_CNTL 0x30C01329# define RLC_ENABLE (1 << 0)1330#define RLC_RL_BASE 0x30C11331#define RLC_RL_SIZE 0x30C21332#define RLC_LB_CNTL 0x30C31333# define LOAD_BALANCE_ENABLE (1 << 0)1334#define RLC_SAVE_AND_RESTORE_BASE 0x30C41335#define RLC_LB_CNTR_MAX 0x30C51336#define RLC_LB_CNTR_INIT 0x30C61337 1338#define RLC_CLEAR_STATE_RESTORE_BASE 0x30C81339 1340#define RLC_UCODE_ADDR 0x30CB1341#define RLC_UCODE_DATA 0x30CC1342 1343#define RLC_GPU_CLOCK_COUNT_LSB 0x30CE1344#define RLC_GPU_CLOCK_COUNT_MSB 0x30CF1345#define RLC_CAPTURE_GPU_CLOCK_COUNT 0x30D01346#define RLC_MC_CNTL 0x30D11347#define RLC_UCODE_CNTL 0x30D21348#define RLC_STAT 0x30D31349# define RLC_BUSY_STATUS (1 << 0)1350# define GFX_POWER_STATUS (1 << 1)1351# define GFX_CLOCK_STATUS (1 << 2)1352# define GFX_LS_STATUS (1 << 3)1353 1354#define RLC_PG_CNTL 0x30D71355# define GFX_PG_ENABLE (1 << 0)1356# define GFX_PG_SRC (1 << 1)1357 1358#define RLC_CGTT_MGCG_OVERRIDE 0x31001359#define RLC_CGCG_CGLS_CTRL 0x31011360# define CGCG_EN (1 << 0)1361# define CGLS_EN (1 << 1)1362 1363#define RLC_TTOP_D 0x31051364# define RLC_PUD(x) ((x) << 0)1365# define RLC_PUD_MASK (0xff << 0)1366# define RLC_PDD(x) ((x) << 8)1367# define RLC_PDD_MASK (0xff << 8)1368# define RLC_TTPD(x) ((x) << 16)1369# define RLC_TTPD_MASK (0xff << 16)1370# define RLC_MSD(x) ((x) << 24)1371# define RLC_MSD_MASK (0xff << 24)1372 1373#define RLC_LB_INIT_CU_MASK 0x31071374 1375#define RLC_PG_AO_CU_MASK 0x310B1376#define RLC_MAX_PG_CU 0x310C1377# define MAX_PU_CU(x) ((x) << 0)1378# define MAX_PU_CU_MASK (0xff << 0)1379#define RLC_AUTO_PG_CTRL 0x310C1380# define AUTO_PG_EN (1 << 0)1381# define GRBM_REG_SGIT(x) ((x) << 3)1382# define GRBM_REG_SGIT_MASK (0xffff << 3)1383# define PG_AFTER_GRBM_REG_ST(x) ((x) << 19)1384# define PG_AFTER_GRBM_REG_ST_MASK (0x1fff << 19)1385 1386#define RLC_SERDES_WR_MASTER_MASK_0 0x31151387#define RLC_SERDES_WR_MASTER_MASK_1 0x31161388#define RLC_SERDES_WR_CTRL 0x31171389 1390#define RLC_SERDES_MASTER_BUSY_0 0x31191391#define RLC_SERDES_MASTER_BUSY_1 0x311A1392 1393#define RLC_GCPM_GENERAL_3 0x311E1394 1395#define DB_RENDER_CONTROL 0xA0001396 1397#define DB_DEPTH_INFO 0xA00F1398 1399#define PA_SC_RASTER_CONFIG 0xA0D41400# define RB_MAP_PKR0(x) ((x) << 0)1401# define RB_MAP_PKR0_MASK (0x3 << 0)1402# define RB_MAP_PKR1(x) ((x) << 2)1403# define RB_MAP_PKR1_MASK (0x3 << 2)1404# define RASTER_CONFIG_RB_MAP_0 01405# define RASTER_CONFIG_RB_MAP_1 11406# define RASTER_CONFIG_RB_MAP_2 21407# define RASTER_CONFIG_RB_MAP_3 31408# define RB_XSEL2(x) ((x) << 4)1409# define RB_XSEL2_MASK (0x3 << 4)1410# define RB_XSEL (1 << 6)1411# define RB_YSEL (1 << 7)1412# define PKR_MAP(x) ((x) << 8)1413# define PKR_MAP_MASK (0x3 << 8)1414# define RASTER_CONFIG_PKR_MAP_0 01415# define RASTER_CONFIG_PKR_MAP_1 11416# define RASTER_CONFIG_PKR_MAP_2 21417# define RASTER_CONFIG_PKR_MAP_3 31418# define PKR_XSEL(x) ((x) << 10)1419# define PKR_XSEL_MASK (0x3 << 10)1420# define PKR_YSEL(x) ((x) << 12)1421# define PKR_YSEL_MASK (0x3 << 12)1422# define SC_MAP(x) ((x) << 16)1423# define SC_MAP_MASK (0x3 << 16)1424# define SC_XSEL(x) ((x) << 18)1425# define SC_XSEL_MASK (0x3 << 18)1426# define SC_YSEL(x) ((x) << 20)1427# define SC_YSEL_MASK (0x3 << 20)1428# define SE_MAP(x) ((x) << 24)1429# define SE_MAP_MASK (0x3 << 24)1430# define RASTER_CONFIG_SE_MAP_0 01431# define RASTER_CONFIG_SE_MAP_1 11432# define RASTER_CONFIG_SE_MAP_2 21433# define RASTER_CONFIG_SE_MAP_3 31434# define SE_XSEL(x) ((x) << 26)1435# define SE_XSEL_MASK (0x3 << 26)1436# define SE_YSEL(x) ((x) << 28)1437# define SE_YSEL_MASK (0x3 << 28)1438 1439 1440#define VGT_EVENT_INITIATOR 0xA2A41441# define SAMPLE_STREAMOUTSTATS1 (1 << 0)1442# define SAMPLE_STREAMOUTSTATS2 (2 << 0)1443# define SAMPLE_STREAMOUTSTATS3 (3 << 0)1444# define CACHE_FLUSH_TS (4 << 0)1445# define CACHE_FLUSH (6 << 0)1446# define CS_PARTIAL_FLUSH (7 << 0)1447# define VGT_STREAMOUT_RESET (10 << 0)1448# define END_OF_PIPE_INCR_DE (11 << 0)1449# define END_OF_PIPE_IB_END (12 << 0)1450# define RST_PIX_CNT (13 << 0)1451# define VS_PARTIAL_FLUSH (15 << 0)1452# define PS_PARTIAL_FLUSH (16 << 0)1453# define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)1454# define ZPASS_DONE (21 << 0)1455# define CACHE_FLUSH_AND_INV_EVENT (22 << 0)1456# define PERFCOUNTER_START (23 << 0)1457# define PERFCOUNTER_STOP (24 << 0)1458# define PIPELINESTAT_START (25 << 0)1459# define PIPELINESTAT_STOP (26 << 0)1460# define PERFCOUNTER_SAMPLE (27 << 0)1461# define SAMPLE_PIPELINESTAT (30 << 0)1462# define SAMPLE_STREAMOUTSTATS (32 << 0)1463# define RESET_VTX_CNT (33 << 0)1464# define VGT_FLUSH (36 << 0)1465# define BOTTOM_OF_PIPE_TS (40 << 0)1466# define DB_CACHE_FLUSH_AND_INV (42 << 0)1467# define FLUSH_AND_INV_DB_DATA_TS (43 << 0)1468# define FLUSH_AND_INV_DB_META (44 << 0)1469# define FLUSH_AND_INV_CB_DATA_TS (45 << 0)1470# define FLUSH_AND_INV_CB_META (46 << 0)1471# define CS_DONE (47 << 0)1472# define PS_DONE (48 << 0)1473# define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)1474# define THREAD_TRACE_START (51 << 0)1475# define THREAD_TRACE_STOP (52 << 0)1476# define THREAD_TRACE_FLUSH (54 << 0)1477# define THREAD_TRACE_FINISH (55 << 0)1478 1479/* PIF PHY0 registers idx/data 0x8/0xc */1480#define PB0_PIF_CNTL 0x101481# define LS2_EXIT_TIME(x) ((x) << 17)1482# define LS2_EXIT_TIME_MASK (0x7 << 17)1483# define LS2_EXIT_TIME_SHIFT 171484#define PB0_PIF_PAIRING 0x111485# define MULTI_PIF (1 << 25)1486#define PB0_PIF_PWRDOWN_0 0x121487# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)1488# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)1489# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 71490# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)1491# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)1492# define PLL_POWER_STATE_IN_OFF_0_SHIFT 101493# define PLL_RAMP_UP_TIME_0(x) ((x) << 24)1494# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)1495# define PLL_RAMP_UP_TIME_0_SHIFT 241496#define PB0_PIF_PWRDOWN_1 0x131497# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)1498# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)1499# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 71500# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)1501# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)1502# define PLL_POWER_STATE_IN_OFF_1_SHIFT 101503# define PLL_RAMP_UP_TIME_1(x) ((x) << 24)1504# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)1505# define PLL_RAMP_UP_TIME_1_SHIFT 241506 1507#define PB0_PIF_PWRDOWN_2 0x171508# define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7)1509# define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7)1510# define PLL_POWER_STATE_IN_TXS2_2_SHIFT 71511# define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10)1512# define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10)1513# define PLL_POWER_STATE_IN_OFF_2_SHIFT 101514# define PLL_RAMP_UP_TIME_2(x) ((x) << 24)1515# define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24)1516# define PLL_RAMP_UP_TIME_2_SHIFT 241517#define PB0_PIF_PWRDOWN_3 0x181518# define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7)1519# define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7)1520# define PLL_POWER_STATE_IN_TXS2_3_SHIFT 71521# define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10)1522# define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10)1523# define PLL_POWER_STATE_IN_OFF_3_SHIFT 101524# define PLL_RAMP_UP_TIME_3(x) ((x) << 24)1525# define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24)1526# define PLL_RAMP_UP_TIME_3_SHIFT 241527/* PIF PHY1 registers idx/data 0x10/0x14 */1528#define PB1_PIF_CNTL 0x101529#define PB1_PIF_PAIRING 0x111530#define PB1_PIF_PWRDOWN_0 0x121531#define PB1_PIF_PWRDOWN_1 0x131532 1533#define PB1_PIF_PWRDOWN_2 0x171534#define PB1_PIF_PWRDOWN_3 0x181535/* PCIE registers idx/data 0x30/0x34 */1536#define PCIE_CNTL2 0x1c /* PCIE */1537# define SLV_MEM_LS_EN (1 << 16)1538# define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)1539# define MST_MEM_LS_EN (1 << 18)1540# define REPLAY_MEM_LS_EN (1 << 19)1541#define PCIE_LC_STATUS1 0x28 /* PCIE */1542# define LC_REVERSE_RCVR (1 << 0)1543# define LC_REVERSE_XMIT (1 << 1)1544# define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)1545# define LC_OPERATING_LINK_WIDTH_SHIFT 21546# define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)1547# define LC_DETECTED_LINK_WIDTH_SHIFT 51548 1549#define PCIE_P_CNTL 0x40 /* PCIE */1550# define P_IGNORE_EDB_ERR (1 << 6)1551 1552/* PCIE PORT registers idx/data 0x38/0x3c */1553#define PCIE_LC_CNTL 0xa01554# define LC_L0S_INACTIVITY(x) ((x) << 8)1555# define LC_L0S_INACTIVITY_MASK (0xf << 8)1556# define LC_L0S_INACTIVITY_SHIFT 81557# define LC_L1_INACTIVITY(x) ((x) << 12)1558# define LC_L1_INACTIVITY_MASK (0xf << 12)1559# define LC_L1_INACTIVITY_SHIFT 121560# define LC_PMI_TO_L1_DIS (1 << 16)1561# define LC_ASPM_TO_L1_DIS (1 << 24)1562#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */1563# define LC_LINK_WIDTH_SHIFT 01564# define LC_LINK_WIDTH_MASK 0x71565# define LC_LINK_WIDTH_X0 01566# define LC_LINK_WIDTH_X1 11567# define LC_LINK_WIDTH_X2 21568# define LC_LINK_WIDTH_X4 31569# define LC_LINK_WIDTH_X8 41570# define LC_LINK_WIDTH_X16 61571# define LC_LINK_WIDTH_RD_SHIFT 41572# define LC_LINK_WIDTH_RD_MASK 0x701573# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)1574# define LC_RECONFIG_NOW (1 << 8)1575# define LC_RENEGOTIATION_SUPPORT (1 << 9)1576# define LC_RENEGOTIATE_EN (1 << 10)1577# define LC_SHORT_RECONFIG_EN (1 << 11)1578# define LC_UPCONFIGURE_SUPPORT (1 << 12)1579# define LC_UPCONFIGURE_DIS (1 << 13)1580# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)1581# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)1582# define LC_DYN_LANES_PWR_STATE_SHIFT 211583#define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */1584# define LC_XMIT_N_FTS(x) ((x) << 0)1585# define LC_XMIT_N_FTS_MASK (0xff << 0)1586# define LC_XMIT_N_FTS_SHIFT 01587# define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)1588# define LC_N_FTS_MASK (0xff << 24)1589#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */1590# define LC_GEN2_EN_STRAP (1 << 0)1591# define LC_GEN3_EN_STRAP (1 << 1)1592# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)1593# define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)1594# define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 31595# define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)1596# define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)1597# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)1598# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)1599# define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)1600# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)1601# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 101602# define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */1603# define LC_CURRENT_DATA_RATE_SHIFT 131604# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)1605# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)1606# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)1607# define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)1608# define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)1609 1610#define PCIE_LC_CNTL2 0xb11611# define LC_ALLOW_PDWN_IN_L1 (1 << 17)1612# define LC_ALLOW_PDWN_IN_L23 (1 << 18)1613 1614#define PCIE_LC_CNTL3 0xb5 /* PCIE_P */1615# define LC_GO_TO_RECOVERY (1 << 30)1616#define PCIE_LC_CNTL4 0xb6 /* PCIE_P */1617# define LC_REDO_EQ (1 << 5)1618# define LC_SET_QUIESCE (1 << 13)1619 1620/*1621 * UVD1622 */1623#define UVD_UDEC_ADDR_CONFIG 0x3bd31624#define UVD_UDEC_DB_ADDR_CONFIG 0x3bd41625#define UVD_UDEC_DBW_ADDR_CONFIG 0x3bd51626#define UVD_RBC_RB_RPTR 0x3da41627#define UVD_RBC_RB_WPTR 0x3da51628#define UVD_STATUS 0x3daf1629 1630#define UVD_CGC_CTRL 0x3dc21631# define DCM (1 << 0)1632# define CG_DT(x) ((x) << 2)1633# define CG_DT_MASK (0xf << 2)1634# define CLK_OD(x) ((x) << 6)1635# define CLK_OD_MASK (0x1f << 6)1636 1637 /* UVD CTX indirect */1638#define UVD_CGC_MEM_CTRL 0xC01639#define UVD_CGC_CTRL2 0xC11640# define DYN_OR_EN (1 << 0)1641# define DYN_RR_EN (1 << 1)1642# define G_DIV_ID(x) ((x) << 2)1643# define G_DIV_ID_MASK (0x7 << 2)1644 1645/*1646 * PM41647 */1648#define PACKET_TYPE0 01649#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \1650 ((reg) & 0xFFFF) | \1651 ((n) & 0x3FFF) << 16)1652#define CP_PACKET2 0x800000001653#define PACKET2_PAD_SHIFT 01654#define PACKET2_PAD_MASK (0x3fffffff << 0)1655 1656#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))1657#define RADEON_PACKET_TYPE3 31658#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \1659 (((op) & 0xFF) << 8) | \1660 ((n) & 0x3FFF) << 16)1661 1662#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)1663 1664/* Packet 3 types */1665#define PACKET3_NOP 0x101666#define PACKET3_SET_BASE 0x111667#define PACKET3_BASE_INDEX(x) ((x) << 0)1668#define GDS_PARTITION_BASE 21669#define CE_PARTITION_BASE 31670#define PACKET3_CLEAR_STATE 0x121671#define PACKET3_INDEX_BUFFER_SIZE 0x131672#define PACKET3_DISPATCH_DIRECT 0x151673#define PACKET3_DISPATCH_INDIRECT 0x161674#define PACKET3_ALLOC_GDS 0x1B1675#define PACKET3_WRITE_GDS_RAM 0x1C1676#define PACKET3_ATOMIC_GDS 0x1D1677#define PACKET3_ATOMIC 0x1E1678#define PACKET3_OCCLUSION_QUERY 0x1F1679#define PACKET3_SET_PREDICATION 0x201680#define PACKET3_REG_RMW 0x211681#define PACKET3_COND_EXEC 0x221682#define PACKET3_PRED_EXEC 0x231683#define PACKET3_DRAW_INDIRECT 0x241684#define PACKET3_DRAW_INDEX_INDIRECT 0x251685#define PACKET3_INDEX_BASE 0x261686#define PACKET3_DRAW_INDEX_2 0x271687#define PACKET3_CONTEXT_CONTROL 0x281688#define PACKET3_INDEX_TYPE 0x2A1689#define PACKET3_DRAW_INDIRECT_MULTI 0x2C1690#define PACKET3_DRAW_INDEX_AUTO 0x2D1691#define PACKET3_DRAW_INDEX_IMMD 0x2E1692#define PACKET3_NUM_INSTANCES 0x2F1693#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x301694#define PACKET3_INDIRECT_BUFFER_CONST 0x311695#define PACKET3_INDIRECT_BUFFER 0x3F1696#define PACKET3_STRMOUT_BUFFER_UPDATE 0x341697#define PACKET3_DRAW_INDEX_OFFSET_2 0x351698#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x361699#define PACKET3_WRITE_DATA 0x371700#define WRITE_DATA_DST_SEL(x) ((x) << 8)1701 /* 0 - register1702 * 1 - memory (sync - via GRBM)1703 * 2 - tc/l21704 * 3 - gds1705 * 4 - reserved1706 * 5 - memory (async - direct)1707 */1708#define WR_ONE_ADDR (1 << 16)1709#define WR_CONFIRM (1 << 20)1710#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)1711 /* 0 - me1712 * 1 - pfp1713 * 2 - ce1714 */1715#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x381716#define PACKET3_MEM_SEMAPHORE 0x391717#define PACKET3_MPEG_INDEX 0x3A1718#define PACKET3_COPY_DW 0x3B1719#define PACKET3_WAIT_REG_MEM 0x3C1720#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)1721 /* 0 - always1722 * 1 - <1723 * 2 - <=1724 * 3 - ==1725 * 4 - !=1726 * 5 - >=1727 * 6 - >1728 */1729#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)1730 /* 0 - reg1731 * 1 - mem1732 */1733#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)1734 /* 0 - me1735 * 1 - pfp1736 */1737#define PACKET3_MEM_WRITE 0x3D1738#define PACKET3_COPY_DATA 0x401739#define PACKET3_CP_DMA 0x411740/* 1. header1741 * 2. SRC_ADDR_LO or DATA [31:0]1742 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |1743 * SRC_ADDR_HI [7:0]1744 * 4. DST_ADDR_LO [31:0]1745 * 5. DST_ADDR_HI [7:0]1746 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]1747 */1748# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)1749 /* 0 - DST_ADDR1750 * 1 - GDS1751 */1752# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)1753 /* 0 - ME1754 * 1 - PFP1755 */1756# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)1757 /* 0 - SRC_ADDR1758 * 1 - GDS1759 * 2 - DATA1760 */1761# define PACKET3_CP_DMA_CP_SYNC (1 << 31)1762/* COMMAND */1763# define PACKET3_CP_DMA_DIS_WC (1 << 21)1764# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)1765 /* 0 - none1766 * 1 - 8 in 161767 * 2 - 8 in 321768 * 3 - 8 in 641769 */1770# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)1771 /* 0 - none1772 * 1 - 8 in 161773 * 2 - 8 in 321774 * 3 - 8 in 641775 */1776# define PACKET3_CP_DMA_CMD_SAS (1 << 26)1777 /* 0 - memory1778 * 1 - register1779 */1780# define PACKET3_CP_DMA_CMD_DAS (1 << 27)1781 /* 0 - memory1782 * 1 - register1783 */1784# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)1785# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)1786# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)1787#define PACKET3_PFP_SYNC_ME 0x421788#define PACKET3_SURFACE_SYNC 0x431789# define PACKET3_DEST_BASE_0_ENA (1 << 0)1790# define PACKET3_DEST_BASE_1_ENA (1 << 1)1791# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)1792# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)1793# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)1794# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)1795# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)1796# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)1797# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)1798# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)1799# define PACKET3_DB_DEST_BASE_ENA (1 << 14)1800# define PACKET3_DEST_BASE_2_ENA (1 << 19)1801# define PACKET3_DEST_BASE_3_ENA (1 << 21)1802# define PACKET3_TCL1_ACTION_ENA (1 << 22)1803# define PACKET3_TC_ACTION_ENA (1 << 23)1804# define PACKET3_CB_ACTION_ENA (1 << 25)1805# define PACKET3_DB_ACTION_ENA (1 << 26)1806# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)1807# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)1808#define PACKET3_ME_INITIALIZE 0x441809#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)1810#define PACKET3_COND_WRITE 0x451811#define PACKET3_EVENT_WRITE 0x461812#define EVENT_TYPE(x) ((x) << 0)1813#define EVENT_INDEX(x) ((x) << 8)1814 /* 0 - any non-TS event1815 * 1 - ZPASS_DONE1816 * 2 - SAMPLE_PIPELINESTAT1817 * 3 - SAMPLE_STREAMOUTSTAT*1818 * 4 - *S_PARTIAL_FLUSH1819 * 5 - EOP events1820 * 6 - EOS events1821 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT1822 */1823#define INV_L2 (1 << 20)1824 /* INV TC L2 cache when EVENT_INDEX = 7 */1825#define PACKET3_EVENT_WRITE_EOP 0x471826#define DATA_SEL(x) ((x) << 29)1827 /* 0 - discard1828 * 1 - send low 32bit data1829 * 2 - send 64bit data1830 * 3 - send 64bit counter value1831 */1832#define INT_SEL(x) ((x) << 24)1833 /* 0 - none1834 * 1 - interrupt only (DATA_SEL = 0)1835 * 2 - interrupt when data write is confirmed1836 */1837#define PACKET3_EVENT_WRITE_EOS 0x481838#define PACKET3_PREAMBLE_CNTL 0x4A1839# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)1840# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)1841#define PACKET3_ONE_REG_WRITE 0x571842#define PACKET3_LOAD_CONFIG_REG 0x5F1843#define PACKET3_LOAD_CONTEXT_REG 0x601844#define PACKET3_LOAD_SH_REG 0x611845#define PACKET3_SET_CONFIG_REG 0x681846#define PACKET3_SET_CONFIG_REG_START 0x000020001847#define PACKET3_SET_CONFIG_REG_END 0x00002c001848#define PACKET3_SET_CONTEXT_REG 0x691849#define PACKET3_SET_CONTEXT_REG_START 0x000a0001850#define PACKET3_SET_CONTEXT_REG_END 0x000a4001851#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x731852#define PACKET3_SET_RESOURCE_INDIRECT 0x741853#define PACKET3_SET_SH_REG 0x761854#define PACKET3_SET_SH_REG_START 0x00002c001855#define PACKET3_SET_SH_REG_END 0x000030001856#define PACKET3_SET_SH_REG_OFFSET 0x771857#define PACKET3_ME_WRITE 0x7A1858#define PACKET3_SCRATCH_RAM_WRITE 0x7D1859#define PACKET3_SCRATCH_RAM_READ 0x7E1860#define PACKET3_CE_WRITE 0x7F1861#define PACKET3_LOAD_CONST_RAM 0x801862#define PACKET3_WRITE_CONST_RAM 0x811863#define PACKET3_WRITE_CONST_RAM_OFFSET 0x821864#define PACKET3_DUMP_CONST_RAM 0x831865#define PACKET3_INCREMENT_CE_COUNTER 0x841866#define PACKET3_INCREMENT_DE_COUNTER 0x851867#define PACKET3_WAIT_ON_CE_COUNTER 0x861868#define PACKET3_WAIT_ON_DE_COUNTER 0x871869#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x881870#define PACKET3_SET_CE_DE_COUNTERS 0x891871#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A1872#define PACKET3_SWITCH_BUFFER 0x8B1873 1874/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */1875#define DMA0_REGISTER_OFFSET 0x0 /* not a register */1876#define DMA1_REGISTER_OFFSET 0x200 /* not a register */1877 1878#define DMA_RB_CNTL 0x34001879# define DMA_RB_ENABLE (1 << 0)1880# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */1881# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */1882# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)1883# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */1884# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */1885#define DMA_RB_BASE 0x34011886#define DMA_RB_RPTR 0x34021887#define DMA_RB_WPTR 0x34031888 1889#define DMA_RB_RPTR_ADDR_HI 0x34071890#define DMA_RB_RPTR_ADDR_LO 0x34081891 1892#define DMA_IB_CNTL 0x34091893# define DMA_IB_ENABLE (1 << 0)1894# define DMA_IB_SWAP_ENABLE (1 << 4)1895# define CMD_VMID_FORCE (1 << 31)1896#define DMA_IB_RPTR 0x340a1897#define DMA_CNTL 0x340b1898# define TRAP_ENABLE (1 << 0)1899# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)1900# define SEM_WAIT_INT_ENABLE (1 << 2)1901# define DATA_SWAP_ENABLE (1 << 3)1902# define FENCE_SWAP_ENABLE (1 << 4)1903# define CTXEMPTY_INT_ENABLE (1 << 28)1904#define DMA_STATUS_REG 0x340d1905# define DMA_IDLE (1 << 0)1906#define DMA_TILING_CONFIG 0x342e1907 1908#define DMA_POWER_CNTL 0x342f1909# define MEM_POWER_OVERRIDE (1 << 8)1910#define DMA_CLK_CTRL 0x34301911 1912#define DMA_PG 0x34351913# define PG_CNTL_ENABLE (1 << 0)1914#define DMA_PGFSM_CONFIG 0x34361915#define DMA_PGFSM_WRITE 0x34371916 1917#define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \1918 (((b) & 0x1) << 26) | \1919 (((t) & 0x1) << 23) | \1920 (((s) & 0x1) << 22) | \1921 (((n) & 0xFFFFF) << 0))1922 1923#define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \1924 (((vmid) & 0xF) << 20) | \1925 (((n) & 0xFFFFF) << 0))1926 1927#define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \1928 (1 << 26) | \1929 (1 << 21) | \1930 (((n) & 0xFFFFF) << 0))1931 1932/* async DMA Packet types */1933#define DMA_PACKET_WRITE 0x21934#define DMA_PACKET_COPY 0x31935#define DMA_PACKET_INDIRECT_BUFFER 0x41936#define DMA_PACKET_SEMAPHORE 0x51937#define DMA_PACKET_FENCE 0x61938#define DMA_PACKET_TRAP 0x71939#define DMA_PACKET_SRBM_WRITE 0x91940#define DMA_PACKET_CONSTANT_FILL 0xd1941#define DMA_PACKET_POLL_REG_MEM 0xe1942#define DMA_PACKET_NOP 0xf1943 1944#define VCE_STATUS 0x200041945#define VCE_VCPU_CNTL 0x200141946#define VCE_CLK_EN (1 << 0)1947#define VCE_VCPU_CACHE_OFFSET0 0x200241948#define VCE_VCPU_CACHE_SIZE0 0x200281949#define VCE_VCPU_CACHE_OFFSET1 0x2002c1950#define VCE_VCPU_CACHE_SIZE1 0x200301951#define VCE_VCPU_CACHE_OFFSET2 0x200341952#define VCE_VCPU_CACHE_SIZE2 0x200381953#define VCE_SOFT_RESET 0x201201954#define VCE_ECPU_SOFT_RESET (1 << 0)1955#define VCE_FME_SOFT_RESET (1 << 2)1956#define VCE_RB_BASE_LO2 0x2016c1957#define VCE_RB_BASE_HI2 0x201701958#define VCE_RB_SIZE2 0x201741959#define VCE_RB_RPTR2 0x201781960#define VCE_RB_WPTR2 0x2017c1961#define VCE_RB_BASE_LO 0x201801962#define VCE_RB_BASE_HI 0x201841963#define VCE_RB_SIZE 0x201881964#define VCE_RB_RPTR 0x2018c1965#define VCE_RB_WPTR 0x201901966#define VCE_CLOCK_GATING_A 0x202f81967#define VCE_CLOCK_GATING_B 0x202fc1968#define VCE_UENC_CLOCK_GATING 0x205bc1969#define VCE_UENC_REG_CLOCK_GATING 0x205c01970#define VCE_FW_REG_STATUS 0x20e101971# define VCE_FW_REG_STATUS_BUSY (1 << 0)1972# define VCE_FW_REG_STATUS_PASS (1 << 3)1973# define VCE_FW_REG_STATUS_DONE (1 << 11)1974#define VCE_LMI_FW_START_KEYSEL 0x20e181975#define VCE_LMI_FW_PERIODIC_CTRL 0x20e201976#define VCE_LMI_CTRL2 0x20e741977#define VCE_LMI_CTRL 0x20e981978#define VCE_LMI_VM_CTRL 0x20ea01979#define VCE_LMI_SWAP_CNTL 0x20eb41980#define VCE_LMI_SWAP_CNTL1 0x20eb81981#define VCE_LMI_CACHE_CTRL 0x20ef41982 1983#define VCE_CMD_NO_OP 0x000000001984#define VCE_CMD_END 0x000000011985#define VCE_CMD_IB 0x000000021986#define VCE_CMD_FENCE 0x000000031987#define VCE_CMD_TRAP 0x000000041988#define VCE_CMD_IB_AUTO 0x000000051989#define VCE_CMD_SEMAPHORE 0x000000061990 1991 1992//#dce stupp1993/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */1994#define SI_CRTC0_REGISTER_OFFSET 0 //(0x6df0 - 0x6df0)/41995#define SI_CRTC1_REGISTER_OFFSET 0x300 //(0x79f0 - 0x6df0)/41996#define SI_CRTC2_REGISTER_OFFSET 0x2600 //(0x105f0 - 0x6df0)/41997#define SI_CRTC3_REGISTER_OFFSET 0x2900 //(0x111f0 - 0x6df0)/41998#define SI_CRTC4_REGISTER_OFFSET 0x2c00 //(0x11df0 - 0x6df0)/41999#define SI_CRTC5_REGISTER_OFFSET 0x2f00 //(0x129f0 - 0x6df0)/42000 2001#define CURSOR_WIDTH 642002#define CURSOR_HEIGHT 642003#define AMDGPU_MM_INDEX 0x00002004#define AMDGPU_MM_DATA 0x00012005 2006#define VERDE_NUM_CRTC 62007#define BLACKOUT_MODE_MASK 0x000000072008#define VGA_RENDER_CONTROL 0xC02009#define R_000300_VGA_RENDER_CONTROL 0xC02010#define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF2011#define EVERGREEN_CRTC_STATUS 0x1BA32012#define EVERGREEN_CRTC_V_BLANK (1 << 0)2013#define EVERGREEN_CRTC_STATUS_POSITION 0x1BA42014/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */2015#define EVERGREEN_CRTC_V_BLANK_START_END 0x1b8d2016#define EVERGREEN_CRTC_CONTROL 0x1b9c2017#define EVERGREEN_CRTC_MASTER_EN (1 << 0)2018#define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)2019#define EVERGREEN_CRTC_BLANK_CONTROL 0x1b9d2020#define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8)2021#define EVERGREEN_CRTC_V_BLANK (1 << 0)2022#define EVERGREEN_CRTC_STATUS_HV_COUNT 0x1ba82023#define EVERGREEN_CRTC_UPDATE_LOCK 0x1bb52024#define EVERGREEN_MASTER_UPDATE_LOCK 0x1bbd2025#define EVERGREEN_MASTER_UPDATE_MODE 0x1bbe2026#define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)2027#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a072028#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a082029#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a042030#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a052031#define EVERGREEN_GRPH_UPDATE 0x1a112032#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0xc42033#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0xc92034#define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)2035 2036#define EVERGREEN_DATA_FORMAT 0x1ac02037# define EVERGREEN_INTERLEAVE_EN (1 << 0)2038 2039#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf0002040#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc2041 2042#define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20)2043#define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20)2044#define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20)2045#define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20)2046 2047#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a452048#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x18452049 2050#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x18472051#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a472052 2053#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x82054#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x82055#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x82056#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x82057#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x82058#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x82059 2060#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x42061#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x42062#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x42063#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x42064#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x42065#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x42066 2067#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x200002068#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x200002069#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x200002070#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x200002071#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x200002072#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x200002073 2074#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x12075#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x1002076 2077#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x12078 2079#define R600_D1GRPH_SWAP_CONTROL 0x18432080#define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)2081#define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)2082#define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)2083#define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)2084 2085#define AVIVO_D1VGA_CONTROL 0x00cc2086# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0)2087# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1 << 8)2088# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9)2089# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10)2090# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16)2091# define AVIVO_DVGA_CONTROL_ROTATE (1 << 24)2092#define AVIVO_D2VGA_CONTROL 0x00ce2093 2094#define R600_BUS_CNTL 0x15082095# define R600_BIOS_ROM_DIS (1 << 1)2096 2097#define R600_ROM_CNTL 0x5802098# define R600_SCK_OVERWRITE (1 << 1)2099# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 282100# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)2101 2102#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x12103 2104#define FMT_BIT_DEPTH_CONTROL 0x1bf22105#define FMT_TRUNCATE_EN (1 << 0)2106#define FMT_TRUNCATE_DEPTH (1 << 4)2107#define FMT_SPATIAL_DITHER_EN (1 << 8)2108#define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)2109#define FMT_SPATIAL_DITHER_DEPTH (1 << 12)2110#define FMT_FRAME_RANDOM_ENABLE (1 << 13)2111#define FMT_RGB_RANDOM_ENABLE (1 << 14)2112#define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)2113#define FMT_TEMPORAL_DITHER_EN (1 << 16)2114#define FMT_TEMPORAL_DITHER_DEPTH (1 << 20)2115#define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)2116#define FMT_TEMPORAL_LEVEL (1 << 24)2117#define FMT_TEMPORAL_DITHER_RESET (1 << 25)2118#define FMT_25FRC_SEL(x) ((x) << 26)2119#define FMT_50FRC_SEL(x) ((x) << 28)2120#define FMT_75FRC_SEL(x) ((x) << 30)2121 2122#define EVERGREEN_DC_LUT_CONTROL 0x1a802123#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x1a812124#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x1a822125#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x1a832126#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x1a842127#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x1a852128#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x1a862129#define EVERGREEN_DC_LUT_30_COLOR 0x1a7c2130#define EVERGREEN_DC_LUT_RW_INDEX 0x1a792131#define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x1a7e2132#define EVERGREEN_DC_LUT_RW_MODE 0x1a782133 2134#define EVERGREEN_GRPH_ENABLE 0x1a002135#define EVERGREEN_GRPH_CONTROL 0x1a012136#define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0)2137#define EVERGREEN_GRPH_DEPTH_8BPP 02138#define EVERGREEN_GRPH_DEPTH_16BPP 12139#define EVERGREEN_GRPH_DEPTH_32BPP 22140#define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)2141#define EVERGREEN_ADDR_SURF_2_BANK 02142#define EVERGREEN_ADDR_SURF_4_BANK 12143#define EVERGREEN_ADDR_SURF_8_BANK 22144#define EVERGREEN_ADDR_SURF_16_BANK 32145#define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4)2146#define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)2147#define EVERGREEN_ADDR_SURF_BANK_WIDTH_1 02148#define EVERGREEN_ADDR_SURF_BANK_WIDTH_2 12149#define EVERGREEN_ADDR_SURF_BANK_WIDTH_4 22150#define EVERGREEN_ADDR_SURF_BANK_WIDTH_8 32151#define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8)2152 2153#define EVERGREEN_GRPH_FORMAT_INDEXED 02154#define EVERGREEN_GRPH_FORMAT_ARGB1555 02155#define EVERGREEN_GRPH_FORMAT_ARGB565 12156#define EVERGREEN_GRPH_FORMAT_ARGB4444 22157#define EVERGREEN_GRPH_FORMAT_AI88 32158#define EVERGREEN_GRPH_FORMAT_MONO16 42159#define EVERGREEN_GRPH_FORMAT_BGRA5551 52160 2161/* 32 BPP */2162#define EVERGREEN_GRPH_FORMAT_ARGB8888 02163#define EVERGREEN_GRPH_FORMAT_ARGB2101010 12164#define EVERGREEN_GRPH_FORMAT_32BPP_DIG 22165#define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 32166#define EVERGREEN_GRPH_FORMAT_BGRA1010102 42167#define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 52168#define EVERGREEN_GRPH_FORMAT_RGB111110 62169#define EVERGREEN_GRPH_FORMAT_BGR101111 72170#define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)2171#define EVERGREEN_ADDR_SURF_BANK_HEIGHT_1 02172#define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2 12173#define EVERGREEN_ADDR_SURF_BANK_HEIGHT_4 22174#define EVERGREEN_ADDR_SURF_BANK_HEIGHT_8 32175#define EVERGREEN_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)2176#define EVERGREEN_ADDR_SURF_TILE_SPLIT_64B 02177#define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B 12178#define EVERGREEN_ADDR_SURF_TILE_SPLIT_256B 22179#define EVERGREEN_ADDR_SURF_TILE_SPLIT_512B 32180#define EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB 42181#define EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB 52182#define EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB 62183#define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)2184#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 02185#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 12186#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 22187#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 32188#define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)2189#define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL 02190#define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 12191#define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 22192#define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 42193#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 02194#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 12195#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 22196#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 32197 2198#define EVERGREEN_GRPH_SWAP_CONTROL 0x1a032199#define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)2200# define EVERGREEN_GRPH_ENDIAN_NONE 02201# define EVERGREEN_GRPH_ENDIAN_8IN16 12202# define EVERGREEN_GRPH_ENDIAN_8IN32 22203# define EVERGREEN_GRPH_ENDIAN_8IN64 32204#define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)2205# define EVERGREEN_GRPH_RED_SEL_R 02206# define EVERGREEN_GRPH_RED_SEL_G 12207# define EVERGREEN_GRPH_RED_SEL_B 22208# define EVERGREEN_GRPH_RED_SEL_A 32209#define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)2210# define EVERGREEN_GRPH_GREEN_SEL_G 02211# define EVERGREEN_GRPH_GREEN_SEL_B 12212# define EVERGREEN_GRPH_GREEN_SEL_A 22213# define EVERGREEN_GRPH_GREEN_SEL_R 32214#define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)2215# define EVERGREEN_GRPH_BLUE_SEL_B 02216# define EVERGREEN_GRPH_BLUE_SEL_A 12217# define EVERGREEN_GRPH_BLUE_SEL_R 22218# define EVERGREEN_GRPH_BLUE_SEL_G 32219#define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)2220# define EVERGREEN_GRPH_ALPHA_SEL_A 02221# define EVERGREEN_GRPH_ALPHA_SEL_R 12222# define EVERGREEN_GRPH_ALPHA_SEL_G 22223# define EVERGREEN_GRPH_ALPHA_SEL_B 32224 2225#define EVERGREEN_D3VGA_CONTROL 0xf82226#define EVERGREEN_D4VGA_CONTROL 0xf92227#define EVERGREEN_D5VGA_CONTROL 0xfa2228#define EVERGREEN_D6VGA_CONTROL 0xfb2229 2230#define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff002231 2232#define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL 0x1a022233#define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8)2234 2235#define EVERGREEN_GRPH_PITCH 0x1a062236#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a072237#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a082238#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x1a092239#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x1a0a2240#define EVERGREEN_GRPH_X_START 0x1a0b2241#define EVERGREEN_GRPH_Y_START 0x1a0c2242#define EVERGREEN_GRPH_X_END 0x1a0d2243#define EVERGREEN_GRPH_Y_END 0x1a0e2244#define EVERGREEN_GRPH_UPDATE 0x1a112245#define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)2246#define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)2247#define EVERGREEN_GRPH_FLIP_CONTROL 0x1a122248#define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)2249 2250#define EVERGREEN_VIEWPORT_START 0x1b5c2251#define EVERGREEN_VIEWPORT_SIZE 0x1b5d2252#define EVERGREEN_DESKTOP_HEIGHT 0x1ac12253 2254/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */2255#define EVERGREEN_CUR_CONTROL 0x1a662256# define EVERGREEN_CURSOR_EN (1 << 0)2257# define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8)2258# define EVERGREEN_CURSOR_MONO 02259# define EVERGREEN_CURSOR_24_1 12260# define EVERGREEN_CURSOR_24_8_PRE_MULT 22261# define EVERGREEN_CURSOR_24_8_UNPRE_MULT 32262# define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16)2263# define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20)2264# define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)2265# define EVERGREEN_CURSOR_URGENT_ALWAYS 02266# define EVERGREEN_CURSOR_URGENT_1_8 12267# define EVERGREEN_CURSOR_URGENT_1_4 22268# define EVERGREEN_CURSOR_URGENT_3_8 32269# define EVERGREEN_CURSOR_URGENT_1_2 42270#define EVERGREEN_CUR_SURFACE_ADDRESS 0x1a672271# define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff0002272#define EVERGREEN_CUR_SIZE 0x1a682273#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x1a692274#define EVERGREEN_CUR_POSITION 0x1a6a2275#define EVERGREEN_CUR_HOT_SPOT 0x1a6b2276#define EVERGREEN_CUR_COLOR1 0x1a6c2277#define EVERGREEN_CUR_COLOR2 0x1a6d2278#define EVERGREEN_CUR_UPDATE 0x1a6e2279# define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0)2280# define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1)2281# define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16)2282# define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)2283 2284 2285#define NI_INPUT_CSC_CONTROL 0x1a352286# define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0)2287# define NI_INPUT_CSC_BYPASS 02288# define NI_INPUT_CSC_PROG_COEFF 12289# define NI_INPUT_CSC_PROG_SHARED_MATRIXA 22290# define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4)2291 2292#define NI_OUTPUT_CSC_CONTROL 0x1a3c2293# define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0)2294# define NI_OUTPUT_CSC_BYPASS 02295# define NI_OUTPUT_CSC_TV_RGB 12296# define NI_OUTPUT_CSC_YCBCR_601 22297# define NI_OUTPUT_CSC_YCBCR_709 32298# define NI_OUTPUT_CSC_PROG_COEFF 42299# define NI_OUTPUT_CSC_PROG_SHARED_MATRIXB 52300# define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4)2301 2302#define NI_DEGAMMA_CONTROL 0x1a582303# define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0)2304# define NI_DEGAMMA_BYPASS 02305# define NI_DEGAMMA_SRGB_24 12306# define NI_DEGAMMA_XVYCC_222 22307# define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4)2308# define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)2309# define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12)2310 2311#define NI_GAMUT_REMAP_CONTROL 0x1a592312# define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0)2313# define NI_GAMUT_REMAP_BYPASS 02314# define NI_GAMUT_REMAP_PROG_COEFF 12315# define NI_GAMUT_REMAP_PROG_SHARED_MATRIXA 22316# define NI_GAMUT_REMAP_PROG_SHARED_MATRIXB 32317# define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 4)2318 2319#define NI_REGAMMA_CONTROL 0x1aa02320# define NI_GRPH_REGAMMA_MODE(x) (((x) & 0x7) << 0)2321# define NI_REGAMMA_BYPASS 02322# define NI_REGAMMA_SRGB_24 12323# define NI_REGAMMA_XVYCC_222 22324# define NI_REGAMMA_PROG_A 32325# define NI_REGAMMA_PROG_B 42326# define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4)2327 2328 2329#define NI_PRESCALE_GRPH_CONTROL 0x1a2d2330# define NI_GRPH_PRESCALE_BYPASS (1 << 4)2331 2332#define NI_PRESCALE_OVL_CONTROL 0x1a312333# define NI_OVL_PRESCALE_BYPASS (1 << 4)2334 2335#define NI_INPUT_GAMMA_CONTROL 0x1a102336# define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0)2337# define NI_INPUT_GAMMA_USE_LUT 02338# define NI_INPUT_GAMMA_BYPASS 12339# define NI_INPUT_GAMMA_SRGB_24 22340# define NI_INPUT_GAMMA_XVYCC_222 32341# define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4)2342 2343#define BLACKOUT_MODE_MASK 0x000000072344#define VGA_RENDER_CONTROL 0xC02345#define R_000300_VGA_RENDER_CONTROL 0xC02346#define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF2347#define EVERGREEN_CRTC_STATUS 0x1BA32348#define EVERGREEN_CRTC_V_BLANK (1 << 0)2349#define EVERGREEN_CRTC_STATUS_POSITION 0x1BA42350/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */2351#define EVERGREEN_CRTC_V_BLANK_START_END 0x1b8d2352#define EVERGREEN_CRTC_CONTROL 0x1b9c2353# define EVERGREEN_CRTC_MASTER_EN (1 << 0)2354# define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)2355#define EVERGREEN_CRTC_BLANK_CONTROL 0x1b9d2356# define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8)2357# define EVERGREEN_CRTC_V_BLANK (1 << 0)2358#define EVERGREEN_CRTC_STATUS_HV_COUNT 0x1ba82359#define EVERGREEN_CRTC_UPDATE_LOCK 0x1bb52360#define EVERGREEN_MASTER_UPDATE_LOCK 0x1bbd2361#define EVERGREEN_MASTER_UPDATE_MODE 0x1bbe2362#define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)2363#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a072364#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a082365#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a042366#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a052367#define EVERGREEN_GRPH_UPDATE 0x1a112368#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0xc42369#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0xc92370#define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)2371 2372#define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x102373#define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x42374#define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x802375#define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x72376#define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x4002377#define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa2378#define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x20002379#define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd2380#define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x100002381#define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x102382#define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x800002383#define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x132384 2385#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID_MASK 0x1e0000002386#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID__SHIFT 0x192387#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS_MASK 0xff2388#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS__SHIFT 0x02389#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID_MASK 0xff0002390#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID__SHIFT 0xc2391#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW_MASK 0x10000002392#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW__SHIFT 0x182393 2394#define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE_MASK 0x72395#define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE__SHIFT 0x02396 2397#define mmBIF_FB_EN__xxFB_READ_EN_MASK 0x12398#define mmBIF_FB_EN__xxFB_READ_EN__SHIFT 0x02399#define mmBIF_FB_EN__xxFB_WRITE_EN_MASK 0x22400#define mmBIF_FB_EN__xxFB_WRITE_EN__SHIFT 0x12401 2402#define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC_MASK 0x200002403#define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC__SHIFT 0x112404#define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC_MASK 0x8002405#define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC__SHIFT 0xb2406 2407#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x82408#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x32409#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x402410#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x62411#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x2002412#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x92413#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x10002414#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc2415#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x80002416#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf2417#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x400002418#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x122419 2420#define MC_SEQ_MISC0__MT__MASK 0xf00000002421#define MC_SEQ_MISC0__MT__GDDR1 0x100000002422#define MC_SEQ_MISC0__MT__DDR2 0x200000002423#define MC_SEQ_MISC0__MT__GDDR3 0x300000002424#define MC_SEQ_MISC0__MT__GDDR4 0x400000002425#define MC_SEQ_MISC0__MT__GDDR5 0x500000002426#define MC_SEQ_MISC0__MT__HBM 0x600000002427#define MC_SEQ_MISC0__MT__DDR3 0xB00000002428 2429#define GRBM_STATUS__GUI_ACTIVE_MASK 0x800000002430#define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x40000002431#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x8000002432#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x4000002433#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)2434#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)2435#define PACKET3_SEM_SEL_WAIT (0x7 << 29)2436 2437#define CONFIG_CNTL 0x15092438#define CC_DRM_ID_STRAPS 0X15592439#define AMDGPU_PCIE_INDEX 0xc2440#define AMDGPU_PCIE_DATA 0xd2441 2442#define DMA_SEM_INCOMPLETE_TIMER_CNTL 0x34112443#define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0x34122444#define DMA_MODE 0x342f2445#define DMA_RB_RPTR_ADDR_HI 0x34072446#define DMA_RB_RPTR_ADDR_LO 0x34082447#define DMA_BUSY_MASK 0x202448#define DMA1_BUSY_MASK 0X402449#define SDMA_MAX_INSTANCE 22450 2451#define PCIE_BUS_CLK 100002452#define TCLK (PCIE_BUS_CLK / 10)2453#define PCIE_PORT_INDEX 0xe2454#define PCIE_PORT_DATA 0xf2455#define EVERGREEN_PIF_PHY0_INDEX 0x82456#define EVERGREEN_PIF_PHY0_DATA 0xc2457#define EVERGREEN_PIF_PHY1_INDEX 0x102458#define EVERGREEN_PIF_PHY1_DATA 0x142459 2460#define MC_VM_FB_OFFSET 0x81a2461 2462/* Discrete VCE clocks */2463#define CG_VCEPLL_FUNC_CNTL 0xc00306002464#define VCEPLL_RESET_MASK 0x000000012465#define VCEPLL_SLEEP_MASK 0x000000022466#define VCEPLL_BYPASS_EN_MASK 0x000000042467#define VCEPLL_CTLREQ_MASK 0x000000082468#define VCEPLL_VCO_MODE_MASK 0x000006002469#define VCEPLL_REF_DIV_MASK 0x003F00002470#define VCEPLL_CTLACK_MASK 0x400000002471#define VCEPLL_CTLACK2_MASK 0x800000002472 2473#define CG_VCEPLL_FUNC_CNTL_2 0xc00306012474#define VCEPLL_PDIV_A(x) ((x) << 0)2475#define VCEPLL_PDIV_A_MASK 0x0000007F2476#define VCEPLL_PDIV_B(x) ((x) << 8)2477#define VCEPLL_PDIV_B_MASK 0x00007F002478#define EVCLK_SRC_SEL(x) ((x) << 20)2479#define EVCLK_SRC_SEL_MASK 0x01F000002480#define ECCLK_SRC_SEL(x) ((x) << 25)2481#define ECCLK_SRC_SEL_MASK 0x3E0000002482 2483#define CG_VCEPLL_FUNC_CNTL_3 0xc00306022484#define VCEPLL_FB_DIV(x) ((x) << 0)2485#define VCEPLL_FB_DIV_MASK 0x01FFFFFF2486 2487#define CG_VCEPLL_FUNC_CNTL_4 0xc00306032488 2489#define CG_VCEPLL_FUNC_CNTL_5 0xc00306042490#define CG_VCEPLL_SPREAD_SPECTRUM 0xc00306062491#define VCEPLL_SSEN_MASK 0x000000012492 2493 2494#endif2495