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1/*2 * Copyright 2023 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include "smu_v13_0_10.h"25#include "amdgpu_reset.h"26#include "amdgpu_dpm.h"27#include "amdgpu_job.h"28#include "amdgpu_ring.h"29#include "amdgpu_ras.h"30#include "amdgpu_psp.h"31 32static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control *reset_ctl)33{34 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;35 if (adev->pm.fw_version >= 0x00502005 && !amdgpu_sriov_vf(adev))36 return true;37 38 return false;39}40 41static struct amdgpu_reset_handler *42smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control *reset_ctl,43 struct amdgpu_reset_context *reset_context)44{45 struct amdgpu_reset_handler *handler;46 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;47 int i;48 49 if (reset_context->method != AMD_RESET_METHOD_NONE) {50 for_each_handler(i, handler, reset_ctl) {51 if (handler->reset_method == reset_context->method)52 return handler;53 }54 }55 56 if (smu_v13_0_10_is_mode2_default(reset_ctl) &&57 amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_MODE2) {58 for_each_handler(i, handler, reset_ctl) {59 if (handler->reset_method == AMD_RESET_METHOD_MODE2)60 return handler;61 }62 }63 64 return NULL;65}66 67static int smu_v13_0_10_mode2_suspend_ip(struct amdgpu_device *adev)68{69 int r, i;70 71 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);72 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);73 74 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {75 if (!(adev->ip_blocks[i].version->type ==76 AMD_IP_BLOCK_TYPE_GFX ||77 adev->ip_blocks[i].version->type ==78 AMD_IP_BLOCK_TYPE_SDMA ||79 adev->ip_blocks[i].version->type ==80 AMD_IP_BLOCK_TYPE_MES))81 continue;82 83 r = adev->ip_blocks[i].version->funcs->suspend(adev);84 85 if (r) {86 dev_err(adev->dev,87 "suspend of IP block <%s> failed %d\n",88 adev->ip_blocks[i].version->funcs->name, r);89 return r;90 }91 adev->ip_blocks[i].status.hw = false;92 }93 94 return 0;95}96 97static int98smu_v13_0_10_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,99 struct amdgpu_reset_context *reset_context)100{101 int r = 0;102 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;103 104 if (!amdgpu_sriov_vf(adev))105 r = smu_v13_0_10_mode2_suspend_ip(adev);106 107 return r;108}109 110static int smu_v13_0_10_mode2_reset(struct amdgpu_device *adev)111{112 return amdgpu_dpm_mode2_reset(adev);113}114 115static void smu_v13_0_10_async_reset(struct work_struct *work)116{117 struct amdgpu_reset_handler *handler;118 struct amdgpu_reset_control *reset_ctl =119 container_of(work, struct amdgpu_reset_control, reset_work);120 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;121 int i;122 123 for_each_handler(i, handler, reset_ctl) {124 if (handler->reset_method == reset_ctl->active_reset) {125 dev_dbg(adev->dev, "Resetting device\n");126 handler->do_reset(adev);127 break;128 }129 }130}131static int132smu_v13_0_10_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,133 struct amdgpu_reset_context *reset_context)134{135 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;136 int r;137 138 r = smu_v13_0_10_mode2_reset(adev);139 if (r) {140 dev_err(adev->dev,141 "ASIC reset failed with error, %d ", r);142 }143 return r;144}145 146static int smu_v13_0_10_mode2_restore_ip(struct amdgpu_device *adev)147{148 int i, r;149 struct psp_context *psp = &adev->psp;150 struct amdgpu_firmware_info *ucode;151 struct amdgpu_firmware_info *ucode_list[2];152 int ucode_count = 0;153 154 for (i = 0; i < adev->firmware.max_ucodes; i++) {155 ucode = &adev->firmware.ucode[i];156 157 switch (ucode->ucode_id) {158 case AMDGPU_UCODE_ID_IMU_I:159 case AMDGPU_UCODE_ID_IMU_D:160 ucode_list[ucode_count++] = ucode;161 break;162 default:163 break;164 }165 }166 167 r = psp_load_fw_list(psp, ucode_list, ucode_count);168 if (r) {169 dev_err(adev->dev, "IMU ucode load failed after mode2 reset\n");170 return r;171 }172 173 r = psp_rlc_autoload_start(psp);174 if (r) {175 DRM_ERROR("Failed to start rlc autoload after mode2 reset\n");176 return r;177 }178 179 amdgpu_dpm_enable_gfx_features(adev);180 181 for (i = 0; i < adev->num_ip_blocks; i++) {182 if (!(adev->ip_blocks[i].version->type ==183 AMD_IP_BLOCK_TYPE_GFX ||184 adev->ip_blocks[i].version->type ==185 AMD_IP_BLOCK_TYPE_MES ||186 adev->ip_blocks[i].version->type ==187 AMD_IP_BLOCK_TYPE_SDMA))188 continue;189 r = adev->ip_blocks[i].version->funcs->resume(adev);190 if (r) {191 dev_err(adev->dev,192 "resume of IP block <%s> failed %d\n",193 adev->ip_blocks[i].version->funcs->name, r);194 return r;195 }196 197 adev->ip_blocks[i].status.hw = true;198 }199 200 for (i = 0; i < adev->num_ip_blocks; i++) {201 if (!(adev->ip_blocks[i].version->type ==202 AMD_IP_BLOCK_TYPE_GFX ||203 adev->ip_blocks[i].version->type ==204 AMD_IP_BLOCK_TYPE_MES ||205 adev->ip_blocks[i].version->type ==206 AMD_IP_BLOCK_TYPE_SDMA))207 continue;208 209 if (adev->ip_blocks[i].version->funcs->late_init) {210 r = adev->ip_blocks[i].version->funcs->late_init(211 (void *)adev);212 if (r) {213 dev_err(adev->dev,214 "late_init of IP block <%s> failed %d after reset\n",215 adev->ip_blocks[i].version->funcs->name,216 r);217 return r;218 }219 }220 adev->ip_blocks[i].status.late_initialized = true;221 }222 223 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);224 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);225 226 return r;227}228 229static int230smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,231 struct amdgpu_reset_context *reset_context)232{233 int r;234 struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl->handle;235 236 dev_info(tmp_adev->dev,237 "GPU reset succeeded, trying to resume\n");238 r = smu_v13_0_10_mode2_restore_ip(tmp_adev);239 if (r)240 goto end;241 242 amdgpu_register_gpu_instance(tmp_adev);243 244 /* Resume RAS */245 amdgpu_ras_resume(tmp_adev);246 247 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);248 249 r = amdgpu_ib_ring_tests(tmp_adev);250 if (r) {251 dev_err(tmp_adev->dev,252 "ib ring test failed (%d).\n", r);253 r = -EAGAIN;254 goto end;255 }256 257end:258 if (r)259 return -EAGAIN;260 else261 return r;262}263 264static struct amdgpu_reset_handler smu_v13_0_10_mode2_handler = {265 .reset_method = AMD_RESET_METHOD_MODE2,266 .prepare_env = NULL,267 .prepare_hwcontext = smu_v13_0_10_mode2_prepare_hwcontext,268 .perform_reset = smu_v13_0_10_mode2_perform_reset,269 .restore_hwcontext = smu_v13_0_10_mode2_restore_hwcontext,270 .restore_env = NULL,271 .do_reset = smu_v13_0_10_mode2_reset,272};273 274static struct amdgpu_reset_handler275 *smu_v13_0_10_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = {276 &smu_v13_0_10_mode2_handler,277 };278 279int smu_v13_0_10_reset_init(struct amdgpu_device *adev)280{281 struct amdgpu_reset_control *reset_ctl;282 283 reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);284 if (!reset_ctl)285 return -ENOMEM;286 287 reset_ctl->handle = adev;288 reset_ctl->async_reset = smu_v13_0_10_async_reset;289 reset_ctl->active_reset = AMD_RESET_METHOD_NONE;290 reset_ctl->get_reset_handler = smu_v13_0_10_get_reset_handler;291 292 INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);293 /* Only mode2 is handled through reset control now */294 reset_ctl->reset_handlers = &smu_v13_0_10_rst_handlers;295 296 adev->reset_cntl = reset_ctl;297 298 return 0;299}300 301int smu_v13_0_10_reset_fini(struct amdgpu_device *adev)302{303 kfree(adev->reset_cntl);304 adev->reset_cntl = NULL;305 return 0;306}307