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1/*2 * Copyright 2014 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23#ifndef SOC15_H24#define SOC15_H25 26#define GFX9_NUM_GFX_RINGS 127#define GFX9_NUM_COMPUTE_RINGS 828 29/*30 * PM431 */32#define PACKET_TYPE0 033#define PACKET_TYPE1 134#define PACKET_TYPE2 235#define PACKET_TYPE3 336 37#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)38#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)39#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)40#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)41#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \42 ((reg) & 0xFFFF) | \43 ((n) & 0x3FFF) << 16)44#define CP_PACKET2 0x8000000045#define PACKET2_PAD_SHIFT 046#define PACKET2_PAD_MASK (0x3fffffff << 0)47 48#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))49 50#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \51 (((op) & 0xFF) << 8) | \52 ((n) & 0x3FFF) << 16)53 54#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)55 56#define PACKETJ_CONDITION_CHECK0 057#define PACKETJ_CONDITION_CHECK1 158#define PACKETJ_CONDITION_CHECK2 259#define PACKETJ_CONDITION_CHECK3 360#define PACKETJ_CONDITION_CHECK4 461#define PACKETJ_CONDITION_CHECK5 562#define PACKETJ_CONDITION_CHECK6 663#define PACKETJ_CONDITION_CHECK7 764 65#define PACKETJ_TYPE0 066#define PACKETJ_TYPE1 167#define PACKETJ_TYPE2 268#define PACKETJ_TYPE3 369#define PACKETJ_TYPE4 470#define PACKETJ_TYPE5 571#define PACKETJ_TYPE6 672#define PACKETJ_TYPE7 773 74#define PACKETJ(reg, r, cond, type) ((reg & 0x3FFFF) | \75 ((r & 0x3F) << 18) | \76 ((cond & 0xF) << 24) | \77 ((type & 0xF) << 28))78 79#define CP_PACKETJ_NOP 0x6000000080#define CP_PACKETJ_GET_REG(x) ((x) & 0x3FFFF)81#define CP_PACKETJ_GET_RES(x) (((x) >> 18) & 0x3F)82#define CP_PACKETJ_GET_COND(x) (((x) >> 24) & 0xF)83#define CP_PACKETJ_GET_TYPE(x) (((x) >> 28) & 0xF)84 85/* Packet 3 types */86#define PACKET3_NOP 0x1087#define PACKET3_SET_BASE 0x1188#define PACKET3_BASE_INDEX(x) ((x) << 0)89#define CE_PARTITION_BASE 390#define PACKET3_CLEAR_STATE 0x1291#define PACKET3_INDEX_BUFFER_SIZE 0x1392#define PACKET3_DISPATCH_DIRECT 0x1593#define PACKET3_DISPATCH_INDIRECT 0x1694#define PACKET3_ATOMIC_GDS 0x1D95#define PACKET3_ATOMIC_MEM 0x1E96#define PACKET3_OCCLUSION_QUERY 0x1F97#define PACKET3_SET_PREDICATION 0x2098#define PACKET3_REG_RMW 0x2199#define PACKET3_COND_EXEC 0x22100#define PACKET3_PRED_EXEC 0x23101#define PACKET3_DRAW_INDIRECT 0x24102#define PACKET3_DRAW_INDEX_INDIRECT 0x25103#define PACKET3_INDEX_BASE 0x26104#define PACKET3_DRAW_INDEX_2 0x27105#define PACKET3_CONTEXT_CONTROL 0x28106#define PACKET3_INDEX_TYPE 0x2A107#define PACKET3_DRAW_INDIRECT_MULTI 0x2C108#define PACKET3_DRAW_INDEX_AUTO 0x2D109#define PACKET3_NUM_INSTANCES 0x2F110#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30111#define PACKET3_INDIRECT_BUFFER_CONST 0x33112#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34113#define PACKET3_DRAW_INDEX_OFFSET_2 0x35114#define PACKET3_DRAW_PREAMBLE 0x36115#define PACKET3_WRITE_DATA 0x37116#define WRITE_DATA_DST_SEL(x) ((x) << 8)117 /* 0 - register118 * 1 - memory (sync - via GRBM)119 * 2 - gl2120 * 3 - gds121 * 4 - reserved122 * 5 - memory (async - direct)123 */124#define WR_ONE_ADDR (1 << 16)125#define WR_CONFIRM (1 << 20)126#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)127 /* 0 - LRU128 * 1 - Stream129 */130#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)131 /* 0 - me132 * 1 - pfp133 * 2 - ce134 */135#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38136#define PACKET3_MEM_SEMAPHORE 0x39137# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)138# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */139# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)140# define PACKET3_SEM_SEL_WAIT (0x7 << 29)141#define PACKET3_WAIT_REG_MEM 0x3C142#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)143 /* 0 - always144 * 1 - <145 * 2 - <=146 * 3 - ==147 * 4 - !=148 * 5 - >=149 * 6 - >150 */151#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)152 /* 0 - reg153 * 1 - mem154 */155#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)156 /* 0 - wait_reg_mem157 * 1 - wr_wait_wr_reg158 */159#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)160 /* 0 - me161 * 1 - pfp162 */163#define PACKET3_INDIRECT_BUFFER 0x3F164#define INDIRECT_BUFFER_VALID (1 << 23)165#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)166 /* 0 - LRU167 * 1 - Stream168 * 2 - Bypass169 */170#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21)171#define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30)172#define PACKET3_COPY_DATA 0x40173#define PACKET3_PFP_SYNC_ME 0x42174#define PACKET3_COND_WRITE 0x45175#define PACKET3_EVENT_WRITE 0x46176#define EVENT_TYPE(x) ((x) << 0)177#define EVENT_INDEX(x) ((x) << 8)178 /* 0 - any non-TS event179 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*180 * 2 - SAMPLE_PIPELINESTAT181 * 3 - SAMPLE_STREAMOUTSTAT*182 * 4 - *S_PARTIAL_FLUSH183 */184#define PACKET3_RELEASE_MEM 0x49185#define EVENT_TYPE(x) ((x) << 0)186#define EVENT_INDEX(x) ((x) << 8)187#define EOP_TCL1_VOL_ACTION_EN (1 << 12)188#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */189#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */190#define EOP_TCL1_ACTION_EN (1 << 16)191#define EOP_TC_ACTION_EN (1 << 17) /* L2 */192#define EOP_TC_NC_ACTION_EN (1 << 19)193#define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */194#define EOP_EXEC (1 << 28) /* For Trailing Fence */195 196#define DATA_SEL(x) ((x) << 29)197 /* 0 - discard198 * 1 - send low 32bit data199 * 2 - send 64bit data200 * 3 - send 64bit GPU counter value201 * 4 - send 64bit sys counter value202 */203#define INT_SEL(x) ((x) << 24)204 /* 0 - none205 * 1 - interrupt only (DATA_SEL = 0)206 * 2 - interrupt when data write is confirmed207 */208#define DST_SEL(x) ((x) << 16)209 /* 0 - MC210 * 1 - TC/L2211 */212 213 214 215#define PACKET3_PREAMBLE_CNTL 0x4A216# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)217# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)218#define PACKET3_DMA_DATA 0x50219/* 1. header220 * 2. CONTROL221 * 3. SRC_ADDR_LO or DATA [31:0]222 * 4. SRC_ADDR_HI [31:0]223 * 5. DST_ADDR_LO [31:0]224 * 6. DST_ADDR_HI [7:0]225 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]226 */227/* CONTROL */228# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)229 /* 0 - ME230 * 1 - PFP231 */232# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)233 /* 0 - LRU234 * 1 - Stream235 */236# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)237 /* 0 - DST_ADDR using DAS238 * 1 - GDS239 * 3 - DST_ADDR using L2240 */241# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)242 /* 0 - LRU243 * 1 - Stream244 */245# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)246 /* 0 - SRC_ADDR using SAS247 * 1 - GDS248 * 2 - DATA249 * 3 - SRC_ADDR using L2250 */251# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)252/* COMMAND */253# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)254 /* 0 - memory255 * 1 - register256 */257# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)258 /* 0 - memory259 * 1 - register260 */261# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)262# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)263# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)264#define PACKET3_ACQUIRE_MEM 0x58265/* 1. HEADER266 * 2. COHER_CNTL [30:0]267 * 2.1 ENGINE_SEL [31:31]268 * 3. COHER_SIZE [31:0]269 * 4. COHER_SIZE_HI [7:0]270 * 5. COHER_BASE_LO [31:0]271 * 6. COHER_BASE_HI [23:0]272 * 7. POLL_INTERVAL [15:0]273 */274/* COHER_CNTL fields for CP_COHER_CNTL */275#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3)276#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) ((x) << 4)277#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5)278#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15)279#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) ((x) << 18)280#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) ((x) << 22)281#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) << 23)282#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) << 25)283#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) << 26)284#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27)285#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28)286#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29)287#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30)288#define PACKET3_REWIND 0x59289#define PACKET3_LOAD_UCONFIG_REG 0x5E290#define PACKET3_LOAD_SH_REG 0x5F291#define PACKET3_LOAD_CONFIG_REG 0x60292#define PACKET3_LOAD_CONTEXT_REG 0x61293#define PACKET3_SET_CONFIG_REG 0x68294#define PACKET3_SET_CONFIG_REG_START 0x00002000295#define PACKET3_SET_CONFIG_REG_END 0x00002c00296#define PACKET3_SET_CONTEXT_REG 0x69297#define PACKET3_SET_CONTEXT_REG_START 0x0000a000298#define PACKET3_SET_CONTEXT_REG_END 0x0000a400299#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73300#define PACKET3_SET_SH_REG 0x76301#define PACKET3_SET_SH_REG_START 0x00002c00302#define PACKET3_SET_SH_REG_END 0x00003000303#define PACKET3_SET_SH_REG_OFFSET 0x77304#define PACKET3_SET_QUEUE_REG 0x78305#define PACKET3_SET_UCONFIG_REG 0x79306#define PACKET3_SET_UCONFIG_REG_START 0x0000c000307#define PACKET3_SET_UCONFIG_REG_END 0x0000c400308#define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28)309#define PACKET3_SCRATCH_RAM_WRITE 0x7D310#define PACKET3_SCRATCH_RAM_READ 0x7E311#define PACKET3_LOAD_CONST_RAM 0x80312#define PACKET3_WRITE_CONST_RAM 0x81313#define PACKET3_DUMP_CONST_RAM 0x83314#define PACKET3_INCREMENT_CE_COUNTER 0x84315#define PACKET3_INCREMENT_DE_COUNTER 0x85316#define PACKET3_WAIT_ON_CE_COUNTER 0x86317#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88318#define PACKET3_SWITCH_BUFFER 0x8B319#define PACKET3_FRAME_CONTROL 0x90320# define FRAME_TMZ (1 << 0)321# define FRAME_CMD(x) ((x) << 28)322 /*323 * x=0: tmz_begin324 * x=1: tmz_end325 */326 327#define PACKET3_INVALIDATE_TLBS 0x98328# define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0)329# define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4)330# define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5)331# define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29)332#define PACKET3_SET_RESOURCES 0xA0333/* 1. header334 * 2. CONTROL335 * 3. QUEUE_MASK_LO [31:0]336 * 4. QUEUE_MASK_HI [31:0]337 * 5. GWS_MASK_LO [31:0]338 * 6. GWS_MASK_HI [31:0]339 * 7. OAC_MASK [15:0]340 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0]341 */342# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0)343# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)344# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29)345#define PACKET3_MAP_QUEUES 0xA2346/* 1. header347 * 2. CONTROL348 * 3. CONTROL2349 * 4. MQD_ADDR_LO [31:0]350 * 5. MQD_ADDR_HI [31:0]351 * 6. WPTR_ADDR_LO [31:0]352 * 7. WPTR_ADDR_HI [31:0]353 */354/* CONTROL */355# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4)356# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8)357# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13)358# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16)359# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18)360# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21)361# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24)362# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26)363# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29)364/* CONTROL2 */365# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1)366# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)367#define PACKET3_UNMAP_QUEUES 0xA3368/* 1. header369 * 2. CONTROL370 * 3. CONTROL2371 * 4. CONTROL3372 * 5. CONTROL4373 * 6. CONTROL5374 */375/* CONTROL */376# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0)377 /* 0 - PREEMPT_QUEUES378 * 1 - RESET_QUEUES379 * 2 - DISABLE_PROCESS_QUEUES380 * 3 - PREEMPT_QUEUES_NO_UNMAP381 */382# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4)383# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26)384# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29)385/* CONTROL2a */386# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0)387/* CONTROL2b */388# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)389/* CONTROL3a */390# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)391/* CONTROL3b */392# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0)393/* CONTROL4 */394# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)395/* CONTROL5 */396# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)397#define PACKET3_QUERY_STATUS 0xA4398/* 1. header399 * 2. CONTROL400 * 3. CONTROL2401 * 4. ADDR_LO [31:0]402 * 5. ADDR_HI [31:0]403 * 6. DATA_LO [31:0]404 * 7. DATA_HI [31:0]405 */406/* CONTROL */407# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0)408# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28)409# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30)410/* CONTROL2a */411# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0)412/* CONTROL2b */413# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2)414# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25)415 416#define PACKET3_RUN_CLEANER_SHADER 0xD2417/* 1. header418 * 2. RESERVED [31:0]419 */420 421#define VCE_CMD_NO_OP 0x00000000422#define VCE_CMD_END 0x00000001423#define VCE_CMD_IB 0x00000002424#define VCE_CMD_FENCE 0x00000003425#define VCE_CMD_TRAP 0x00000004426#define VCE_CMD_IB_AUTO 0x00000005427#define VCE_CMD_SEMAPHORE 0x00000006428 429#define VCE_CMD_IB_VM 0x00000102430#define VCE_CMD_WAIT_GE 0x00000106431#define VCE_CMD_UPDATE_PTB 0x00000107432#define VCE_CMD_FLUSH_TLB 0x00000108433#define VCE_CMD_REG_WRITE 0x00000109434#define VCE_CMD_REG_WAIT 0x0000010a435 436#define HEVC_ENC_CMD_NO_OP 0x00000000437#define HEVC_ENC_CMD_END 0x00000001438#define HEVC_ENC_CMD_FENCE 0x00000003439#define HEVC_ENC_CMD_TRAP 0x00000004440#define HEVC_ENC_CMD_IB_VM 0x00000102441#define HEVC_ENC_CMD_REG_WRITE 0x00000109442#define HEVC_ENC_CMD_REG_WAIT 0x0000010a443 444#endif445