610 lines · c
1/*2 * Copyright 2023 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23#include <linux/firmware.h>24#include <linux/slab.h>25#include <linux/module.h>26#include <linux/pci.h>27 28#include "amdgpu.h"29#include "amdgpu_atombios.h"30#include "amdgpu_ih.h"31#include "amdgpu_uvd.h"32#include "amdgpu_vce.h"33#include "amdgpu_ucode.h"34#include "amdgpu_psp.h"35#include "amdgpu_smu.h"36#include "atom.h"37#include "amd_pcie.h"38 39#include "gc/gc_12_0_0_offset.h"40#include "gc/gc_12_0_0_sh_mask.h"41#include "mp/mp_14_0_2_offset.h"42 43#include "soc15.h"44#include "soc15_common.h"45#include "soc24.h"46#include "mxgpu_nv.h"47 48static const struct amd_ip_funcs soc24_common_ip_funcs;49 50static const struct amdgpu_video_codec_info vcn_5_0_0_video_codecs_encode_array_vcn0[] = {51 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},54};55 56static const struct amdgpu_video_codecs vcn_5_0_0_video_codecs_encode_vcn0 = {57 .codec_count = ARRAY_SIZE(vcn_5_0_0_video_codecs_encode_array_vcn0),58 .codec_array = vcn_5_0_0_video_codecs_encode_array_vcn0,59};60 61static const struct amdgpu_video_codec_info vcn_5_0_0_video_codecs_decode_array_vcn0[] = {62 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},63 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},64 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},65 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},66 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},67};68 69static const struct amdgpu_video_codecs vcn_5_0_0_video_codecs_decode_vcn0 = {70 .codec_count = ARRAY_SIZE(vcn_5_0_0_video_codecs_decode_array_vcn0),71 .codec_array = vcn_5_0_0_video_codecs_decode_array_vcn0,72};73 74static int soc24_query_video_codecs(struct amdgpu_device *adev, bool encode,75 const struct amdgpu_video_codecs **codecs)76{77 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))78 return -EINVAL;79 80 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {81 case IP_VERSION(5, 0, 0):82 if (encode)83 *codecs = &vcn_5_0_0_video_codecs_encode_vcn0;84 else85 *codecs = &vcn_5_0_0_video_codecs_decode_vcn0;86 return 0;87 default:88 return -EINVAL;89 }90}91 92static u32 soc24_get_config_memsize(struct amdgpu_device *adev)93{94 return adev->nbio.funcs->get_memsize(adev);95}96 97static u32 soc24_get_xclk(struct amdgpu_device *adev)98{99 return adev->clock.spll.reference_freq;100}101 102void soc24_grbm_select(struct amdgpu_device *adev,103 u32 me, u32 pipe, u32 queue, u32 vmid)104{105 u32 grbm_gfx_cntl = 0;106 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);107 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);108 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);109 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);110 111 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);112}113 114static struct soc15_allowed_register_entry soc24_allowed_read_registers[] = {115 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},116 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},117 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},118 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},119 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},120 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},121 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},122 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},123 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},124 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},125 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},126 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},127 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},128 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},129 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},130 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},131 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},132 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},133 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},134};135 136static uint32_t soc24_read_indexed_register(struct amdgpu_device *adev,137 u32 se_num,138 u32 sh_num,139 u32 reg_offset)140{141 uint32_t val;142 143 mutex_lock(&adev->grbm_idx_mutex);144 if (se_num != 0xffffffff || sh_num != 0xffffffff)145 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);146 147 val = RREG32(reg_offset);148 149 if (se_num != 0xffffffff || sh_num != 0xffffffff)150 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);151 mutex_unlock(&adev->grbm_idx_mutex);152 return val;153}154 155static uint32_t soc24_get_register_value(struct amdgpu_device *adev,156 bool indexed, u32 se_num,157 u32 sh_num, u32 reg_offset)158{159 if (indexed) {160 return soc24_read_indexed_register(adev, se_num, sh_num, reg_offset);161 } else {162 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) &&163 adev->gfx.config.gb_addr_config)164 return adev->gfx.config.gb_addr_config;165 return RREG32(reg_offset);166 }167}168 169static int soc24_read_register(struct amdgpu_device *adev, u32 se_num,170 u32 sh_num, u32 reg_offset, u32 *value)171{172 uint32_t i;173 struct soc15_allowed_register_entry *en;174 175 *value = 0;176 for (i = 0; i < ARRAY_SIZE(soc24_allowed_read_registers); i++) {177 en = &soc24_allowed_read_registers[i];178 if (!adev->reg_offset[en->hwip][en->inst])179 continue;180 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]181 + en->reg_offset))182 continue;183 184 *value = soc24_get_register_value(adev,185 soc24_allowed_read_registers[i].grbm_indexed,186 se_num, sh_num, reg_offset);187 return 0;188 }189 return -EINVAL;190}191 192static enum amd_reset_method193soc24_asic_reset_method(struct amdgpu_device *adev)194{195 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||196 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||197 amdgpu_reset_method == AMD_RESET_METHOD_BACO)198 return amdgpu_reset_method;199 200 if (amdgpu_reset_method != -1)201 dev_warn(adev->dev,202 "Specified reset method:%d isn't supported, using AUTO instead.\n",203 amdgpu_reset_method);204 205 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {206 case IP_VERSION(14, 0, 2):207 case IP_VERSION(14, 0, 3):208 return AMD_RESET_METHOD_MODE1;209 default:210 if (amdgpu_dpm_is_baco_supported(adev))211 return AMD_RESET_METHOD_BACO;212 else213 return AMD_RESET_METHOD_MODE1;214 }215}216 217static int soc24_asic_reset(struct amdgpu_device *adev)218{219 int ret = 0;220 221 switch (soc24_asic_reset_method(adev)) {222 case AMD_RESET_METHOD_PCI:223 dev_info(adev->dev, "PCI reset\n");224 ret = amdgpu_device_pci_reset(adev);225 break;226 case AMD_RESET_METHOD_BACO:227 dev_info(adev->dev, "BACO reset\n");228 ret = amdgpu_dpm_baco_reset(adev);229 break;230 case AMD_RESET_METHOD_MODE2:231 dev_info(adev->dev, "MODE2 reset\n");232 ret = amdgpu_dpm_mode2_reset(adev);233 break;234 default:235 dev_info(adev->dev, "MODE1 reset\n");236 ret = amdgpu_device_mode1_reset(adev);237 break;238 }239 240 return ret;241}242 243static void soc24_program_aspm(struct amdgpu_device *adev)244{245 if (!amdgpu_device_should_use_aspm(adev))246 return;247 248 if (!(adev->flags & AMD_IS_APU) &&249 (adev->nbio.funcs->program_aspm))250 adev->nbio.funcs->program_aspm(adev);251}252 253const struct amdgpu_ip_block_version soc24_common_ip_block = {254 .type = AMD_IP_BLOCK_TYPE_COMMON,255 .major = 1,256 .minor = 0,257 .rev = 0,258 .funcs = &soc24_common_ip_funcs,259};260 261static bool soc24_need_full_reset(struct amdgpu_device *adev)262{263 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {264 case IP_VERSION(12, 0, 0):265 case IP_VERSION(12, 0, 1):266 default:267 return true;268 }269}270 271static bool soc24_need_reset_on_init(struct amdgpu_device *adev)272{273 u32 sol_reg;274 275 if (adev->flags & AMD_IS_APU)276 return false;277 278 /* Check sOS sign of life register to confirm sys driver and sOS279 * are already been loaded.280 */281 sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);282 if (sol_reg)283 return true;284 285 return false;286}287 288static uint64_t soc24_get_pcie_replay_count(struct amdgpu_device *adev)289{290 /* TODO291 * dummy implement for pcie_replay_count sysfs interface292 * */293 return 0;294}295 296static void soc24_init_doorbell_index(struct amdgpu_device *adev)297{298 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;299 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;300 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;301 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;302 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;303 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;304 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;305 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;306 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;307 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;308 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;309 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;310 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;311 adev->doorbell_index.gfx_userqueue_start =312 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;313 adev->doorbell_index.gfx_userqueue_end =314 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;315 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;316 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;317 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;318 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;319 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;320 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;321 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;322 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;323 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;324 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;325 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;326 327 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;328 adev->doorbell_index.sdma_doorbell_range = 20;329}330 331static void soc24_pre_asic_init(struct amdgpu_device *adev)332{333}334 335static int soc24_update_umd_stable_pstate(struct amdgpu_device *adev,336 bool enter)337{338 if (enter)339 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);340 else341 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);342 343 if (adev->gfx.funcs->update_perfmon_mgcg)344 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);345 346 return 0;347}348 349static const struct amdgpu_asic_funcs soc24_asic_funcs = {350 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,351 .read_register = &soc24_read_register,352 .reset = &soc24_asic_reset,353 .reset_method = &soc24_asic_reset_method,354 .get_xclk = &soc24_get_xclk,355 .get_config_memsize = &soc24_get_config_memsize,356 .init_doorbell_index = &soc24_init_doorbell_index,357 .need_full_reset = &soc24_need_full_reset,358 .need_reset_on_init = &soc24_need_reset_on_init,359 .get_pcie_replay_count = &soc24_get_pcie_replay_count,360 .supports_baco = &amdgpu_dpm_is_baco_supported,361 .pre_asic_init = &soc24_pre_asic_init,362 .query_video_codecs = &soc24_query_video_codecs,363 .update_umd_stable_pstate = &soc24_update_umd_stable_pstate,364};365 366static int soc24_common_early_init(void *handle)367{368 struct amdgpu_device *adev = (struct amdgpu_device *)handle;369 370 adev->nbio.funcs->set_reg_remap(adev);371 adev->smc_rreg = NULL;372 adev->smc_wreg = NULL;373 adev->pcie_rreg = &amdgpu_device_indirect_rreg;374 adev->pcie_wreg = &amdgpu_device_indirect_wreg;375 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;376 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;377 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;378 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;379 adev->uvd_ctx_rreg = NULL;380 adev->uvd_ctx_wreg = NULL;381 adev->didt_rreg = NULL;382 adev->didt_wreg = NULL;383 384 adev->asic_funcs = &soc24_asic_funcs;385 386 adev->rev_id = amdgpu_device_get_rev_id(adev);387 adev->external_rev_id = 0xff;388 389 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {390 case IP_VERSION(12, 0, 0):391 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |392 AMD_CG_SUPPORT_GFX_CGLS |393 AMD_CG_SUPPORT_GFX_MGCG |394 AMD_CG_SUPPORT_GFX_3D_CGCG |395 AMD_CG_SUPPORT_GFX_3D_CGLS |396 AMD_CG_SUPPORT_REPEATER_FGCG |397 AMD_CG_SUPPORT_GFX_FGCG |398 AMD_CG_SUPPORT_GFX_PERF_CLK |399 AMD_CG_SUPPORT_ATHUB_MGCG |400 AMD_CG_SUPPORT_ATHUB_LS |401 AMD_CG_SUPPORT_MC_MGCG |402 AMD_CG_SUPPORT_HDP_SD |403 AMD_CG_SUPPORT_MC_LS;404 adev->pg_flags = AMD_PG_SUPPORT_VCN |405 AMD_PG_SUPPORT_JPEG |406 AMD_PG_SUPPORT_VCN_DPG;407 adev->external_rev_id = adev->rev_id + 0x40;408 break;409 case IP_VERSION(12, 0, 1):410 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |411 AMD_CG_SUPPORT_GFX_CGLS |412 AMD_CG_SUPPORT_GFX_MGCG |413 AMD_CG_SUPPORT_GFX_3D_CGCG |414 AMD_CG_SUPPORT_GFX_3D_CGLS |415 AMD_CG_SUPPORT_REPEATER_FGCG |416 AMD_CG_SUPPORT_GFX_FGCG |417 AMD_CG_SUPPORT_GFX_PERF_CLK |418 AMD_CG_SUPPORT_ATHUB_MGCG |419 AMD_CG_SUPPORT_ATHUB_LS |420 AMD_CG_SUPPORT_MC_MGCG |421 AMD_CG_SUPPORT_HDP_SD |422 AMD_CG_SUPPORT_MC_LS;423 424 adev->pg_flags = AMD_PG_SUPPORT_VCN |425 AMD_PG_SUPPORT_JPEG |426 AMD_PG_SUPPORT_JPEG_DPG |427 AMD_PG_SUPPORT_VCN_DPG;428 adev->external_rev_id = adev->rev_id + 0x50;429 break;430 default:431 /* FIXME: not supported yet */432 return -EINVAL;433 }434 435 if (amdgpu_sriov_vf(adev)) {436 amdgpu_virt_init_setting(adev);437 xgpu_nv_mailbox_set_irq_funcs(adev);438 }439 440 return 0;441}442 443static int soc24_common_late_init(void *handle)444{445 struct amdgpu_device *adev = (struct amdgpu_device *)handle;446 447 if (amdgpu_sriov_vf(adev))448 xgpu_nv_mailbox_get_irq(adev);449 450 /* Enable selfring doorbell aperture late because doorbell BAR451 * aperture will change if resize BAR successfully in gmc sw_init.452 */453 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);454 455 return 0;456}457 458static int soc24_common_sw_init(void *handle)459{460 struct amdgpu_device *adev = (struct amdgpu_device *)handle;461 462 if (amdgpu_sriov_vf(adev))463 xgpu_nv_mailbox_add_irq_id(adev);464 465 return 0;466}467 468static int soc24_common_sw_fini(void *handle)469{470 return 0;471}472 473static int soc24_common_hw_init(void *handle)474{475 struct amdgpu_device *adev = (struct amdgpu_device *)handle;476 477 /* enable aspm */478 soc24_program_aspm(adev);479 /* setup nbio registers */480 adev->nbio.funcs->init_registers(adev);481 /* remap HDP registers to a hole in mmio space,482 * for the purpose of expose those registers483 * to process space484 */485 if (adev->nbio.funcs->remap_hdp_registers)486 adev->nbio.funcs->remap_hdp_registers(adev);487 488 if (adev->df.funcs->hw_init)489 adev->df.funcs->hw_init(adev);490 491 /* enable the doorbell aperture */492 adev->nbio.funcs->enable_doorbell_aperture(adev, true);493 494 return 0;495}496 497static int soc24_common_hw_fini(void *handle)498{499 struct amdgpu_device *adev = (struct amdgpu_device *)handle;500 501 /* Disable the doorbell aperture and selfring doorbell aperture502 * separately in hw_fini because soc21_enable_doorbell_aperture503 * has been removed and there is no need to delay disabling504 * selfring doorbell.505 */506 adev->nbio.funcs->enable_doorbell_aperture(adev, false);507 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);508 509 if (amdgpu_sriov_vf(adev))510 xgpu_nv_mailbox_put_irq(adev);511 512 return 0;513}514 515static int soc24_common_suspend(void *handle)516{517 struct amdgpu_device *adev = (struct amdgpu_device *)handle;518 519 return soc24_common_hw_fini(adev);520}521 522static int soc24_common_resume(void *handle)523{524 struct amdgpu_device *adev = (struct amdgpu_device *)handle;525 526 return soc24_common_hw_init(adev);527}528 529static bool soc24_common_is_idle(void *handle)530{531 return true;532}533 534static int soc24_common_wait_for_idle(void *handle)535{536 return 0;537}538 539static int soc24_common_soft_reset(void *handle)540{541 return 0;542}543 544static int soc24_common_set_clockgating_state(void *handle,545 enum amd_clockgating_state state)546{547 struct amdgpu_device *adev = (struct amdgpu_device *)handle;548 549 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {550 case IP_VERSION(6, 3, 1):551 adev->nbio.funcs->update_medium_grain_clock_gating(adev,552 state == AMD_CG_STATE_GATE);553 adev->nbio.funcs->update_medium_grain_light_sleep(adev,554 state == AMD_CG_STATE_GATE);555 adev->hdp.funcs->update_clock_gating(adev,556 state == AMD_CG_STATE_GATE);557 break;558 default:559 break;560 }561 return 0;562}563 564static int soc24_common_set_powergating_state(void *handle,565 enum amd_powergating_state state)566{567 struct amdgpu_device *adev = (struct amdgpu_device *)handle;568 569 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {570 case IP_VERSION(7, 0, 0):571 case IP_VERSION(7, 0, 1):572 adev->lsdma.funcs->update_memory_power_gating(adev,573 state == AMD_PG_STATE_GATE);574 break;575 default:576 break;577 }578 579 return 0;580}581 582static void soc24_common_get_clockgating_state(void *handle, u64 *flags)583{584 struct amdgpu_device *adev = (struct amdgpu_device *)handle;585 586 adev->nbio.funcs->get_clockgating_state(adev, flags);587 588 adev->hdp.funcs->get_clock_gating_state(adev, flags);589 590 return;591}592 593static const struct amd_ip_funcs soc24_common_ip_funcs = {594 .name = "soc24_common",595 .early_init = soc24_common_early_init,596 .late_init = soc24_common_late_init,597 .sw_init = soc24_common_sw_init,598 .sw_fini = soc24_common_sw_fini,599 .hw_init = soc24_common_hw_init,600 .hw_fini = soc24_common_hw_fini,601 .suspend = soc24_common_suspend,602 .resume = soc24_common_resume,603 .is_idle = soc24_common_is_idle,604 .wait_for_idle = soc24_common_wait_for_idle,605 .soft_reset = soc24_common_soft_reset,606 .set_clockgating_state = soc24_common_set_clockgating_state,607 .set_powergating_state = soc24_common_set_powergating_state,608 .get_clockgating_state = soc24_common_get_clockgating_state,609};610