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1/*2 * Copyright 2022 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23#ifndef __UMC_V8_10_H__24#define __UMC_V8_10_H__25 26#include "soc15_common.h"27#include "amdgpu.h"28 29/* number of umc channel instance with memory map register access */30#define UMC_V8_10_CHANNEL_INSTANCE_NUM 231/* number of umc instance with memory map register access */32#define UMC_V8_10_UMC_INSTANCE_NUM 233 34/* Total channel instances for all available umc nodes */35#define UMC_V8_10_TOTAL_CHANNEL_NUM(adev) \36 (UMC_V8_10_CHANNEL_INSTANCE_NUM * UMC_V8_10_UMC_INSTANCE_NUM * \37 (adev)->gmc.num_umc - hweight32((adev)->gmc.m_half_use) * 2)38 39/* UMC regiser per channel offset */40#define UMC_V8_10_PER_CHANNEL_OFFSET 0x40041 42/* EccErrCnt max value */43#define UMC_V8_10_CE_CNT_MAX 0xffff44/* umc ce interrupt threshold */45#define UUMC_V8_10_CE_INT_THRESHOLD 0xffff46/* umc ce count initial value */47#define UMC_V8_10_CE_CNT_INIT (UMC_V8_10_CE_CNT_MAX - UUMC_V8_10_CE_INT_THRESHOLD)48 49#define UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM 450 51/* The C5 bit in NA address */52#define UMC_V8_10_NA_C5_BIT 1453 54/* Map to swizzle mode address */55#define SWIZZLE_MODE_TMP_ADDR(na, ch_num, ch_idx) \56 ((((na) >> 10) * (ch_num) + (ch_idx)) << 10)57#define SWIZZLE_MODE_ADDR_HI(addr, col_bit) \58 (((addr) >> ((col_bit) + 2)) << ((col_bit) + 2))59#define SWIZZLE_MODE_ADDR_MID(na, col_bit) ((((na) >> 8) & 0x3) << (col_bit))60#define SWIZZLE_MODE_ADDR_LOW(addr, col_bit) \61 ((((addr) >> 10) & ((0x1ULL << (col_bit - 8)) - 1)) << 8)62#define SWIZZLE_MODE_ADDR_LSB(na) ((na) & 0xFF)63 64extern struct amdgpu_umc_ras umc_v8_10_ras;65extern const uint32_t66 umc_v8_10_channel_idx_tbl[]67 [UMC_V8_10_UMC_INSTANCE_NUM]68 [UMC_V8_10_CHANNEL_INSTANCE_NUM];69 70extern const uint32_t71 umc_v8_10_channel_idx_tbl_ext0[]72 [UMC_V8_10_UMC_INSTANCE_NUM]73 [UMC_V8_10_CHANNEL_INSTANCE_NUM];74#endif75 76