52 lines · c
1/*2 * Copyright 2020 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23#ifndef __UMC_V8_7_H__24#define __UMC_V8_7_H__25 26#include "soc15_common.h"27#include "amdgpu.h"28 29/* HBM Memory Channel Width */30#define UMC_V8_7_HBM_MEMORY_CHANNEL_WIDTH 12831/* number of umc channel instance with memory map register access */32#define UMC_V8_7_CHANNEL_INSTANCE_NUM 233/* number of umc instance with memory map register access */34#define UMC_V8_7_UMC_INSTANCE_NUM 835/* total channel instances in one umc block */36#define UMC_V8_7_TOTAL_CHANNEL_NUM (UMC_V8_7_CHANNEL_INSTANCE_NUM * UMC_V8_7_UMC_INSTANCE_NUM)37/* UMC regiser per channel offset */38#define UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA 0x40039 40/* EccErrCnt max value */41#define UMC_V8_7_CE_CNT_MAX 0xffff42/* umc ce interrupt threshold */43#define UMC_V8_7_CE_INT_THRESHOLD 0xffff44/* umc ce count initial value */45#define UMC_V8_7_CE_CNT_INIT (UMC_V8_7_CE_CNT_MAX - UMC_V8_7_CE_INT_THRESHOLD)46 47extern struct amdgpu_umc_ras umc_v8_7_ras;48extern const uint32_t49 umc_v8_7_channel_idx_tbl[UMC_V8_7_UMC_INSTANCE_NUM][UMC_V8_7_CHANNEL_INSTANCE_NUM];50 51#endif52