2210 lines · c
1/*2 * Copyright 2018 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#include <linux/firmware.h>25#include <drm/drm_drv.h>26 27#include "amdgpu.h"28#include "amdgpu_vcn.h"29#include "soc15.h"30#include "soc15d.h"31#include "amdgpu_pm.h"32#include "amdgpu_psp.h"33#include "mmsch_v2_0.h"34#include "vcn_v2_0.h"35 36#include "vcn/vcn_2_0_0_offset.h"37#include "vcn/vcn_2_0_0_sh_mask.h"38#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"39 40#define VCN_VID_SOC_ADDRESS_2_0 0x1fa0041#define VCN1_VID_SOC_ADDRESS_3_0 0x4820042 43#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd44#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x50345#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x50446#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x50547#define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f48#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a49#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d50 51#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e152#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a653#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a754#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e255 56static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = {57 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),63 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)90};91 92static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);93static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);94static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);95static int vcn_v2_0_set_powergating_state(void *handle,96 enum amd_powergating_state state);97static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,98 int inst_idx, struct dpg_pause_state *new_state);99static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);100/**101 * vcn_v2_0_early_init - set function pointers and load microcode102 *103 * @handle: amdgpu_device pointer104 *105 * Set ring and irq function pointers106 * Load microcode from filesystem107 */108static int vcn_v2_0_early_init(void *handle)109{110 struct amdgpu_device *adev = (struct amdgpu_device *)handle;111 112 if (amdgpu_sriov_vf(adev))113 adev->vcn.num_enc_rings = 1;114 else115 adev->vcn.num_enc_rings = 2;116 117 vcn_v2_0_set_dec_ring_funcs(adev);118 vcn_v2_0_set_enc_ring_funcs(adev);119 vcn_v2_0_set_irq_funcs(adev);120 121 return amdgpu_vcn_early_init(adev);122}123 124/**125 * vcn_v2_0_sw_init - sw init for VCN block126 *127 * @handle: amdgpu_device pointer128 *129 * Load firmware and sw initialization130 */131static int vcn_v2_0_sw_init(void *handle)132{133 struct amdgpu_ring *ring;134 int i, r;135 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);136 uint32_t *ptr;137 struct amdgpu_device *adev = (struct amdgpu_device *)handle;138 volatile struct amdgpu_fw_shared *fw_shared;139 140 /* VCN DEC TRAP */141 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,142 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,143 &adev->vcn.inst->irq);144 if (r)145 return r;146 147 /* VCN ENC TRAP */148 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {149 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,150 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,151 &adev->vcn.inst->irq);152 if (r)153 return r;154 }155 156 r = amdgpu_vcn_sw_init(adev);157 if (r)158 return r;159 160 amdgpu_vcn_setup_ucode(adev);161 162 r = amdgpu_vcn_resume(adev);163 if (r)164 return r;165 166 ring = &adev->vcn.inst->ring_dec;167 168 ring->use_doorbell = true;169 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;170 ring->vm_hub = AMDGPU_MMHUB0(0);171 172 sprintf(ring->name, "vcn_dec");173 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,174 AMDGPU_RING_PRIO_DEFAULT, NULL);175 if (r)176 return r;177 178 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;179 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;180 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;181 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;182 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;183 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;184 185 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;186 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);187 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;188 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);189 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;190 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);191 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;192 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);193 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;194 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);195 196 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {197 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);198 199 ring = &adev->vcn.inst->ring_enc[i];200 ring->use_doorbell = true;201 ring->vm_hub = AMDGPU_MMHUB0(0);202 if (!amdgpu_sriov_vf(adev))203 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;204 else205 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;206 sprintf(ring->name, "vcn_enc%d", i);207 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,208 hw_prio, NULL);209 if (r)210 return r;211 }212 213 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;214 215 r = amdgpu_virt_alloc_mm_table(adev);216 if (r)217 return r;218 219 fw_shared = adev->vcn.inst->fw_shared.cpu_addr;220 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);221 222 if (amdgpu_vcnfw_log)223 amdgpu_vcn_fwlog_init(adev->vcn.inst);224 225 /* Allocate memory for VCN IP Dump buffer */226 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);227 if (!ptr) {228 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");229 adev->vcn.ip_dump = NULL;230 } else {231 adev->vcn.ip_dump = ptr;232 }233 234 return 0;235}236 237/**238 * vcn_v2_0_sw_fini - sw fini for VCN block239 *240 * @handle: amdgpu_device pointer241 *242 * VCN suspend and free up sw allocation243 */244static int vcn_v2_0_sw_fini(void *handle)245{246 int r, idx;247 struct amdgpu_device *adev = (struct amdgpu_device *)handle;248 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;249 250 if (drm_dev_enter(adev_to_drm(adev), &idx)) {251 fw_shared->present_flag_0 = 0;252 drm_dev_exit(idx);253 }254 255 amdgpu_virt_free_mm_table(adev);256 257 r = amdgpu_vcn_suspend(adev);258 if (r)259 return r;260 261 r = amdgpu_vcn_sw_fini(adev);262 263 kfree(adev->vcn.ip_dump);264 265 return r;266}267 268/**269 * vcn_v2_0_hw_init - start and test VCN block270 *271 * @handle: amdgpu_device pointer272 *273 * Initialize the hardware, boot up the VCPU and do some testing274 */275static int vcn_v2_0_hw_init(void *handle)276{277 struct amdgpu_device *adev = (struct amdgpu_device *)handle;278 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;279 int i, r;280 281 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,282 ring->doorbell_index, 0);283 284 if (amdgpu_sriov_vf(adev))285 vcn_v2_0_start_sriov(adev);286 287 r = amdgpu_ring_test_helper(ring);288 if (r)289 return r;290 291 //Disable vcn decode for sriov292 if (amdgpu_sriov_vf(adev))293 ring->sched.ready = false;294 295 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {296 ring = &adev->vcn.inst->ring_enc[i];297 r = amdgpu_ring_test_helper(ring);298 if (r)299 return r;300 }301 302 return 0;303}304 305/**306 * vcn_v2_0_hw_fini - stop the hardware block307 *308 * @handle: amdgpu_device pointer309 *310 * Stop the VCN block, mark ring as not ready any more311 */312static int vcn_v2_0_hw_fini(void *handle)313{314 struct amdgpu_device *adev = (struct amdgpu_device *)handle;315 316 cancel_delayed_work_sync(&adev->vcn.idle_work);317 318 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||319 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&320 RREG32_SOC15(VCN, 0, mmUVD_STATUS)))321 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);322 323 return 0;324}325 326/**327 * vcn_v2_0_suspend - suspend VCN block328 *329 * @handle: amdgpu_device pointer330 *331 * HW fini and suspend VCN block332 */333static int vcn_v2_0_suspend(void *handle)334{335 int r;336 struct amdgpu_device *adev = (struct amdgpu_device *)handle;337 338 r = vcn_v2_0_hw_fini(adev);339 if (r)340 return r;341 342 r = amdgpu_vcn_suspend(adev);343 344 return r;345}346 347/**348 * vcn_v2_0_resume - resume VCN block349 *350 * @handle: amdgpu_device pointer351 *352 * Resume firmware and hw init VCN block353 */354static int vcn_v2_0_resume(void *handle)355{356 int r;357 struct amdgpu_device *adev = (struct amdgpu_device *)handle;358 359 r = amdgpu_vcn_resume(adev);360 if (r)361 return r;362 363 r = vcn_v2_0_hw_init(adev);364 365 return r;366}367 368/**369 * vcn_v2_0_mc_resume - memory controller programming370 *371 * @adev: amdgpu_device pointer372 *373 * Let the VCN memory controller know it's offsets374 */375static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)376{377 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);378 uint32_t offset;379 380 if (amdgpu_sriov_vf(adev))381 return;382 383 /* cache window 0: fw */384 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {385 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,386 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));387 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,388 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));389 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);390 offset = 0;391 } else {392 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,393 lower_32_bits(adev->vcn.inst->gpu_addr));394 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,395 upper_32_bits(adev->vcn.inst->gpu_addr));396 offset = size;397 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,398 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);399 }400 401 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);402 403 /* cache window 1: stack */404 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,405 lower_32_bits(adev->vcn.inst->gpu_addr + offset));406 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,407 upper_32_bits(adev->vcn.inst->gpu_addr + offset));408 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);409 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);410 411 /* cache window 2: context */412 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,413 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));414 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,415 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));416 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);417 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);418 419 /* non-cache window */420 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,421 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr));422 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,423 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr));424 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0);425 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0,426 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));427 428 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);429}430 431static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)432{433 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);434 uint32_t offset;435 436 /* cache window 0: fw */437 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {438 if (!indirect) {439 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(440 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),441 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);442 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(443 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),444 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);445 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(446 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);447 } else {448 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(449 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);450 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(451 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);452 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(453 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);454 }455 offset = 0;456 } else {457 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(458 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),459 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);460 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(461 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),462 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);463 offset = size;464 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(465 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),466 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);467 }468 469 if (!indirect)470 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(471 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);472 else473 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(474 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);475 476 /* cache window 1: stack */477 if (!indirect) {478 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(479 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),480 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);481 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(482 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),483 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);484 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(485 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);486 } else {487 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(488 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);489 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(490 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);491 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(492 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);493 }494 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(495 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);496 497 /* cache window 2: context */498 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(499 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),500 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);501 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(502 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),503 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);504 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(505 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);506 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(507 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);508 509 /* non-cache window */510 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(511 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),512 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);513 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(514 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),515 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);516 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(517 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);518 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(519 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0),520 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);521 522 /* VCN global tiling registers */523 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(524 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);525}526 527/**528 * vcn_v2_0_disable_clock_gating - disable VCN clock gating529 *530 * @adev: amdgpu_device pointer531 *532 * Disable clock gating for VCN block533 */534static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)535{536 uint32_t data;537 538 if (amdgpu_sriov_vf(adev))539 return;540 541 /* UVD disable CGC */542 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);543 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)544 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;545 else546 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;547 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;548 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;549 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);550 551 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);552 data &= ~(UVD_CGC_GATE__SYS_MASK553 | UVD_CGC_GATE__UDEC_MASK554 | UVD_CGC_GATE__MPEG2_MASK555 | UVD_CGC_GATE__REGS_MASK556 | UVD_CGC_GATE__RBC_MASK557 | UVD_CGC_GATE__LMI_MC_MASK558 | UVD_CGC_GATE__LMI_UMC_MASK559 | UVD_CGC_GATE__IDCT_MASK560 | UVD_CGC_GATE__MPRD_MASK561 | UVD_CGC_GATE__MPC_MASK562 | UVD_CGC_GATE__LBSI_MASK563 | UVD_CGC_GATE__LRBBM_MASK564 | UVD_CGC_GATE__UDEC_RE_MASK565 | UVD_CGC_GATE__UDEC_CM_MASK566 | UVD_CGC_GATE__UDEC_IT_MASK567 | UVD_CGC_GATE__UDEC_DB_MASK568 | UVD_CGC_GATE__UDEC_MP_MASK569 | UVD_CGC_GATE__WCB_MASK570 | UVD_CGC_GATE__VCPU_MASK571 | UVD_CGC_GATE__SCPU_MASK);572 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);573 574 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);575 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK576 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK577 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK578 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK579 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK580 | UVD_CGC_CTRL__SYS_MODE_MASK581 | UVD_CGC_CTRL__UDEC_MODE_MASK582 | UVD_CGC_CTRL__MPEG2_MODE_MASK583 | UVD_CGC_CTRL__REGS_MODE_MASK584 | UVD_CGC_CTRL__RBC_MODE_MASK585 | UVD_CGC_CTRL__LMI_MC_MODE_MASK586 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK587 | UVD_CGC_CTRL__IDCT_MODE_MASK588 | UVD_CGC_CTRL__MPRD_MODE_MASK589 | UVD_CGC_CTRL__MPC_MODE_MASK590 | UVD_CGC_CTRL__LBSI_MODE_MASK591 | UVD_CGC_CTRL__LRBBM_MODE_MASK592 | UVD_CGC_CTRL__WCB_MODE_MASK593 | UVD_CGC_CTRL__VCPU_MODE_MASK594 | UVD_CGC_CTRL__SCPU_MODE_MASK);595 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);596 597 /* turn on */598 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);599 data |= (UVD_SUVD_CGC_GATE__SRE_MASK600 | UVD_SUVD_CGC_GATE__SIT_MASK601 | UVD_SUVD_CGC_GATE__SMP_MASK602 | UVD_SUVD_CGC_GATE__SCM_MASK603 | UVD_SUVD_CGC_GATE__SDB_MASK604 | UVD_SUVD_CGC_GATE__SRE_H264_MASK605 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK606 | UVD_SUVD_CGC_GATE__SIT_H264_MASK607 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK608 | UVD_SUVD_CGC_GATE__SCM_H264_MASK609 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK610 | UVD_SUVD_CGC_GATE__SDB_H264_MASK611 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK612 | UVD_SUVD_CGC_GATE__SCLR_MASK613 | UVD_SUVD_CGC_GATE__UVD_SC_MASK614 | UVD_SUVD_CGC_GATE__ENT_MASK615 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK616 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK617 | UVD_SUVD_CGC_GATE__SITE_MASK618 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK619 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK620 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK621 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK622 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);623 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);624 625 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);626 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK627 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK628 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK629 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK630 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK631 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK632 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK633 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK634 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK635 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);636 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);637}638 639static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,640 uint8_t sram_sel, uint8_t indirect)641{642 uint32_t reg_data = 0;643 644 /* enable sw clock gating control */645 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)646 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;647 else648 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;649 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;650 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;651 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |652 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |653 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |654 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |655 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |656 UVD_CGC_CTRL__SYS_MODE_MASK |657 UVD_CGC_CTRL__UDEC_MODE_MASK |658 UVD_CGC_CTRL__MPEG2_MODE_MASK |659 UVD_CGC_CTRL__REGS_MODE_MASK |660 UVD_CGC_CTRL__RBC_MODE_MASK |661 UVD_CGC_CTRL__LMI_MC_MODE_MASK |662 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |663 UVD_CGC_CTRL__IDCT_MODE_MASK |664 UVD_CGC_CTRL__MPRD_MODE_MASK |665 UVD_CGC_CTRL__MPC_MODE_MASK |666 UVD_CGC_CTRL__LBSI_MODE_MASK |667 UVD_CGC_CTRL__LRBBM_MODE_MASK |668 UVD_CGC_CTRL__WCB_MODE_MASK |669 UVD_CGC_CTRL__VCPU_MODE_MASK |670 UVD_CGC_CTRL__SCPU_MODE_MASK);671 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(672 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);673 674 /* turn off clock gating */675 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(676 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);677 678 /* turn on SUVD clock gating */679 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(680 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);681 682 /* turn on sw mode in UVD_SUVD_CGC_CTRL */683 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(684 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);685}686 687/**688 * vcn_v2_0_enable_clock_gating - enable VCN clock gating689 *690 * @adev: amdgpu_device pointer691 *692 * Enable clock gating for VCN block693 */694static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)695{696 uint32_t data = 0;697 698 if (amdgpu_sriov_vf(adev))699 return;700 701 /* enable UVD CGC */702 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);703 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)704 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;705 else706 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;707 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;708 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;709 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);710 711 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);712 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK713 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK714 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK715 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK716 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK717 | UVD_CGC_CTRL__SYS_MODE_MASK718 | UVD_CGC_CTRL__UDEC_MODE_MASK719 | UVD_CGC_CTRL__MPEG2_MODE_MASK720 | UVD_CGC_CTRL__REGS_MODE_MASK721 | UVD_CGC_CTRL__RBC_MODE_MASK722 | UVD_CGC_CTRL__LMI_MC_MODE_MASK723 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK724 | UVD_CGC_CTRL__IDCT_MODE_MASK725 | UVD_CGC_CTRL__MPRD_MODE_MASK726 | UVD_CGC_CTRL__MPC_MODE_MASK727 | UVD_CGC_CTRL__LBSI_MODE_MASK728 | UVD_CGC_CTRL__LRBBM_MODE_MASK729 | UVD_CGC_CTRL__WCB_MODE_MASK730 | UVD_CGC_CTRL__VCPU_MODE_MASK731 | UVD_CGC_CTRL__SCPU_MODE_MASK);732 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);733 734 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);735 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK736 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK737 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK738 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK739 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK740 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK741 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK742 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK743 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK744 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);745 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);746}747 748static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)749{750 uint32_t data = 0;751 752 if (amdgpu_sriov_vf(adev))753 return;754 755 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {756 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT757 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT758 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT759 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT760 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT761 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT762 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT763 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT764 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT765 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);766 767 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);768 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,769 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF);770 } else {771 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT772 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT773 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT774 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT775 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT776 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT777 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT778 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT779 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT780 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);781 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);782 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF);783 }784 785 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,786 * UVDU_PWR_STATUS are 0 (power on) */787 788 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);789 data &= ~0x103;790 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)791 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |792 UVD_POWER_STATUS__UVD_PG_EN_MASK;793 794 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);795}796 797static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)798{799 uint32_t data = 0;800 801 if (amdgpu_sriov_vf(adev))802 return;803 804 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {805 /* Before power off, this indicator has to be turned on */806 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);807 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;808 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;809 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);810 811 812 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT813 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT814 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT815 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT816 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT817 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT818 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT819 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT820 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT821 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);822 823 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);824 825 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT826 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT827 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT828 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT829 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT830 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT831 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT832 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT833 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT834 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);835 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF);836 }837}838 839static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)840{841 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;842 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;843 uint32_t rb_bufsz, tmp;844 845 vcn_v2_0_enable_static_power_gating(adev);846 847 /* enable dynamic power gating mode */848 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);849 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;850 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;851 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);852 853 if (indirect)854 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr;855 856 /* enable clock gating */857 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);858 859 /* enable VCPU clock */860 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);861 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;862 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;863 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(864 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);865 866 /* disable master interupt */867 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(868 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);869 870 /* setup mmUVD_LMI_CTRL */871 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |872 UVD_LMI_CTRL__REQ_MODE_MASK |873 UVD_LMI_CTRL__CRC_RESET_MASK |874 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |875 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |876 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |877 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |878 0x00100000L);879 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(880 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);881 882 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(883 UVD, 0, mmUVD_MPC_CNTL),884 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);885 886 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(887 UVD, 0, mmUVD_MPC_SET_MUXA0),888 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |889 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |890 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |891 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);892 893 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(894 UVD, 0, mmUVD_MPC_SET_MUXB0),895 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |896 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |897 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |898 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);899 900 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(901 UVD, 0, mmUVD_MPC_SET_MUX),902 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |903 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |904 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);905 906 vcn_v2_0_mc_resume_dpg_mode(adev, indirect);907 908 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(909 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);910 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(911 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);912 913 /* release VCPU reset to boot */914 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(915 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);916 917 /* enable LMI MC and UMC channels */918 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(919 UVD, 0, mmUVD_LMI_CTRL2),920 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);921 922 /* enable master interrupt */923 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(924 UVD, 0, mmUVD_MASTINT_EN),925 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);926 927 if (indirect)928 amdgpu_vcn_psp_update_sram(adev, 0, 0);929 930 /* force RBC into idle state */931 rb_bufsz = order_base_2(ring->ring_size);932 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);933 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);934 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);935 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);936 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);937 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);938 939 /* Stall DPG before WPTR/RPTR reset */940 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),941 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,942 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);943 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;944 945 /* set the write pointer delay */946 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);947 948 /* set the wb address */949 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,950 (upper_32_bits(ring->gpu_addr) >> 2));951 952 /* program the RB_BASE for ring buffer */953 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,954 lower_32_bits(ring->gpu_addr));955 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,956 upper_32_bits(ring->gpu_addr));957 958 /* Initialize the ring buffer's read and write pointers */959 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);960 961 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);962 963 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);964 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,965 lower_32_bits(ring->wptr));966 967 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;968 /* Unstall DPG */969 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),970 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);971 return 0;972}973 974static int vcn_v2_0_start(struct amdgpu_device *adev)975{976 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;977 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;978 uint32_t rb_bufsz, tmp;979 uint32_t lmi_swap_cntl;980 int i, j, r;981 982 if (adev->pm.dpm_enabled)983 amdgpu_dpm_enable_uvd(adev, true);984 985 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)986 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);987 988 vcn_v2_0_disable_static_power_gating(adev);989 990 /* set uvd status busy */991 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;992 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);993 994 /*SW clock gating */995 vcn_v2_0_disable_clock_gating(adev);996 997 /* enable VCPU clock */998 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),999 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);1000 1001 /* disable master interrupt */1002 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,1003 ~UVD_MASTINT_EN__VCPU_EN_MASK);1004 1005 /* setup mmUVD_LMI_CTRL */1006 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);1007 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |1008 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |1009 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |1010 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |1011 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);1012 1013 /* setup mmUVD_MPC_CNTL */1014 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);1015 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;1016 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;1017 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);1018 1019 /* setup UVD_MPC_SET_MUXA0 */1020 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,1021 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |1022 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |1023 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |1024 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));1025 1026 /* setup UVD_MPC_SET_MUXB0 */1027 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,1028 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |1029 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |1030 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |1031 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));1032 1033 /* setup mmUVD_MPC_SET_MUX */1034 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,1035 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |1036 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |1037 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));1038 1039 vcn_v2_0_mc_resume(adev);1040 1041 /* release VCPU reset to boot */1042 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,1043 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);1044 1045 /* enable LMI MC and UMC channels */1046 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,1047 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);1048 1049 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);1050 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;1051 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;1052 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);1053 1054 /* disable byte swapping */1055 lmi_swap_cntl = 0;1056#ifdef __BIG_ENDIAN1057 /* swap (8 in 32) RB and IB */1058 lmi_swap_cntl = 0xa;1059#endif1060 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);1061 1062 for (i = 0; i < 10; ++i) {1063 uint32_t status;1064 1065 for (j = 0; j < 100; ++j) {1066 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);1067 if (status & 2)1068 break;1069 mdelay(10);1070 }1071 r = 0;1072 if (status & 2)1073 break;1074 1075 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");1076 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),1077 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,1078 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);1079 mdelay(10);1080 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,1081 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);1082 mdelay(10);1083 r = -1;1084 }1085 1086 if (r) {1087 DRM_ERROR("VCN decode not responding, giving up!!!\n");1088 return r;1089 }1090 1091 /* enable master interrupt */1092 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),1093 UVD_MASTINT_EN__VCPU_EN_MASK,1094 ~UVD_MASTINT_EN__VCPU_EN_MASK);1095 1096 /* clear the busy bit of VCN_STATUS */1097 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,1098 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));1099 1100 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);1101 1102 /* force RBC into idle state */1103 rb_bufsz = order_base_2(ring->ring_size);1104 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);1105 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);1106 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);1107 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);1108 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);1109 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);1110 1111 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;1112 /* program the RB_BASE for ring buffer */1113 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,1114 lower_32_bits(ring->gpu_addr));1115 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,1116 upper_32_bits(ring->gpu_addr));1117 1118 /* Initialize the ring buffer's read and write pointers */1119 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);1120 1121 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);1122 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,1123 lower_32_bits(ring->wptr));1124 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;1125 1126 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;1127 ring = &adev->vcn.inst->ring_enc[0];1128 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));1129 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));1130 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);1131 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));1132 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);1133 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;1134 1135 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;1136 ring = &adev->vcn.inst->ring_enc[1];1137 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));1138 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));1139 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);1140 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));1141 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);1142 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;1143 1144 return 0;1145}1146 1147static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)1148{1149 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};1150 uint32_t tmp;1151 1152 vcn_v2_0_pause_dpg_mode(adev, 0, &state);1153 /* Wait for power status to be 1 */1154 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,1155 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);1156 1157 /* wait for read ptr to be equal to write ptr */1158 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);1159 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);1160 1161 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);1162 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);1163 1164 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;1165 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);1166 1167 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,1168 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);1169 1170 /* disable dynamic power gating mode */1171 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,1172 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);1173 1174 return 0;1175}1176 1177static int vcn_v2_0_stop(struct amdgpu_device *adev)1178{1179 uint32_t tmp;1180 int r;1181 1182 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {1183 r = vcn_v2_0_stop_dpg_mode(adev);1184 if (r)1185 return r;1186 goto power_off;1187 }1188 1189 /* wait for uvd idle */1190 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);1191 if (r)1192 return r;1193 1194 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |1195 UVD_LMI_STATUS__READ_CLEAN_MASK |1196 UVD_LMI_STATUS__WRITE_CLEAN_MASK |1197 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;1198 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);1199 if (r)1200 return r;1201 1202 /* stall UMC channel */1203 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);1204 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;1205 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);1206 1207 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|1208 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;1209 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);1210 if (r)1211 return r;1212 1213 /* disable VCPU clock */1214 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,1215 ~(UVD_VCPU_CNTL__CLK_EN_MASK));1216 1217 /* reset LMI UMC */1218 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),1219 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,1220 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);1221 1222 /* reset LMI */1223 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),1224 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,1225 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);1226 1227 /* reset VCPU */1228 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),1229 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,1230 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);1231 1232 /* clear status */1233 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);1234 1235 vcn_v2_0_enable_clock_gating(adev);1236 vcn_v2_0_enable_static_power_gating(adev);1237 1238power_off:1239 if (adev->pm.dpm_enabled)1240 amdgpu_dpm_enable_uvd(adev, false);1241 1242 return 0;1243}1244 1245static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,1246 int inst_idx, struct dpg_pause_state *new_state)1247{1248 struct amdgpu_ring *ring;1249 uint32_t reg_data = 0;1250 int ret_code;1251 1252 /* pause/unpause if state is changed */1253 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {1254 DRM_DEBUG("dpg pause state changed %d -> %d",1255 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);1256 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &1257 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);1258 1259 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {1260 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,1261 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);1262 1263 if (!ret_code) {1264 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;1265 /* pause DPG */1266 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;1267 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);1268 1269 /* wait for ACK */1270 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,1271 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,1272 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);1273 1274 /* Stall DPG before WPTR/RPTR reset */1275 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),1276 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,1277 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);1278 /* Restore */1279 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;1280 ring = &adev->vcn.inst->ring_enc[0];1281 ring->wptr = 0;1282 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);1283 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));1284 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);1285 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));1286 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));1287 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;1288 1289 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;1290 ring = &adev->vcn.inst->ring_enc[1];1291 ring->wptr = 0;1292 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);1293 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));1294 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);1295 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));1296 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));1297 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;1298 1299 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;1300 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,1301 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);1302 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;1303 /* Unstall DPG */1304 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),1305 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);1306 1307 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,1308 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,1309 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);1310 }1311 } else {1312 /* unpause dpg, no need to wait */1313 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;1314 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);1315 }1316 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;1317 }1318 1319 return 0;1320}1321 1322static bool vcn_v2_0_is_idle(void *handle)1323{1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1325 1326 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);1327}1328 1329static int vcn_v2_0_wait_for_idle(void *handle)1330{1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1332 int ret;1333 1334 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,1335 UVD_STATUS__IDLE);1336 1337 return ret;1338}1339 1340static int vcn_v2_0_set_clockgating_state(void *handle,1341 enum amd_clockgating_state state)1342{1343 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1344 bool enable = (state == AMD_CG_STATE_GATE);1345 1346 if (amdgpu_sriov_vf(adev))1347 return 0;1348 1349 if (enable) {1350 /* wait for STATUS to clear */1351 if (!vcn_v2_0_is_idle(handle))1352 return -EBUSY;1353 vcn_v2_0_enable_clock_gating(adev);1354 } else {1355 /* disable HW gating and enable Sw gating */1356 vcn_v2_0_disable_clock_gating(adev);1357 }1358 return 0;1359}1360 1361/**1362 * vcn_v2_0_dec_ring_get_rptr - get read pointer1363 *1364 * @ring: amdgpu_ring pointer1365 *1366 * Returns the current hardware read pointer1367 */1368static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)1369{1370 struct amdgpu_device *adev = ring->adev;1371 1372 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);1373}1374 1375/**1376 * vcn_v2_0_dec_ring_get_wptr - get write pointer1377 *1378 * @ring: amdgpu_ring pointer1379 *1380 * Returns the current hardware write pointer1381 */1382static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)1383{1384 struct amdgpu_device *adev = ring->adev;1385 1386 if (ring->use_doorbell)1387 return *ring->wptr_cpu_addr;1388 else1389 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);1390}1391 1392/**1393 * vcn_v2_0_dec_ring_set_wptr - set write pointer1394 *1395 * @ring: amdgpu_ring pointer1396 *1397 * Commits the write pointer to the hardware1398 */1399static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)1400{1401 struct amdgpu_device *adev = ring->adev;1402 1403 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)1404 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,1405 lower_32_bits(ring->wptr) | 0x80000000);1406 1407 if (ring->use_doorbell) {1408 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);1409 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));1410 } else {1411 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));1412 }1413}1414 1415/**1416 * vcn_v2_0_dec_ring_insert_start - insert a start command1417 *1418 * @ring: amdgpu_ring pointer1419 *1420 * Write a start command to the ring.1421 */1422void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)1423{1424 struct amdgpu_device *adev = ring->adev;1425 1426 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));1427 amdgpu_ring_write(ring, 0);1428 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));1429 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));1430}1431 1432/**1433 * vcn_v2_0_dec_ring_insert_end - insert a end command1434 *1435 * @ring: amdgpu_ring pointer1436 *1437 * Write a end command to the ring.1438 */1439void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)1440{1441 struct amdgpu_device *adev = ring->adev;1442 1443 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));1444 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));1445}1446 1447/**1448 * vcn_v2_0_dec_ring_insert_nop - insert a nop command1449 *1450 * @ring: amdgpu_ring pointer1451 * @count: the number of NOP packets to insert1452 *1453 * Write a nop command to the ring.1454 */1455void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)1456{1457 struct amdgpu_device *adev = ring->adev;1458 int i;1459 1460 WARN_ON(ring->wptr % 2 || count % 2);1461 1462 for (i = 0; i < count / 2; i++) {1463 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));1464 amdgpu_ring_write(ring, 0);1465 }1466}1467 1468/**1469 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command1470 *1471 * @ring: amdgpu_ring pointer1472 * @addr: address1473 * @seq: sequence number1474 * @flags: fence related flags1475 *1476 * Write a fence and a trap command to the ring.1477 */1478void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,1479 unsigned flags)1480{1481 struct amdgpu_device *adev = ring->adev;1482 1483 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);1484 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));1485 amdgpu_ring_write(ring, seq);1486 1487 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));1488 amdgpu_ring_write(ring, addr & 0xffffffff);1489 1490 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));1491 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);1492 1493 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));1494 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));1495 1496 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));1497 amdgpu_ring_write(ring, 0);1498 1499 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));1500 amdgpu_ring_write(ring, 0);1501 1502 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));1503 1504 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));1505}1506 1507/**1508 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer1509 *1510 * @ring: amdgpu_ring pointer1511 * @job: job to retrieve vmid from1512 * @ib: indirect buffer to execute1513 * @flags: unused1514 *1515 * Write ring commands to execute the indirect buffer1516 */1517void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,1518 struct amdgpu_job *job,1519 struct amdgpu_ib *ib,1520 uint32_t flags)1521{1522 struct amdgpu_device *adev = ring->adev;1523 unsigned vmid = AMDGPU_JOB_GET_VMID(job);1524 1525 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));1526 amdgpu_ring_write(ring, vmid);1527 1528 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0));1529 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));1530 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0));1531 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));1532 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0));1533 amdgpu_ring_write(ring, ib->length_dw);1534}1535 1536void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,1537 uint32_t val, uint32_t mask)1538{1539 struct amdgpu_device *adev = ring->adev;1540 1541 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));1542 amdgpu_ring_write(ring, reg << 2);1543 1544 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));1545 amdgpu_ring_write(ring, val);1546 1547 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));1548 amdgpu_ring_write(ring, mask);1549 1550 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));1551 1552 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));1553}1554 1555void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,1556 unsigned vmid, uint64_t pd_addr)1557{1558 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];1559 uint32_t data0, data1, mask;1560 1561 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);1562 1563 /* wait for register write */1564 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;1565 data1 = lower_32_bits(pd_addr);1566 mask = 0xffffffff;1567 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);1568}1569 1570void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,1571 uint32_t reg, uint32_t val)1572{1573 struct amdgpu_device *adev = ring->adev;1574 1575 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));1576 amdgpu_ring_write(ring, reg << 2);1577 1578 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));1579 amdgpu_ring_write(ring, val);1580 1581 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));1582 1583 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));1584}1585 1586/**1587 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer1588 *1589 * @ring: amdgpu_ring pointer1590 *1591 * Returns the current hardware enc read pointer1592 */1593static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)1594{1595 struct amdgpu_device *adev = ring->adev;1596 1597 if (ring == &adev->vcn.inst->ring_enc[0])1598 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);1599 else1600 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);1601}1602 1603 /**1604 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer1605 *1606 * @ring: amdgpu_ring pointer1607 *1608 * Returns the current hardware enc write pointer1609 */1610static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)1611{1612 struct amdgpu_device *adev = ring->adev;1613 1614 if (ring == &adev->vcn.inst->ring_enc[0]) {1615 if (ring->use_doorbell)1616 return *ring->wptr_cpu_addr;1617 else1618 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);1619 } else {1620 if (ring->use_doorbell)1621 return *ring->wptr_cpu_addr;1622 else1623 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);1624 }1625}1626 1627 /**1628 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer1629 *1630 * @ring: amdgpu_ring pointer1631 *1632 * Commits the enc write pointer to the hardware1633 */1634static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)1635{1636 struct amdgpu_device *adev = ring->adev;1637 1638 if (ring == &adev->vcn.inst->ring_enc[0]) {1639 if (ring->use_doorbell) {1640 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);1641 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));1642 } else {1643 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));1644 }1645 } else {1646 if (ring->use_doorbell) {1647 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);1648 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));1649 } else {1650 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));1651 }1652 }1653}1654 1655/**1656 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command1657 *1658 * @ring: amdgpu_ring pointer1659 * @addr: address1660 * @seq: sequence number1661 * @flags: fence related flags1662 *1663 * Write enc a fence and a trap command to the ring.1664 */1665void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,1666 u64 seq, unsigned flags)1667{1668 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);1669 1670 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);1671 amdgpu_ring_write(ring, addr);1672 amdgpu_ring_write(ring, upper_32_bits(addr));1673 amdgpu_ring_write(ring, seq);1674 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);1675}1676 1677void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)1678{1679 amdgpu_ring_write(ring, VCN_ENC_CMD_END);1680}1681 1682/**1683 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer1684 *1685 * @ring: amdgpu_ring pointer1686 * @job: job to retrive vmid from1687 * @ib: indirect buffer to execute1688 * @flags: unused1689 *1690 * Write enc ring commands to execute the indirect buffer1691 */1692void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,1693 struct amdgpu_job *job,1694 struct amdgpu_ib *ib,1695 uint32_t flags)1696{1697 unsigned vmid = AMDGPU_JOB_GET_VMID(job);1698 1699 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);1700 amdgpu_ring_write(ring, vmid);1701 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));1702 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));1703 amdgpu_ring_write(ring, ib->length_dw);1704}1705 1706void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,1707 uint32_t val, uint32_t mask)1708{1709 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);1710 amdgpu_ring_write(ring, reg << 2);1711 amdgpu_ring_write(ring, mask);1712 amdgpu_ring_write(ring, val);1713}1714 1715void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,1716 unsigned int vmid, uint64_t pd_addr)1717{1718 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];1719 1720 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);1721 1722 /* wait for reg writes */1723 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +1724 vmid * hub->ctx_addr_distance,1725 lower_32_bits(pd_addr), 0xffffffff);1726}1727 1728void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)1729{1730 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);1731 amdgpu_ring_write(ring, reg << 2);1732 amdgpu_ring_write(ring, val);1733}1734 1735static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,1736 struct amdgpu_irq_src *source,1737 unsigned type,1738 enum amdgpu_interrupt_state state)1739{1740 return 0;1741}1742 1743static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,1744 struct amdgpu_irq_src *source,1745 struct amdgpu_iv_entry *entry)1746{1747 DRM_DEBUG("IH: VCN TRAP\n");1748 1749 switch (entry->src_id) {1750 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:1751 amdgpu_fence_process(&adev->vcn.inst->ring_dec);1752 break;1753 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:1754 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);1755 break;1756 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:1757 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);1758 break;1759 default:1760 DRM_ERROR("Unhandled interrupt: %d %d\n",1761 entry->src_id, entry->src_data[0]);1762 break;1763 }1764 1765 return 0;1766}1767 1768int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)1769{1770 struct amdgpu_device *adev = ring->adev;1771 uint32_t tmp = 0;1772 unsigned i;1773 int r;1774 1775 if (amdgpu_sriov_vf(adev))1776 return 0;1777 1778 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);1779 r = amdgpu_ring_alloc(ring, 4);1780 if (r)1781 return r;1782 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));1783 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));1784 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));1785 amdgpu_ring_write(ring, 0xDEADBEEF);1786 amdgpu_ring_commit(ring);1787 for (i = 0; i < adev->usec_timeout; i++) {1788 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);1789 if (tmp == 0xDEADBEEF)1790 break;1791 udelay(1);1792 }1793 1794 if (i >= adev->usec_timeout)1795 r = -ETIMEDOUT;1796 1797 return r;1798}1799 1800 1801static int vcn_v2_0_set_powergating_state(void *handle,1802 enum amd_powergating_state state)1803{1804 /* This doesn't actually powergate the VCN block.1805 * That's done in the dpm code via the SMC. This1806 * just re-inits the block as necessary. The actual1807 * gating still happens in the dpm code. We should1808 * revisit this when there is a cleaner line between1809 * the smc and the hw blocks1810 */1811 int ret;1812 struct amdgpu_device *adev = (struct amdgpu_device *)handle;1813 1814 if (amdgpu_sriov_vf(adev)) {1815 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;1816 return 0;1817 }1818 1819 if (state == adev->vcn.cur_state)1820 return 0;1821 1822 if (state == AMD_PG_STATE_GATE)1823 ret = vcn_v2_0_stop(adev);1824 else1825 ret = vcn_v2_0_start(adev);1826 1827 if (!ret)1828 adev->vcn.cur_state = state;1829 return ret;1830}1831 1832static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,1833 struct amdgpu_mm_table *table)1834{1835 uint32_t data = 0, loop;1836 uint64_t addr = table->gpu_addr;1837 struct mmsch_v2_0_init_header *header;1838 uint32_t size;1839 int i;1840 1841 header = (struct mmsch_v2_0_init_header *)table->cpu_addr;1842 size = header->header_size + header->vcn_table_size;1843 1844 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr1845 * of memory descriptor location1846 */1847 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));1848 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));1849 1850 /* 2, update vmid of descriptor */1851 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);1852 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;1853 /* use domain0 for MM scheduler */1854 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);1855 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);1856 1857 /* 3, notify mmsch about the size of this descriptor */1858 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);1859 1860 /* 4, set resp to zero */1861 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);1862 1863 adev->vcn.inst->ring_dec.wptr = 0;1864 adev->vcn.inst->ring_dec.wptr_old = 0;1865 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);1866 1867 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {1868 adev->vcn.inst->ring_enc[i].wptr = 0;1869 adev->vcn.inst->ring_enc[i].wptr_old = 0;1870 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);1871 }1872 1873 /* 5, kick off the initialization and wait until1874 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero1875 */1876 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);1877 1878 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);1879 loop = 1000;1880 while ((data & 0x10000002) != 0x10000002) {1881 udelay(10);1882 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);1883 loop--;1884 if (!loop)1885 break;1886 }1887 1888 if (!loop) {1889 DRM_ERROR("failed to init MMSCH, " \1890 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);1891 return -EBUSY;1892 }1893 1894 return 0;1895}1896 1897static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)1898{1899 int r;1900 uint32_t tmp;1901 struct amdgpu_ring *ring;1902 uint32_t offset, size;1903 uint32_t table_size = 0;1904 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };1905 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };1906 struct mmsch_v2_0_cmd_end end = { {0} };1907 struct mmsch_v2_0_init_header *header;1908 uint32_t *init_table = adev->virt.mm_table.cpu_addr;1909 uint8_t i = 0;1910 1911 header = (struct mmsch_v2_0_init_header *)init_table;1912 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;1913 direct_rd_mod_wt.cmd_header.command_type =1914 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;1915 end.cmd_header.command_type = MMSCH_COMMAND__END;1916 1917 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {1918 header->version = MMSCH_VERSION;1919 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;1920 1921 header->vcn_table_offset = header->header_size;1922 1923 init_table += header->vcn_table_offset;1924 1925 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);1926 1927 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(1928 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),1929 0xFFFFFFFF, 0x00000004);1930 1931 /* mc resume*/1932 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {1933 MMSCH_V2_0_INSERT_DIRECT_WT(1934 SOC15_REG_OFFSET(UVD, i,1935 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),1936 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo);1937 MMSCH_V2_0_INSERT_DIRECT_WT(1938 SOC15_REG_OFFSET(UVD, i,1939 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),1940 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi);1941 offset = 0;1942 } else {1943 MMSCH_V2_0_INSERT_DIRECT_WT(1944 SOC15_REG_OFFSET(UVD, i,1945 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),1946 lower_32_bits(adev->vcn.inst->gpu_addr));1947 MMSCH_V2_0_INSERT_DIRECT_WT(1948 SOC15_REG_OFFSET(UVD, i,1949 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),1950 upper_32_bits(adev->vcn.inst->gpu_addr));1951 offset = size;1952 }1953 1954 MMSCH_V2_0_INSERT_DIRECT_WT(1955 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),1956 0);1957 MMSCH_V2_0_INSERT_DIRECT_WT(1958 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),1959 size);1960 1961 MMSCH_V2_0_INSERT_DIRECT_WT(1962 SOC15_REG_OFFSET(UVD, i,1963 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),1964 lower_32_bits(adev->vcn.inst->gpu_addr + offset));1965 MMSCH_V2_0_INSERT_DIRECT_WT(1966 SOC15_REG_OFFSET(UVD, i,1967 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),1968 upper_32_bits(adev->vcn.inst->gpu_addr + offset));1969 MMSCH_V2_0_INSERT_DIRECT_WT(1970 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),1971 0);1972 MMSCH_V2_0_INSERT_DIRECT_WT(1973 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),1974 AMDGPU_VCN_STACK_SIZE);1975 1976 MMSCH_V2_0_INSERT_DIRECT_WT(1977 SOC15_REG_OFFSET(UVD, i,1978 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),1979 lower_32_bits(adev->vcn.inst->gpu_addr + offset +1980 AMDGPU_VCN_STACK_SIZE));1981 MMSCH_V2_0_INSERT_DIRECT_WT(1982 SOC15_REG_OFFSET(UVD, i,1983 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),1984 upper_32_bits(adev->vcn.inst->gpu_addr + offset +1985 AMDGPU_VCN_STACK_SIZE));1986 MMSCH_V2_0_INSERT_DIRECT_WT(1987 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),1988 0);1989 MMSCH_V2_0_INSERT_DIRECT_WT(1990 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),1991 AMDGPU_VCN_CONTEXT_SIZE);1992 1993 for (r = 0; r < adev->vcn.num_enc_rings; ++r) {1994 ring = &adev->vcn.inst->ring_enc[r];1995 ring->wptr = 0;1996 MMSCH_V2_0_INSERT_DIRECT_WT(1997 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),1998 lower_32_bits(ring->gpu_addr));1999 MMSCH_V2_0_INSERT_DIRECT_WT(2000 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),2001 upper_32_bits(ring->gpu_addr));2002 MMSCH_V2_0_INSERT_DIRECT_WT(2003 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),2004 ring->ring_size / 4);2005 }2006 2007 ring = &adev->vcn.inst->ring_dec;2008 ring->wptr = 0;2009 MMSCH_V2_0_INSERT_DIRECT_WT(2010 SOC15_REG_OFFSET(UVD, i,2011 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),2012 lower_32_bits(ring->gpu_addr));2013 MMSCH_V2_0_INSERT_DIRECT_WT(2014 SOC15_REG_OFFSET(UVD, i,2015 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),2016 upper_32_bits(ring->gpu_addr));2017 /* force RBC into idle state */2018 tmp = order_base_2(ring->ring_size);2019 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);2020 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);2021 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);2022 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);2023 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);2024 MMSCH_V2_0_INSERT_DIRECT_WT(2025 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);2026 2027 /* add end packet */2028 tmp = sizeof(struct mmsch_v2_0_cmd_end);2029 memcpy((void *)init_table, &end, tmp);2030 table_size += (tmp / 4);2031 header->vcn_table_size = table_size;2032 2033 }2034 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);2035}2036 2037static void vcn_v2_0_print_ip_state(void *handle, struct drm_printer *p)2038{2039 struct amdgpu_device *adev = (struct amdgpu_device *)handle;2040 int i, j;2041 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);2042 uint32_t inst_off, is_powered;2043 2044 if (!adev->vcn.ip_dump)2045 return;2046 2047 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);2048 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {2049 if (adev->vcn.harvest_config & (1 << i)) {2050 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);2051 continue;2052 }2053 2054 inst_off = i * reg_count;2055 is_powered = (adev->vcn.ip_dump[inst_off] &2056 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;2057 2058 if (is_powered) {2059 drm_printf(p, "\nActive Instance:VCN%d\n", i);2060 for (j = 0; j < reg_count; j++)2061 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name,2062 adev->vcn.ip_dump[inst_off + j]);2063 } else {2064 drm_printf(p, "\nInactive Instance:VCN%d\n", i);2065 }2066 }2067}2068 2069static void vcn_v2_0_dump_ip_state(void *handle)2070{2071 struct amdgpu_device *adev = (struct amdgpu_device *)handle;2072 int i, j;2073 bool is_powered;2074 uint32_t inst_off;2075 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);2076 2077 if (!adev->vcn.ip_dump)2078 return;2079 2080 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {2081 if (adev->vcn.harvest_config & (1 << i))2082 continue;2083 2084 inst_off = i * reg_count;2085 /* mmUVD_POWER_STATUS is always readable and is first element of the array */2086 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);2087 is_powered = (adev->vcn.ip_dump[inst_off] &2088 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;2089 2090 if (is_powered)2091 for (j = 1; j < reg_count; j++)2092 adev->vcn.ip_dump[inst_off + j] =2093 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i));2094 }2095}2096 2097static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {2098 .name = "vcn_v2_0",2099 .early_init = vcn_v2_0_early_init,2100 .late_init = NULL,2101 .sw_init = vcn_v2_0_sw_init,2102 .sw_fini = vcn_v2_0_sw_fini,2103 .hw_init = vcn_v2_0_hw_init,2104 .hw_fini = vcn_v2_0_hw_fini,2105 .suspend = vcn_v2_0_suspend,2106 .resume = vcn_v2_0_resume,2107 .is_idle = vcn_v2_0_is_idle,2108 .wait_for_idle = vcn_v2_0_wait_for_idle,2109 .check_soft_reset = NULL,2110 .pre_soft_reset = NULL,2111 .soft_reset = NULL,2112 .post_soft_reset = NULL,2113 .set_clockgating_state = vcn_v2_0_set_clockgating_state,2114 .set_powergating_state = vcn_v2_0_set_powergating_state,2115 .dump_ip_state = vcn_v2_0_dump_ip_state,2116 .print_ip_state = vcn_v2_0_print_ip_state,2117};2118 2119static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {2120 .type = AMDGPU_RING_TYPE_VCN_DEC,2121 .align_mask = 0xf,2122 .secure_submission_supported = true,2123 .get_rptr = vcn_v2_0_dec_ring_get_rptr,2124 .get_wptr = vcn_v2_0_dec_ring_get_wptr,2125 .set_wptr = vcn_v2_0_dec_ring_set_wptr,2126 .emit_frame_size =2127 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +2128 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +2129 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */2130 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */2131 6,2132 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */2133 .emit_ib = vcn_v2_0_dec_ring_emit_ib,2134 .emit_fence = vcn_v2_0_dec_ring_emit_fence,2135 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,2136 .test_ring = vcn_v2_0_dec_ring_test_ring,2137 .test_ib = amdgpu_vcn_dec_ring_test_ib,2138 .insert_nop = vcn_v2_0_dec_ring_insert_nop,2139 .insert_start = vcn_v2_0_dec_ring_insert_start,2140 .insert_end = vcn_v2_0_dec_ring_insert_end,2141 .pad_ib = amdgpu_ring_generic_pad_ib,2142 .begin_use = amdgpu_vcn_ring_begin_use,2143 .end_use = amdgpu_vcn_ring_end_use,2144 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,2145 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,2146 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,2147};2148 2149static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {2150 .type = AMDGPU_RING_TYPE_VCN_ENC,2151 .align_mask = 0x3f,2152 .nop = VCN_ENC_CMD_NO_OP,2153 .get_rptr = vcn_v2_0_enc_ring_get_rptr,2154 .get_wptr = vcn_v2_0_enc_ring_get_wptr,2155 .set_wptr = vcn_v2_0_enc_ring_set_wptr,2156 .emit_frame_size =2157 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +2158 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +2159 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */2160 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */2161 1, /* vcn_v2_0_enc_ring_insert_end */2162 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */2163 .emit_ib = vcn_v2_0_enc_ring_emit_ib,2164 .emit_fence = vcn_v2_0_enc_ring_emit_fence,2165 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,2166 .test_ring = amdgpu_vcn_enc_ring_test_ring,2167 .test_ib = amdgpu_vcn_enc_ring_test_ib,2168 .insert_nop = amdgpu_ring_insert_nop,2169 .insert_end = vcn_v2_0_enc_ring_insert_end,2170 .pad_ib = amdgpu_ring_generic_pad_ib,2171 .begin_use = amdgpu_vcn_ring_begin_use,2172 .end_use = amdgpu_vcn_ring_end_use,2173 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,2174 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,2175 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,2176};2177 2178static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)2179{2180 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;2181}2182 2183static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)2184{2185 int i;2186 2187 for (i = 0; i < adev->vcn.num_enc_rings; ++i)2188 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;2189}2190 2191static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {2192 .set = vcn_v2_0_set_interrupt_state,2193 .process = vcn_v2_0_process_interrupt,2194};2195 2196static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)2197{2198 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1;2199 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;2200}2201 2202const struct amdgpu_ip_block_version vcn_v2_0_ip_block =2203{2204 .type = AMD_IP_BLOCK_TYPE_VCN,2205 .major = 2,2206 .minor = 0,2207 .rev = 0,2208 .funcs = &vcn_v2_0_ip_funcs,2209};2210