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1/*2 * Copyright (C) 2016 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included12 * in all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.20 *21 */22 23#ifndef __VEGA10_SDMA_PKT_OPEN_H_24#define __VEGA10_SDMA_PKT_OPEN_H_25 26#define SDMA_OP_NOP 027#define SDMA_OP_COPY 128#define SDMA_OP_WRITE 229#define SDMA_OP_INDIRECT 430#define SDMA_OP_FENCE 531#define SDMA_OP_TRAP 632#define SDMA_OP_SEM 733#define SDMA_OP_POLL_REGMEM 834#define SDMA_OP_COND_EXE 935#define SDMA_OP_ATOMIC 1036#define SDMA_OP_CONST_FILL 1137#define SDMA_OP_PTEPDE 1238#define SDMA_OP_TIMESTAMP 1339#define SDMA_OP_SRBM_WRITE 1440#define SDMA_OP_PRE_EXE 1541#define SDMA_OP_DUMMY_TRAP 1642#define SDMA_SUBOP_TIMESTAMP_SET 043#define SDMA_SUBOP_TIMESTAMP_GET 144#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 245#define SDMA_SUBOP_COPY_LINEAR 046#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 447#define SDMA_SUBOP_COPY_TILED 148#define SDMA_SUBOP_COPY_TILED_SUB_WIND 549#define SDMA_SUBOP_COPY_T2T_SUB_WIND 650#define SDMA_SUBOP_COPY_SOA 351#define SDMA_SUBOP_COPY_DIRTY_PAGE 752#define SDMA_SUBOP_COPY_LINEAR_PHY 853#define SDMA_SUBOP_WRITE_LINEAR 054#define SDMA_SUBOP_WRITE_TILED 155#define SDMA_SUBOP_PTEPDE_GEN 056#define SDMA_SUBOP_PTEPDE_COPY 157#define SDMA_SUBOP_PTEPDE_RMW 258#define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 359#define SDMA_SUBOP_DATA_FILL_MULTI 160#define SDMA_SUBOP_POLL_REG_WRITE_MEM 161#define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 262#define SDMA_SUBOP_POLL_MEM_VERIFY 363#define HEADER_AGENT_DISPATCH 464#define HEADER_BARRIER 565#define SDMA_OP_AQL_COPY 066#define SDMA_OP_AQL_BARRIER_OR 067 68/*define for op field*/69#define SDMA_PKT_HEADER_op_offset 070#define SDMA_PKT_HEADER_op_mask 0x000000FF71#define SDMA_PKT_HEADER_op_shift 072#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift)73 74/*define for sub_op field*/75#define SDMA_PKT_HEADER_sub_op_offset 076#define SDMA_PKT_HEADER_sub_op_mask 0x000000FF77#define SDMA_PKT_HEADER_sub_op_shift 878#define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift)79 80 81/*82** Definitions for SDMA_PKT_COPY_LINEAR packet83*/84 85/*define for HEADER word*/86/*define for op field*/87#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 088#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF89#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 090#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift)91 92/*define for sub_op field*/93#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 094#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF95#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 896#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift)97 98/*define for encrypt field*/99#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0100#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001101#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16102#define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift)103 104/*define for tmz field*/105#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0106#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001107#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18108#define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift)109 110/*define for broadcast field*/111#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0112#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001113#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27114#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift)115 116/*define for COUNT word*/117/*define for count field*/118#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1119#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF120#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0121#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift)122 123/*define for PARAMETER word*/124/*define for dst_sw field*/125#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2126#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003127#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16128#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift)129 130/*define for src_sw field*/131#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2132#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003133#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24134#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift)135 136/*define for SRC_ADDR_LO word*/137/*define for src_addr_31_0 field*/138#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3139#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF140#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0141#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)142 143/*define for SRC_ADDR_HI word*/144/*define for src_addr_63_32 field*/145#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4146#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF147#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0148#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)149 150/*define for DST_ADDR_LO word*/151/*define for dst_addr_31_0 field*/152#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5153#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF154#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0155#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)156 157/*define for DST_ADDR_HI word*/158/*define for dst_addr_63_32 field*/159#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6160#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF161#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0162#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)163 164 165/*166** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet167*/168 169/*define for HEADER word*/170/*define for op field*/171#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0172#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF173#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0174#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift)175 176/*define for sub_op field*/177#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0178#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF179#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8180#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift)181 182/*define for tmz field*/183#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0184#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001185#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18186#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift)187 188/*define for all field*/189#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0190#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001191#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31192#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift)193 194/*define for COUNT word*/195/*define for count field*/196#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1197#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF198#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0199#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift)200 201/*define for PARAMETER word*/202/*define for dst_sw field*/203#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2204#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003205#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 16206#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift)207 208/*define for dst_gcc field*/209#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2210#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001211#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19212#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift)213 214/*define for dst_sys field*/215#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2216#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001217#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20218#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift)219 220/*define for dst_snoop field*/221#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2222#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001223#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22224#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift)225 226/*define for dst_gpa field*/227#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2228#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001229#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23230#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift)231 232/*define for src_sw field*/233#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2234#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003235#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24236#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift)237 238/*define for src_sys field*/239#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2240#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001241#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28242#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift)243 244/*define for src_snoop field*/245#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2246#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001247#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30248#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift)249 250/*define for src_gpa field*/251#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2252#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001253#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31254#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift)255 256/*define for SRC_ADDR_LO word*/257/*define for src_addr_31_0 field*/258#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3259#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF260#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0261#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift)262 263/*define for SRC_ADDR_HI word*/264/*define for src_addr_63_32 field*/265#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4266#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF267#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0268#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift)269 270/*define for DST_ADDR_LO word*/271/*define for dst_addr_31_0 field*/272#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5273#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF274#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0275#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift)276 277/*define for DST_ADDR_HI word*/278/*define for dst_addr_63_32 field*/279#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6280#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF281#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0282#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift)283 284 285/*286** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet287*/288 289/*define for HEADER word*/290/*define for op field*/291#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0292#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF293#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0294#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift)295 296/*define for sub_op field*/297#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0298#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF299#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8300#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift)301 302/*define for tmz field*/303#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0304#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001305#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18306#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift)307 308/*define for COUNT word*/309/*define for count field*/310#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1311#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF312#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0313#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift)314 315/*define for PARAMETER word*/316/*define for dst_sw field*/317#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2318#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003319#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 16320#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift)321 322/*define for dst_gcc field*/323#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2324#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001325#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19326#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift)327 328/*define for dst_sys field*/329#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2330#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001331#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20332#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift)333 334/*define for dst_log field*/335#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2336#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001337#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21338#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift)339 340/*define for dst_snoop field*/341#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2342#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001343#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22344#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift)345 346/*define for dst_gpa field*/347#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2348#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001349#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23350#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift)351 352/*define for src_sw field*/353#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2354#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003355#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24356#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift)357 358/*define for src_gcc field*/359#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2360#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001361#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27362#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift)363 364/*define for src_sys field*/365#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2366#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001367#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28368#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift)369 370/*define for src_snoop field*/371#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2372#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001373#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30374#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift)375 376/*define for src_gpa field*/377#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2378#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001379#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31380#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift)381 382/*define for SRC_ADDR_LO word*/383/*define for src_addr_31_0 field*/384#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3385#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF386#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0387#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)388 389/*define for SRC_ADDR_HI word*/390/*define for src_addr_63_32 field*/391#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4392#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF393#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0394#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)395 396/*define for DST_ADDR_LO word*/397/*define for dst_addr_31_0 field*/398#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5399#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF400#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0401#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)402 403/*define for DST_ADDR_HI word*/404/*define for dst_addr_63_32 field*/405#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6406#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF407#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0408#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)409 410 411/*412** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet413*/414 415/*define for HEADER word*/416/*define for op field*/417#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0418#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF419#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0420#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift)421 422/*define for sub_op field*/423#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0424#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF425#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8426#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift)427 428/*define for encrypt field*/429#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0430#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001431#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16432#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift)433 434/*define for tmz field*/435#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0436#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001437#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18438#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift)439 440/*define for broadcast field*/441#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0442#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001443#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27444#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift)445 446/*define for COUNT word*/447/*define for count field*/448#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1449#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF450#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0451#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift)452 453/*define for PARAMETER word*/454/*define for dst2_sw field*/455#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2456#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003457#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8458#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift)459 460/*define for dst1_sw field*/461#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2462#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003463#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16464#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift)465 466/*define for src_sw field*/467#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2468#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003469#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24470#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift)471 472/*define for SRC_ADDR_LO word*/473/*define for src_addr_31_0 field*/474#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3475#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF476#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0477#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)478 479/*define for SRC_ADDR_HI word*/480/*define for src_addr_63_32 field*/481#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4482#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF483#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0484#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)485 486/*define for DST1_ADDR_LO word*/487/*define for dst1_addr_31_0 field*/488#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5489#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF490#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0491#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift)492 493/*define for DST1_ADDR_HI word*/494/*define for dst1_addr_63_32 field*/495#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6496#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF497#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0498#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift)499 500/*define for DST2_ADDR_LO word*/501/*define for dst2_addr_31_0 field*/502#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7503#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF504#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0505#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift)506 507/*define for DST2_ADDR_HI word*/508/*define for dst2_addr_63_32 field*/509#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8510#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF511#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0512#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift)513 514 515/*516** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet517*/518 519/*define for HEADER word*/520/*define for op field*/521#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0522#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF523#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0524#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift)525 526/*define for sub_op field*/527#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0528#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF529#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8530#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift)531 532/*define for tmz field*/533#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0534#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001535#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18536#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift)537 538/*define for elementsize field*/539#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0540#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007541#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29542#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift)543 544/*define for SRC_ADDR_LO word*/545/*define for src_addr_31_0 field*/546#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1547#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF548#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0549#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift)550 551/*define for SRC_ADDR_HI word*/552/*define for src_addr_63_32 field*/553#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2554#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF555#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0556#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift)557 558/*define for DW_3 word*/559/*define for src_x field*/560#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3561#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF562#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0563#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift)564 565/*define for src_y field*/566#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3567#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF568#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16569#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift)570 571/*define for DW_4 word*/572/*define for src_z field*/573#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4574#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF575#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0576#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift)577 578/*define for src_pitch field*/579#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4580#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF581#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13582#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift)583 584/*define for DW_5 word*/585/*define for src_slice_pitch field*/586#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5587#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF588#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0589#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift)590 591/*define for DST_ADDR_LO word*/592/*define for dst_addr_31_0 field*/593#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6594#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF595#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0596#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift)597 598/*define for DST_ADDR_HI word*/599/*define for dst_addr_63_32 field*/600#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7601#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF602#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0603#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift)604 605/*define for DW_8 word*/606/*define for dst_x field*/607#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8608#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF609#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0610#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift)611 612/*define for dst_y field*/613#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8614#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF615#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16616#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift)617 618/*define for DW_9 word*/619/*define for dst_z field*/620#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9621#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF622#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0623#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift)624 625/*define for dst_pitch field*/626#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9627#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF628#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13629#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift)630 631/*define for DW_10 word*/632/*define for dst_slice_pitch field*/633#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10634#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF635#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0636#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift)637 638/*define for DW_11 word*/639/*define for rect_x field*/640#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11641#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF642#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0643#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift)644 645/*define for rect_y field*/646#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11647#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF648#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16649#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift)650 651/*define for DW_12 word*/652/*define for rect_z field*/653#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12654#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF655#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0656#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift)657 658/*define for dst_sw field*/659#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12660#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003661#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16662#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift)663 664/*define for src_sw field*/665#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12666#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003667#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24668#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift)669 670 671/*672** Definitions for SDMA_PKT_COPY_TILED packet673*/674 675/*define for HEADER word*/676/*define for op field*/677#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0678#define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF679#define SDMA_PKT_COPY_TILED_HEADER_op_shift 0680#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift)681 682/*define for sub_op field*/683#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0684#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF685#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8686#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift)687 688/*define for encrypt field*/689#define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0690#define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001691#define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16692#define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift)693 694/*define for tmz field*/695#define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0696#define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001697#define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18698#define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift)699 700/*define for mip_max field*/701#define SDMA_PKT_COPY_TILED_HEADER_mip_max_offset 0702#define SDMA_PKT_COPY_TILED_HEADER_mip_max_mask 0x0000000F703#define SDMA_PKT_COPY_TILED_HEADER_mip_max_shift 20704#define SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_HEADER_mip_max_shift)705 706/*define for detile field*/707#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0708#define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001709#define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31710#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift)711 712/*define for TILED_ADDR_LO word*/713/*define for tiled_addr_31_0 field*/714#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1715#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF716#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0717#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift)718 719/*define for TILED_ADDR_HI word*/720/*define for tiled_addr_63_32 field*/721#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2722#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF723#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0724#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift)725 726/*define for DW_3 word*/727/*define for width field*/728#define SDMA_PKT_COPY_TILED_DW_3_width_offset 3729#define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF730#define SDMA_PKT_COPY_TILED_DW_3_width_shift 0731#define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift)732 733/*define for DW_4 word*/734/*define for height field*/735#define SDMA_PKT_COPY_TILED_DW_4_height_offset 4736#define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF737#define SDMA_PKT_COPY_TILED_DW_4_height_shift 0738#define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift)739 740/*define for depth field*/741#define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4742#define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x000007FF743#define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16744#define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift)745 746/*define for DW_5 word*/747/*define for element_size field*/748#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5749#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007750#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0751#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift)752 753/*define for swizzle_mode field*/754#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5755#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F756#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3757#define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift)758 759/*define for dimension field*/760#define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5761#define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003762#define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9763#define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift)764 765/*define for epitch field*/766#define SDMA_PKT_COPY_TILED_DW_5_epitch_offset 5767#define SDMA_PKT_COPY_TILED_DW_5_epitch_mask 0x0000FFFF768#define SDMA_PKT_COPY_TILED_DW_5_epitch_shift 16769#define SDMA_PKT_COPY_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_epitch_mask) << SDMA_PKT_COPY_TILED_DW_5_epitch_shift)770 771/*define for DW_6 word*/772/*define for x field*/773#define SDMA_PKT_COPY_TILED_DW_6_x_offset 6774#define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF775#define SDMA_PKT_COPY_TILED_DW_6_x_shift 0776#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift)777 778/*define for y field*/779#define SDMA_PKT_COPY_TILED_DW_6_y_offset 6780#define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF781#define SDMA_PKT_COPY_TILED_DW_6_y_shift 16782#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift)783 784/*define for DW_7 word*/785/*define for z field*/786#define SDMA_PKT_COPY_TILED_DW_7_z_offset 7787#define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x000007FF788#define SDMA_PKT_COPY_TILED_DW_7_z_shift 0789#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift)790 791/*define for linear_sw field*/792#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7793#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003794#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16795#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift)796 797/*define for tile_sw field*/798#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7799#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003800#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24801#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift)802 803/*define for LINEAR_ADDR_LO word*/804/*define for linear_addr_31_0 field*/805#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8806#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF807#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0808#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift)809 810/*define for LINEAR_ADDR_HI word*/811/*define for linear_addr_63_32 field*/812#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9813#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF814#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0815#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift)816 817/*define for LINEAR_PITCH word*/818/*define for linear_pitch field*/819#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10820#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF821#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0822#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift)823 824/*define for LINEAR_SLICE_PITCH word*/825/*define for linear_slice_pitch field*/826#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11827#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF828#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0829#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift)830 831/*define for COUNT word*/832/*define for count field*/833#define SDMA_PKT_COPY_TILED_COUNT_count_offset 12834#define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF835#define SDMA_PKT_COPY_TILED_COUNT_count_shift 0836#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift)837 838 839/*840** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet841*/842 843/*define for HEADER word*/844/*define for op field*/845#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0846#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF847#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0848#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift)849 850/*define for sub_op field*/851#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0852#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF853#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8854#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift)855 856/*define for encrypt field*/857#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0858#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001859#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16860#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift)861 862/*define for tmz field*/863#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0864#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001865#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18866#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift)867 868/*define for mip_max field*/869#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset 0870#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask 0x0000000F871#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift 20872#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift)873 874/*define for videocopy field*/875#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0876#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001877#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26878#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift)879 880/*define for broadcast field*/881#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0882#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001883#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27884#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift)885 886/*define for TILED_ADDR_LO_0 word*/887/*define for tiled_addr0_31_0 field*/888#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1889#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF890#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0891#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift)892 893/*define for TILED_ADDR_HI_0 word*/894/*define for tiled_addr0_63_32 field*/895#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2896#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF897#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0898#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift)899 900/*define for TILED_ADDR_LO_1 word*/901/*define for tiled_addr1_31_0 field*/902#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3903#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF904#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0905#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift)906 907/*define for TILED_ADDR_HI_1 word*/908/*define for tiled_addr1_63_32 field*/909#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4910#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF911#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0912#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift)913 914/*define for DW_5 word*/915/*define for width field*/916#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5917#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF918#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0919#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift)920 921/*define for DW_6 word*/922/*define for height field*/923#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6924#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF925#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0926#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift)927 928/*define for depth field*/929#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6930#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x000007FF931#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16932#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift)933 934/*define for DW_7 word*/935/*define for element_size field*/936#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7937#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007938#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0939#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift)940 941/*define for swizzle_mode field*/942#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7943#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F944#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3945#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift)946 947/*define for dimension field*/948#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7949#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003950#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9951#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift)952 953/*define for epitch field*/954#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset 7955#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask 0x0000FFFF956#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift 16957#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift)958 959/*define for DW_8 word*/960/*define for x field*/961#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8962#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF963#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0964#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift)965 966/*define for y field*/967#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8968#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF969#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16970#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift)971 972/*define for DW_9 word*/973/*define for z field*/974#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9975#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x000007FF976#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0977#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift)978 979/*define for DW_10 word*/980/*define for dst2_sw field*/981#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10982#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003983#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8984#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift)985 986/*define for linear_sw field*/987#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10988#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003989#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16990#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift)991 992/*define for tile_sw field*/993#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10994#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003995#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24996#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift)997 998/*define for LINEAR_ADDR_LO word*/999/*define for linear_addr_31_0 field*/1000#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 111001#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF1002#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 01003#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift)1004 1005/*define for LINEAR_ADDR_HI word*/1006/*define for linear_addr_63_32 field*/1007#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 121008#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF1009#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 01010#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift)1011 1012/*define for LINEAR_PITCH word*/1013/*define for linear_pitch field*/1014#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 131015#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF1016#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 01017#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift)1018 1019/*define for LINEAR_SLICE_PITCH word*/1020/*define for linear_slice_pitch field*/1021#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 141022#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF1023#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 01024#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift)1025 1026/*define for COUNT word*/1027/*define for count field*/1028#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 151029#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF1030#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 01031#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift)1032 1033 1034/*1035** Definitions for SDMA_PKT_COPY_T2T packet1036*/1037 1038/*define for HEADER word*/1039/*define for op field*/1040#define SDMA_PKT_COPY_T2T_HEADER_op_offset 01041#define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF1042#define SDMA_PKT_COPY_T2T_HEADER_op_shift 01043#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift)1044 1045/*define for sub_op field*/1046#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 01047#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF1048#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 81049#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift)1050 1051/*define for tmz field*/1052#define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 01053#define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x000000011054#define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 181055#define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift)1056 1057/*define for mip_max field*/1058#define SDMA_PKT_COPY_T2T_HEADER_mip_max_offset 01059#define SDMA_PKT_COPY_T2T_HEADER_mip_max_mask 0x0000000F1060#define SDMA_PKT_COPY_T2T_HEADER_mip_max_shift 201061#define SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_mip_max_mask) << SDMA_PKT_COPY_T2T_HEADER_mip_max_shift)1062 1063/*define for SRC_ADDR_LO word*/1064/*define for src_addr_31_0 field*/1065#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 11066#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF1067#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 01068#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift)1069 1070/*define for SRC_ADDR_HI word*/1071/*define for src_addr_63_32 field*/1072#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 21073#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF1074#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 01075#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift)1076 1077/*define for DW_3 word*/1078/*define for src_x field*/1079#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 31080#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF1081#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 01082#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift)1083 1084/*define for src_y field*/1085#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 31086#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF1087#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 161088#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift)1089 1090/*define for DW_4 word*/1091/*define for src_z field*/1092#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 41093#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF1094#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 01095#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift)1096 1097/*define for src_width field*/1098#define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 41099#define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF1100#define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 161101#define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift)1102 1103/*define for DW_5 word*/1104/*define for src_height field*/1105#define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 51106#define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF1107#define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 01108#define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift)1109 1110/*define for src_depth field*/1111#define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 51112#define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x000007FF1113#define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 161114#define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift)1115 1116/*define for DW_6 word*/1117/*define for src_element_size field*/1118#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 61119#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x000000071120#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 01121#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift)1122 1123/*define for src_swizzle_mode field*/1124#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 61125#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F1126#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 31127#define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift)1128 1129/*define for src_dimension field*/1130#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 61131#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x000000031132#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 91133#define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift)1134 1135/*define for src_epitch field*/1136#define SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset 61137#define SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask 0x0000FFFF1138#define SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift 161139#define SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask) << SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift)1140 1141/*define for DST_ADDR_LO word*/1142/*define for dst_addr_31_0 field*/1143#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 71144#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF1145#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 01146#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift)1147 1148/*define for DST_ADDR_HI word*/1149/*define for dst_addr_63_32 field*/1150#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 81151#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF1152#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 01153#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift)1154 1155/*define for DW_9 word*/1156/*define for dst_x field*/1157#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 91158#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF1159#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 01160#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift)1161 1162/*define for dst_y field*/1163#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 91164#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF1165#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 161166#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift)1167 1168/*define for DW_10 word*/1169/*define for dst_z field*/1170#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 101171#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF1172#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 01173#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift)1174 1175/*define for dst_width field*/1176#define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 101177#define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF1178#define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 161179#define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift)1180 1181/*define for DW_11 word*/1182/*define for dst_height field*/1183#define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 111184#define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF1185#define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 01186#define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift)1187 1188/*define for dst_depth field*/1189#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 111190#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x000007FF1191#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 161192#define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift)1193 1194/*define for DW_12 word*/1195/*define for dst_element_size field*/1196#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 121197#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x000000071198#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 01199#define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift)1200 1201/*define for dst_swizzle_mode field*/1202#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 121203#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F1204#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 31205#define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift)1206 1207/*define for dst_dimension field*/1208#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 121209#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x000000031210#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 91211#define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift)1212 1213/*define for dst_epitch field*/1214#define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset 121215#define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask 0x0000FFFF1216#define SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift 161217#define SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift)1218 1219/*define for DW_13 word*/1220/*define for rect_x field*/1221#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 131222#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF1223#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 01224#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift)1225 1226/*define for rect_y field*/1227#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 131228#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF1229#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 161230#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift)1231 1232/*define for DW_14 word*/1233/*define for rect_z field*/1234#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 141235#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF1236#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 01237#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift)1238 1239/*define for dst_sw field*/1240#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 141241#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x000000031242#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 161243#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift)1244 1245/*define for src_sw field*/1246#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 141247#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x000000031248#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 241249#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift)1250 1251 1252/*1253** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet1254*/1255 1256/*define for HEADER word*/1257/*define for op field*/1258#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 01259#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF1260#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 01261#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift)1262 1263/*define for sub_op field*/1264#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 01265#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF1266#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 81267#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift)1268 1269/*define for tmz field*/1270#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 01271#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x000000011272#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 181273#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift)1274 1275/*define for mip_max field*/1276#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset 01277#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask 0x0000000F1278#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift 201279#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift)1280 1281/*define for mip_id field*/1282#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset 01283#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask 0x0000000F1284#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift 241285#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift)1286 1287/*define for detile field*/1288#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 01289#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x000000011290#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 311291#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift)1292 1293/*define for TILED_ADDR_LO word*/1294/*define for tiled_addr_31_0 field*/1295#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 11296#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF1297#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 01298#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift)1299 1300/*define for TILED_ADDR_HI word*/1301/*define for tiled_addr_63_32 field*/1302#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 21303#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF1304#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 01305#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift)1306 1307/*define for DW_3 word*/1308/*define for tiled_x field*/1309#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 31310#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF1311#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 01312#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift)1313 1314/*define for tiled_y field*/1315#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 31316#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF1317#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 161318#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift)1319 1320/*define for DW_4 word*/1321/*define for tiled_z field*/1322#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 41323#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF1324#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 01325#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift)1326 1327/*define for width field*/1328#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 41329#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF1330#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 161331#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift)1332 1333/*define for DW_5 word*/1334/*define for height field*/1335#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 51336#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF1337#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 01338#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift)1339 1340/*define for depth field*/1341#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 51342#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x000007FF1343#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 161344#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift)1345 1346/*define for DW_6 word*/1347/*define for element_size field*/1348#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 61349#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x000000071350#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 01351#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift)1352 1353/*define for swizzle_mode field*/1354#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 61355#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F1356#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 31357#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift)1358 1359/*define for dimension field*/1360#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 61361#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x000000031362#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 91363#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift)1364 1365/*define for epitch field*/1366#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset 61367#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask 0x0000FFFF1368#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift 161369#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift)1370 1371/*define for LINEAR_ADDR_LO word*/1372/*define for linear_addr_31_0 field*/1373#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 71374#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF1375#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 01376#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift)1377 1378/*define for LINEAR_ADDR_HI word*/1379/*define for linear_addr_63_32 field*/1380#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 81381#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF1382#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 01383#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift)1384 1385/*define for DW_9 word*/1386/*define for linear_x field*/1387#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 91388#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF1389#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 01390#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift)1391 1392/*define for linear_y field*/1393#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 91394#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF1395#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 161396#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift)1397 1398/*define for DW_10 word*/1399/*define for linear_z field*/1400#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 101401#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF1402#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 01403#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift)1404 1405/*define for linear_pitch field*/1406#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 101407#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF1408#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 161409#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift)1410 1411/*define for DW_11 word*/1412/*define for linear_slice_pitch field*/1413#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 111414#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF1415#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 01416#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift)1417 1418/*define for DW_12 word*/1419/*define for rect_x field*/1420#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 121421#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF1422#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 01423#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift)1424 1425/*define for rect_y field*/1426#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 121427#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF1428#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 161429#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift)1430 1431/*define for DW_13 word*/1432/*define for rect_z field*/1433#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 131434#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF1435#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 01436#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift)1437 1438/*define for linear_sw field*/1439#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 131440#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x000000031441#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 161442#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift)1443 1444/*define for tile_sw field*/1445#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 131446#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x000000031447#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 241448#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift)1449 1450 1451/*1452** Definitions for SDMA_PKT_COPY_STRUCT packet1453*/1454 1455/*define for HEADER word*/1456/*define for op field*/1457#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 01458#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF1459#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 01460#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift)1461 1462/*define for sub_op field*/1463#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 01464#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF1465#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 81466#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift)1467 1468/*define for tmz field*/1469#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 01470#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x000000011471#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 181472#define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift)1473 1474/*define for detile field*/1475#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 01476#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x000000011477#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 311478#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift)1479 1480/*define for SB_ADDR_LO word*/1481/*define for sb_addr_31_0 field*/1482#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 11483#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF1484#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 01485#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift)1486 1487/*define for SB_ADDR_HI word*/1488/*define for sb_addr_63_32 field*/1489#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 21490#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF1491#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 01492#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift)1493 1494/*define for START_INDEX word*/1495/*define for start_index field*/1496#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 31497#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF1498#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 01499#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift)1500 1501/*define for COUNT word*/1502/*define for count field*/1503#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 41504#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF1505#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 01506#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift)1507 1508/*define for DW_5 word*/1509/*define for stride field*/1510#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 51511#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF1512#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 01513#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift)1514 1515/*define for linear_sw field*/1516#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 51517#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x000000031518#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 161519#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift)1520 1521/*define for struct_sw field*/1522#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 51523#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x000000031524#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 241525#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift)1526 1527/*define for LINEAR_ADDR_LO word*/1528/*define for linear_addr_31_0 field*/1529#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 61530#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF1531#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 01532#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift)1533 1534/*define for LINEAR_ADDR_HI word*/1535/*define for linear_addr_63_32 field*/1536#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 71537#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF1538#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 01539#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift)1540 1541 1542/*1543** Definitions for SDMA_PKT_WRITE_UNTILED packet1544*/1545 1546/*define for HEADER word*/1547/*define for op field*/1548#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 01549#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF1550#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 01551#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift)1552 1553/*define for sub_op field*/1554#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 01555#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF1556#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 81557#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift)1558 1559/*define for encrypt field*/1560#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 01561#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x000000011562#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 161563#define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift)1564 1565/*define for tmz field*/1566#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 01567#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x000000011568#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 181569#define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift)1570 1571/*define for DST_ADDR_LO word*/1572/*define for dst_addr_31_0 field*/1573#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 11574#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF1575#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 01576#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift)1577 1578/*define for DST_ADDR_HI word*/1579/*define for dst_addr_63_32 field*/1580#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 21581#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF1582#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 01583#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift)1584 1585/*define for DW_3 word*/1586/*define for count field*/1587#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 31588#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF1589#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 01590#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift)1591 1592/*define for sw field*/1593#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 31594#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x000000031595#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 241596#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift)1597 1598/*define for DATA0 word*/1599/*define for data0 field*/1600#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 41601#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF1602#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 01603#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift)1604 1605 1606/*1607** Definitions for SDMA_PKT_WRITE_TILED packet1608*/1609 1610/*define for HEADER word*/1611/*define for op field*/1612#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 01613#define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF1614#define SDMA_PKT_WRITE_TILED_HEADER_op_shift 01615#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift)1616 1617/*define for sub_op field*/1618#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 01619#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF1620#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 81621#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift)1622 1623/*define for encrypt field*/1624#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 01625#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x000000011626#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 161627#define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift)1628 1629/*define for tmz field*/1630#define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 01631#define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x000000011632#define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 181633#define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift)1634 1635/*define for mip_max field*/1636#define SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset 01637#define SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask 0x0000000F1638#define SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift 201639#define SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask) << SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift)1640 1641/*define for DST_ADDR_LO word*/1642/*define for dst_addr_31_0 field*/1643#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 11644#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF1645#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 01646#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift)1647 1648/*define for DST_ADDR_HI word*/1649/*define for dst_addr_63_32 field*/1650#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 21651#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF1652#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 01653#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift)1654 1655/*define for DW_3 word*/1656/*define for width field*/1657#define SDMA_PKT_WRITE_TILED_DW_3_width_offset 31658#define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF1659#define SDMA_PKT_WRITE_TILED_DW_3_width_shift 01660#define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift)1661 1662/*define for DW_4 word*/1663/*define for height field*/1664#define SDMA_PKT_WRITE_TILED_DW_4_height_offset 41665#define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF1666#define SDMA_PKT_WRITE_TILED_DW_4_height_shift 01667#define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift)1668 1669/*define for depth field*/1670#define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 41671#define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x000007FF1672#define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 161673#define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift)1674 1675/*define for DW_5 word*/1676/*define for element_size field*/1677#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 51678#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x000000071679#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 01680#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift)1681 1682/*define for swizzle_mode field*/1683#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 51684#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F1685#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 31686#define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift)1687 1688/*define for dimension field*/1689#define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 51690#define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x000000031691#define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 91692#define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift)1693 1694/*define for epitch field*/1695#define SDMA_PKT_WRITE_TILED_DW_5_epitch_offset 51696#define SDMA_PKT_WRITE_TILED_DW_5_epitch_mask 0x0000FFFF1697#define SDMA_PKT_WRITE_TILED_DW_5_epitch_shift 161698#define SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_epitch_mask) << SDMA_PKT_WRITE_TILED_DW_5_epitch_shift)1699 1700/*define for DW_6 word*/1701/*define for x field*/1702#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 61703#define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF1704#define SDMA_PKT_WRITE_TILED_DW_6_x_shift 01705#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift)1706 1707/*define for y field*/1708#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 61709#define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF1710#define SDMA_PKT_WRITE_TILED_DW_6_y_shift 161711#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift)1712 1713/*define for DW_7 word*/1714/*define for z field*/1715#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 71716#define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x000007FF1717#define SDMA_PKT_WRITE_TILED_DW_7_z_shift 01718#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift)1719 1720/*define for sw field*/1721#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 71722#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x000000031723#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 241724#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift)1725 1726/*define for COUNT word*/1727/*define for count field*/1728#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 81729#define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF1730#define SDMA_PKT_WRITE_TILED_COUNT_count_shift 01731#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift)1732 1733/*define for DATA0 word*/1734/*define for data0 field*/1735#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 91736#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF1737#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 01738#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift)1739 1740 1741/*1742** Definitions for SDMA_PKT_PTEPDE_COPY packet1743*/1744 1745/*define for HEADER word*/1746/*define for op field*/1747#define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 01748#define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF1749#define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 01750#define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift)1751 1752/*define for sub_op field*/1753#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 01754#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF1755#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 81756#define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift)1757 1758/*define for ptepde_op field*/1759#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 01760#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x000000011761#define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 311762#define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift)1763 1764/*define for SRC_ADDR_LO word*/1765/*define for src_addr_31_0 field*/1766#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 11767#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF1768#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 01769#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift)1770 1771/*define for SRC_ADDR_HI word*/1772/*define for src_addr_63_32 field*/1773#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 21774#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF1775#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 01776#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift)1777 1778/*define for DST_ADDR_LO word*/1779/*define for dst_addr_31_0 field*/1780#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 31781#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF1782#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 01783#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift)1784 1785/*define for DST_ADDR_HI word*/1786/*define for dst_addr_63_32 field*/1787#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 41788#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF1789#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 01790#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift)1791 1792/*define for MASK_DW0 word*/1793/*define for mask_dw0 field*/1794#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 51795#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF1796#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 01797#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift)1798 1799/*define for MASK_DW1 word*/1800/*define for mask_dw1 field*/1801#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 61802#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF1803#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 01804#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift)1805 1806/*define for COUNT word*/1807/*define for count field*/1808#define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 71809#define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF1810#define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 01811#define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift)1812 1813 1814/*1815** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet1816*/1817 1818/*define for HEADER word*/1819/*define for op field*/1820#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 01821#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF1822#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 01823#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift)1824 1825/*define for sub_op field*/1826#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 01827#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF1828#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 81829#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift)1830 1831/*define for pte_size field*/1832#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 01833#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x000000031834#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 281835#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift)1836 1837/*define for direction field*/1838#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 01839#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x000000011840#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 301841#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift)1842 1843/*define for ptepde_op field*/1844#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 01845#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x000000011846#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 311847#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift)1848 1849/*define for SRC_ADDR_LO word*/1850/*define for src_addr_31_0 field*/1851#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 11852#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF1853#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 01854#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift)1855 1856/*define for SRC_ADDR_HI word*/1857/*define for src_addr_63_32 field*/1858#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 21859#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF1860#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 01861#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift)1862 1863/*define for DST_ADDR_LO word*/1864/*define for dst_addr_31_0 field*/1865#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 31866#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF1867#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 01868#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift)1869 1870/*define for DST_ADDR_HI word*/1871/*define for dst_addr_63_32 field*/1872#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 41873#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF1874#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 01875#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift)1876 1877/*define for MASK_BIT_FOR_DW word*/1878/*define for mask_first_xfer field*/1879#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 51880#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF1881#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 01882#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift)1883 1884/*define for mask_last_xfer field*/1885#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 51886#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF1887#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 81888#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift)1889 1890/*define for COUNT_IN_32B_XFER word*/1891/*define for count field*/1892#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 61893#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF1894#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 01895#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift)1896 1897 1898/*1899** Definitions for SDMA_PKT_PTEPDE_RMW packet1900*/1901 1902/*define for HEADER word*/1903/*define for op field*/1904#define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 01905#define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF1906#define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 01907#define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift)1908 1909/*define for sub_op field*/1910#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 01911#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF1912#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 81913#define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift)1914 1915/*define for gcc field*/1916#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 01917#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x000000011918#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 191919#define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift)1920 1921/*define for sys field*/1922#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 01923#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x000000011924#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 201925#define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift)1926 1927/*define for snp field*/1928#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 01929#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x000000011930#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 221931#define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift)1932 1933/*define for gpa field*/1934#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 01935#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x000000011936#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 231937#define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift)1938 1939/*define for ADDR_LO word*/1940/*define for addr_31_0 field*/1941#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 11942#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF1943#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 01944#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift)1945 1946/*define for ADDR_HI word*/1947/*define for addr_63_32 field*/1948#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 21949#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF1950#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 01951#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift)1952 1953/*define for MASK_LO word*/1954/*define for mask_31_0 field*/1955#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 31956#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF1957#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 01958#define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift)1959 1960/*define for MASK_HI word*/1961/*define for mask_63_32 field*/1962#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 41963#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF1964#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 01965#define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift)1966 1967/*define for VALUE_LO word*/1968/*define for value_31_0 field*/1969#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 51970#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF1971#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 01972#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift)1973 1974/*define for VALUE_HI word*/1975/*define for value_63_32 field*/1976#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 61977#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF1978#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 01979#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift)1980 1981 1982/*1983** Definitions for SDMA_PKT_WRITE_INCR packet1984*/1985 1986/*define for HEADER word*/1987/*define for op field*/1988#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 01989#define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF1990#define SDMA_PKT_WRITE_INCR_HEADER_op_shift 01991#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift)1992 1993/*define for sub_op field*/1994#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 01995#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF1996#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 81997#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift)1998 1999/*define for DST_ADDR_LO word*/2000/*define for dst_addr_31_0 field*/2001#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 12002#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF2003#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 02004#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift)2005 2006/*define for DST_ADDR_HI word*/2007/*define for dst_addr_63_32 field*/2008#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 22009#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF2010#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 02011#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift)2012 2013/*define for MASK_DW0 word*/2014/*define for mask_dw0 field*/2015#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 32016#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF2017#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 02018#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift)2019 2020/*define for MASK_DW1 word*/2021/*define for mask_dw1 field*/2022#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 42023#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF2024#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 02025#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift)2026 2027/*define for INIT_DW0 word*/2028/*define for init_dw0 field*/2029#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 52030#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF2031#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 02032#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift)2033 2034/*define for INIT_DW1 word*/2035/*define for init_dw1 field*/2036#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 62037#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF2038#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 02039#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift)2040 2041/*define for INCR_DW0 word*/2042/*define for incr_dw0 field*/2043#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 72044#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF2045#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 02046#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift)2047 2048/*define for INCR_DW1 word*/2049/*define for incr_dw1 field*/2050#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 82051#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF2052#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 02053#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift)2054 2055/*define for COUNT word*/2056/*define for count field*/2057#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 92058#define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF2059#define SDMA_PKT_WRITE_INCR_COUNT_count_shift 02060#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift)2061 2062 2063/*2064** Definitions for SDMA_PKT_INDIRECT packet2065*/2066 2067/*define for HEADER word*/2068/*define for op field*/2069#define SDMA_PKT_INDIRECT_HEADER_op_offset 02070#define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF2071#define SDMA_PKT_INDIRECT_HEADER_op_shift 02072#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift)2073 2074/*define for sub_op field*/2075#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 02076#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF2077#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 82078#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift)2079 2080/*define for vmid field*/2081#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 02082#define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F2083#define SDMA_PKT_INDIRECT_HEADER_vmid_shift 162084#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift)2085 2086/*define for BASE_LO word*/2087/*define for ib_base_31_0 field*/2088#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 12089#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF2090#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 02091#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift)2092 2093/*define for BASE_HI word*/2094/*define for ib_base_63_32 field*/2095#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 22096#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF2097#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 02098#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift)2099 2100/*define for IB_SIZE word*/2101/*define for ib_size field*/2102#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 32103#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF2104#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 02105#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift)2106 2107/*define for CSA_ADDR_LO word*/2108/*define for csa_addr_31_0 field*/2109#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 42110#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF2111#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 02112#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift)2113 2114/*define for CSA_ADDR_HI word*/2115/*define for csa_addr_63_32 field*/2116#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 52117#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF2118#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 02119#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift)2120 2121 2122/*2123** Definitions for SDMA_PKT_SEMAPHORE packet2124*/2125 2126/*define for HEADER word*/2127/*define for op field*/2128#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 02129#define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF2130#define SDMA_PKT_SEMAPHORE_HEADER_op_shift 02131#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift)2132 2133/*define for sub_op field*/2134#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 02135#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF2136#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 82137#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift)2138 2139/*define for write_one field*/2140#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 02141#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x000000012142#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 292143#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift)2144 2145/*define for signal field*/2146#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 02147#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x000000012148#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 302149#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift)2150 2151/*define for mailbox field*/2152#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 02153#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x000000012154#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 312155#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift)2156 2157/*define for ADDR_LO word*/2158/*define for addr_31_0 field*/2159#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 12160#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF2161#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 02162#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift)2163 2164/*define for ADDR_HI word*/2165/*define for addr_63_32 field*/2166#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 22167#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF2168#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 02169#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift)2170 2171 2172/*2173** Definitions for SDMA_PKT_FENCE packet2174*/2175 2176/*define for HEADER word*/2177/*define for op field*/2178#define SDMA_PKT_FENCE_HEADER_op_offset 02179#define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF2180#define SDMA_PKT_FENCE_HEADER_op_shift 02181#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift)2182 2183/*define for sub_op field*/2184#define SDMA_PKT_FENCE_HEADER_sub_op_offset 02185#define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF2186#define SDMA_PKT_FENCE_HEADER_sub_op_shift 82187#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift)2188 2189/*define for ADDR_LO word*/2190/*define for addr_31_0 field*/2191#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 12192#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF2193#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 02194#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift)2195 2196/*define for ADDR_HI word*/2197/*define for addr_63_32 field*/2198#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 22199#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF2200#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 02201#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift)2202 2203/*define for DATA word*/2204/*define for data field*/2205#define SDMA_PKT_FENCE_DATA_data_offset 32206#define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF2207#define SDMA_PKT_FENCE_DATA_data_shift 02208#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift)2209 2210 2211/*2212** Definitions for SDMA_PKT_SRBM_WRITE packet2213*/2214 2215/*define for HEADER word*/2216/*define for op field*/2217#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 02218#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF2219#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 02220#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift)2221 2222/*define for sub_op field*/2223#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 02224#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF2225#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 82226#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift)2227 2228/*define for byte_en field*/2229#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 02230#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F2231#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 282232#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift)2233 2234/*define for ADDR word*/2235/*define for addr field*/2236#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 12237#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF2238#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 02239#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift)2240 2241/*define for DATA word*/2242/*define for data field*/2243#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 22244#define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF2245#define SDMA_PKT_SRBM_WRITE_DATA_data_shift 02246#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift)2247 2248 2249/*2250** Definitions for SDMA_PKT_PRE_EXE packet2251*/2252 2253/*define for HEADER word*/2254/*define for op field*/2255#define SDMA_PKT_PRE_EXE_HEADER_op_offset 02256#define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF2257#define SDMA_PKT_PRE_EXE_HEADER_op_shift 02258#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift)2259 2260/*define for sub_op field*/2261#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 02262#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF2263#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 82264#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift)2265 2266/*define for dev_sel field*/2267#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 02268#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF2269#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 162270#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift)2271 2272/*define for EXEC_COUNT word*/2273/*define for exec_count field*/2274#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 12275#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF2276#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 02277#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift)2278 2279 2280/*2281** Definitions for SDMA_PKT_COND_EXE packet2282*/2283 2284/*define for HEADER word*/2285/*define for op field*/2286#define SDMA_PKT_COND_EXE_HEADER_op_offset 02287#define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF2288#define SDMA_PKT_COND_EXE_HEADER_op_shift 02289#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift)2290 2291/*define for sub_op field*/2292#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 02293#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF2294#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 82295#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift)2296 2297/*define for ADDR_LO word*/2298/*define for addr_31_0 field*/2299#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 12300#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF2301#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 02302#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift)2303 2304/*define for ADDR_HI word*/2305/*define for addr_63_32 field*/2306#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 22307#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF2308#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 02309#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift)2310 2311/*define for REFERENCE word*/2312/*define for reference field*/2313#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 32314#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF2315#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 02316#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift)2317 2318/*define for EXEC_COUNT word*/2319/*define for exec_count field*/2320#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 42321#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF2322#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 02323#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift)2324 2325 2326/*2327** Definitions for SDMA_PKT_CONSTANT_FILL packet2328*/2329 2330/*define for HEADER word*/2331/*define for op field*/2332#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 02333#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF2334#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 02335#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift)2336 2337/*define for sub_op field*/2338#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 02339#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF2340#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 82341#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift)2342 2343/*define for sw field*/2344#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 02345#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x000000032346#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 162347#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift)2348 2349/*define for fillsize field*/2350#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 02351#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x000000032352#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 302353#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift)2354 2355/*define for DST_ADDR_LO word*/2356/*define for dst_addr_31_0 field*/2357#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 12358#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF2359#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 02360#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift)2361 2362/*define for DST_ADDR_HI word*/2363/*define for dst_addr_63_32 field*/2364#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 22365#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF2366#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 02367#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift)2368 2369/*define for DATA word*/2370/*define for src_data_31_0 field*/2371#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 32372#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF2373#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 02374#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift)2375 2376/*define for COUNT word*/2377/*define for count field*/2378#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 42379#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF2380#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 02381#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift)2382 2383 2384/*2385** Definitions for SDMA_PKT_DATA_FILL_MULTI packet2386*/2387 2388/*define for HEADER word*/2389/*define for op field*/2390#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 02391#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF2392#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 02393#define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift)2394 2395/*define for sub_op field*/2396#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 02397#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF2398#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 82399#define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift)2400 2401/*define for memlog_clr field*/2402#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 02403#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x000000012404#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 312405#define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift)2406 2407/*define for BYTE_STRIDE word*/2408/*define for byte_stride field*/2409#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 12410#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF2411#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 02412#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift)2413 2414/*define for DMA_COUNT word*/2415/*define for dma_count field*/2416#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 22417#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF2418#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 02419#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift)2420 2421/*define for DST_ADDR_LO word*/2422/*define for dst_addr_31_0 field*/2423#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 32424#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF2425#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 02426#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift)2427 2428/*define for DST_ADDR_HI word*/2429/*define for dst_addr_63_32 field*/2430#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 42431#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF2432#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 02433#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift)2434 2435/*define for BYTE_COUNT word*/2436/*define for count field*/2437#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 52438#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF2439#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 02440#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift)2441 2442 2443/*2444** Definitions for SDMA_PKT_POLL_REGMEM packet2445*/2446 2447/*define for HEADER word*/2448/*define for op field*/2449#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 02450#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF2451#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 02452#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift)2453 2454/*define for sub_op field*/2455#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 02456#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF2457#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 82458#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift)2459 2460/*define for hdp_flush field*/2461#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 02462#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x000000012463#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 262464#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift)2465 2466/*define for func field*/2467#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 02468#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x000000072469#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 282470#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift)2471 2472/*define for mem_poll field*/2473#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 02474#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x000000012475#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 312476#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift)2477 2478/*define for ADDR_LO word*/2479/*define for addr_31_0 field*/2480#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 12481#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF2482#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 02483#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift)2484 2485/*define for ADDR_HI word*/2486/*define for addr_63_32 field*/2487#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 22488#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF2489#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 02490#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift)2491 2492/*define for VALUE word*/2493/*define for value field*/2494#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 32495#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF2496#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 02497#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift)2498 2499/*define for MASK word*/2500/*define for mask field*/2501#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 42502#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF2503#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 02504#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift)2505 2506/*define for DW5 word*/2507/*define for interval field*/2508#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 52509#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF2510#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 02511#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift)2512 2513/*define for retry_count field*/2514#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 52515#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF2516#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 162517#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift)2518 2519 2520/*2521** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet2522*/2523 2524/*define for HEADER word*/2525/*define for op field*/2526#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 02527#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF2528#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 02529#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift)2530 2531/*define for sub_op field*/2532#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 02533#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF2534#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 82535#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift)2536 2537/*define for SRC_ADDR word*/2538/*define for addr_31_2 field*/2539#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 12540#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF2541#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 22542#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift)2543 2544/*define for DST_ADDR_LO word*/2545/*define for addr_31_0 field*/2546#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 22547#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF2548#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 02549#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift)2550 2551/*define for DST_ADDR_HI word*/2552/*define for addr_63_32 field*/2553#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 32554#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF2555#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 02556#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift)2557 2558 2559/*2560** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet2561*/2562 2563/*define for HEADER word*/2564/*define for op field*/2565#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 02566#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF2567#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 02568#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift)2569 2570/*define for sub_op field*/2571#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 02572#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF2573#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 82574#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift)2575 2576/*define for ea field*/2577#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 02578#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x000000032579#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 162580#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift)2581 2582/*define for DST_ADDR_LO word*/2583/*define for addr_31_0 field*/2584#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 12585#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF2586#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 02587#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift)2588 2589/*define for DST_ADDR_HI word*/2590/*define for addr_63_32 field*/2591#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 22592#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF2593#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 02594#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift)2595 2596/*define for START_PAGE word*/2597/*define for addr_31_4 field*/2598#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 32599#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF2600#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 42601#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift)2602 2603/*define for PAGE_NUM word*/2604/*define for page_num_31_0 field*/2605#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 42606#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF2607#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 02608#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift)2609 2610 2611/*2612** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet2613*/2614 2615/*define for HEADER word*/2616/*define for op field*/2617#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 02618#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF2619#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 02620#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift)2621 2622/*define for sub_op field*/2623#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 02624#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF2625#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 82626#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift)2627 2628/*define for mode field*/2629#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 02630#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x000000012631#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 312632#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift)2633 2634/*define for PATTERN word*/2635/*define for pattern field*/2636#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 12637#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF2638#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 02639#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift)2640 2641/*define for CMP0_ADDR_START_LO word*/2642/*define for cmp0_start_31_0 field*/2643#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 22644#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF2645#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 02646#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift)2647 2648/*define for CMP0_ADDR_START_HI word*/2649/*define for cmp0_start_63_32 field*/2650#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 32651#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF2652#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 02653#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift)2654 2655/*define for CMP0_ADDR_END_LO word*/2656/*define for cmp1_end_31_0 field*/2657#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset 42658#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF2659#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift 02660#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift)2661 2662/*define for CMP0_ADDR_END_HI word*/2663/*define for cmp1_end_63_32 field*/2664#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset 52665#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF2666#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift 02667#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift)2668 2669/*define for CMP1_ADDR_START_LO word*/2670/*define for cmp1_start_31_0 field*/2671#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 62672#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF2673#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 02674#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift)2675 2676/*define for CMP1_ADDR_START_HI word*/2677/*define for cmp1_start_63_32 field*/2678#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 72679#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF2680#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 02681#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift)2682 2683/*define for CMP1_ADDR_END_LO word*/2684/*define for cmp1_end_31_0 field*/2685#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 82686#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF2687#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 02688#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift)2689 2690/*define for CMP1_ADDR_END_HI word*/2691/*define for cmp1_end_63_32 field*/2692#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 92693#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF2694#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 02695#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift)2696 2697/*define for REC_ADDR_LO word*/2698/*define for rec_31_0 field*/2699#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 102700#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF2701#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 02702#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift)2703 2704/*define for REC_ADDR_HI word*/2705/*define for rec_63_32 field*/2706#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 112707#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF2708#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 02709#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift)2710 2711/*define for RESERVED word*/2712/*define for reserved field*/2713#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 122714#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF2715#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 02716#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift)2717 2718 2719/*2720** Definitions for SDMA_PKT_ATOMIC packet2721*/2722 2723/*define for HEADER word*/2724/*define for op field*/2725#define SDMA_PKT_ATOMIC_HEADER_op_offset 02726#define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF2727#define SDMA_PKT_ATOMIC_HEADER_op_shift 02728#define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift)2729 2730/*define for loop field*/2731#define SDMA_PKT_ATOMIC_HEADER_loop_offset 02732#define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x000000012733#define SDMA_PKT_ATOMIC_HEADER_loop_shift 162734#define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift)2735 2736/*define for tmz field*/2737#define SDMA_PKT_ATOMIC_HEADER_tmz_offset 02738#define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x000000012739#define SDMA_PKT_ATOMIC_HEADER_tmz_shift 182740#define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift)2741 2742/*define for atomic_op field*/2743#define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 02744#define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F2745#define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 252746#define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift)2747 2748/*define for ADDR_LO word*/2749/*define for addr_31_0 field*/2750#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 12751#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF2752#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 02753#define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift)2754 2755/*define for ADDR_HI word*/2756/*define for addr_63_32 field*/2757#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 22758#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF2759#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 02760#define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift)2761 2762/*define for SRC_DATA_LO word*/2763/*define for src_data_31_0 field*/2764#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 32765#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF2766#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 02767#define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift)2768 2769/*define for SRC_DATA_HI word*/2770/*define for src_data_63_32 field*/2771#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 42772#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF2773#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 02774#define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift)2775 2776/*define for CMP_DATA_LO word*/2777/*define for cmp_data_31_0 field*/2778#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 52779#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF2780#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 02781#define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift)2782 2783/*define for CMP_DATA_HI word*/2784/*define for cmp_data_63_32 field*/2785#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 62786#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF2787#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 02788#define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift)2789 2790/*define for LOOP_INTERVAL word*/2791/*define for loop_interval field*/2792#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 72793#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF2794#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 02795#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift)2796 2797 2798/*2799** Definitions for SDMA_PKT_TIMESTAMP_SET packet2800*/2801 2802/*define for HEADER word*/2803/*define for op field*/2804#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 02805#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF2806#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 02807#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift)2808 2809/*define for sub_op field*/2810#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 02811#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF2812#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 82813#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift)2814 2815/*define for INIT_DATA_LO word*/2816/*define for init_data_31_0 field*/2817#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 12818#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF2819#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 02820#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift)2821 2822/*define for INIT_DATA_HI word*/2823/*define for init_data_63_32 field*/2824#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 22825#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF2826#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 02827#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift)2828 2829 2830/*2831** Definitions for SDMA_PKT_TIMESTAMP_GET packet2832*/2833 2834/*define for HEADER word*/2835/*define for op field*/2836#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 02837#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF2838#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 02839#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift)2840 2841/*define for sub_op field*/2842#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 02843#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF2844#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 82845#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift)2846 2847/*define for WRITE_ADDR_LO word*/2848/*define for write_addr_31_3 field*/2849#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 12850#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF2851#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 32852#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift)2853 2854/*define for WRITE_ADDR_HI word*/2855/*define for write_addr_63_32 field*/2856#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 22857#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF2858#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 02859#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift)2860 2861 2862/*2863** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet2864*/2865 2866/*define for HEADER word*/2867/*define for op field*/2868#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 02869#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF2870#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 02871#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift)2872 2873/*define for sub_op field*/2874#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 02875#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF2876#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 82877#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift)2878 2879/*define for WRITE_ADDR_LO word*/2880/*define for write_addr_31_3 field*/2881#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 12882#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF2883#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 32884#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift)2885 2886/*define for WRITE_ADDR_HI word*/2887/*define for write_addr_63_32 field*/2888#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 22889#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF2890#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 02891#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift)2892 2893 2894/*2895** Definitions for SDMA_PKT_TRAP packet2896*/2897 2898/*define for HEADER word*/2899/*define for op field*/2900#define SDMA_PKT_TRAP_HEADER_op_offset 02901#define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF2902#define SDMA_PKT_TRAP_HEADER_op_shift 02903#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift)2904 2905/*define for sub_op field*/2906#define SDMA_PKT_TRAP_HEADER_sub_op_offset 02907#define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF2908#define SDMA_PKT_TRAP_HEADER_sub_op_shift 82909#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift)2910 2911/*define for INT_CONTEXT word*/2912/*define for int_context field*/2913#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 12914#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF2915#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 02916#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift)2917 2918 2919/*2920** Definitions for SDMA_PKT_DUMMY_TRAP packet2921*/2922 2923/*define for HEADER word*/2924/*define for op field*/2925#define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 02926#define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF2927#define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 02928#define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift)2929 2930/*define for sub_op field*/2931#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 02932#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF2933#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 82934#define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift)2935 2936/*define for INT_CONTEXT word*/2937/*define for int_context field*/2938#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 12939#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF2940#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 02941#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift)2942 2943 2944/*2945** Definitions for SDMA_PKT_NOP packet2946*/2947 2948/*define for HEADER word*/2949/*define for op field*/2950#define SDMA_PKT_NOP_HEADER_op_offset 02951#define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF2952#define SDMA_PKT_NOP_HEADER_op_shift 02953#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift)2954 2955/*define for sub_op field*/2956#define SDMA_PKT_NOP_HEADER_sub_op_offset 02957#define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF2958#define SDMA_PKT_NOP_HEADER_sub_op_shift 82959#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift)2960 2961/*define for count field*/2962#define SDMA_PKT_NOP_HEADER_count_offset 02963#define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF2964#define SDMA_PKT_NOP_HEADER_count_shift 162965#define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift)2966 2967/*define for DATA0 word*/2968/*define for data0 field*/2969#define SDMA_PKT_NOP_DATA0_data0_offset 12970#define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF2971#define SDMA_PKT_NOP_DATA0_data0_shift 02972#define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift)2973 2974 2975/*2976** Definitions for SDMA_AQL_PKT_HEADER packet2977*/2978 2979/*define for HEADER word*/2980/*define for format field*/2981#define SDMA_AQL_PKT_HEADER_HEADER_format_offset 02982#define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF2983#define SDMA_AQL_PKT_HEADER_HEADER_format_shift 02984#define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift)2985 2986/*define for barrier field*/2987#define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 02988#define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x000000012989#define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 82990#define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift)2991 2992/*define for acquire_fence_scope field*/2993#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 02994#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x000000032995#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 92996#define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift)2997 2998/*define for release_fence_scope field*/2999#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 03000#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x000000033001#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 113002#define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift)3003 3004/*define for reserved field*/3005#define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 03006#define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x000000073007#define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 133008#define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift)3009 3010/*define for op field*/3011#define SDMA_AQL_PKT_HEADER_HEADER_op_offset 03012#define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F3013#define SDMA_AQL_PKT_HEADER_HEADER_op_shift 163014#define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift)3015 3016/*define for subop field*/3017#define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 03018#define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x000000073019#define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 203020#define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift)3021 3022 3023/*3024** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet3025*/3026 3027/*define for HEADER word*/3028/*define for format field*/3029#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 03030#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF3031#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 03032#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift)3033 3034/*define for barrier field*/3035#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 03036#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x000000013037#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 83038#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift)3039 3040/*define for acquire_fence_scope field*/3041#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 03042#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x000000033043#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 93044#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift)3045 3046/*define for release_fence_scope field*/3047#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 03048#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x000000033049#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 113050#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift)3051 3052/*define for reserved field*/3053#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 03054#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x000000073055#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 133056#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift)3057 3058/*define for op field*/3059#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 03060#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F3061#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 163062#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift)3063 3064/*define for subop field*/3065#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 03066#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x000000073067#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 203068#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift)3069 3070/*define for RESERVED_DW1 word*/3071/*define for reserved_dw1 field*/3072#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 13073#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF3074#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 03075#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift)3076 3077/*define for RETURN_ADDR_LO word*/3078/*define for return_addr_31_0 field*/3079#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 23080#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF3081#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 03082#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift)3083 3084/*define for RETURN_ADDR_HI word*/3085/*define for return_addr_63_32 field*/3086#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 33087#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF3088#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 03089#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift)3090 3091/*define for COUNT word*/3092/*define for count field*/3093#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 43094#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF3095#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 03096#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift)3097 3098/*define for PARAMETER word*/3099/*define for dst_sw field*/3100#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 53101#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x000000033102#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 163103#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift)3104 3105/*define for src_sw field*/3106#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 53107#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x000000033108#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 243109#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift)3110 3111/*define for SRC_ADDR_LO word*/3112/*define for src_addr_31_0 field*/3113#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 63114#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF3115#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 03116#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift)3117 3118/*define for SRC_ADDR_HI word*/3119/*define for src_addr_63_32 field*/3120#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 73121#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF3122#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 03123#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift)3124 3125/*define for DST_ADDR_LO word*/3126/*define for dst_addr_31_0 field*/3127#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 83128#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF3129#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 03130#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift)3131 3132/*define for DST_ADDR_HI word*/3133/*define for dst_addr_63_32 field*/3134#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 93135#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF3136#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 03137#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift)3138 3139/*define for RESERVED_DW10 word*/3140/*define for reserved_dw10 field*/3141#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 103142#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF3143#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 03144#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift)3145 3146/*define for RESERVED_DW11 word*/3147/*define for reserved_dw11 field*/3148#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 113149#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF3150#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 03151#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift)3152 3153/*define for RESERVED_DW12 word*/3154/*define for reserved_dw12 field*/3155#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 123156#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF3157#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 03158#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift)3159 3160/*define for RESERVED_DW13 word*/3161/*define for reserved_dw13 field*/3162#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 133163#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF3164#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 03165#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift)3166 3167/*define for COMPLETION_SIGNAL_LO word*/3168/*define for completion_signal_31_0 field*/3169#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 143170#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF3171#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 03172#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift)3173 3174/*define for COMPLETION_SIGNAL_HI word*/3175/*define for completion_signal_63_32 field*/3176#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 153177#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF3178#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 03179#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift)3180 3181 3182/*3183** Definitions for SDMA_AQL_PKT_BARRIER_OR packet3184*/3185 3186/*define for HEADER word*/3187/*define for format field*/3188#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 03189#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF3190#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 03191#define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift)3192 3193/*define for barrier field*/3194#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 03195#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x000000013196#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 83197#define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift)3198 3199/*define for acquire_fence_scope field*/3200#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 03201#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x000000033202#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 93203#define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift)3204 3205/*define for release_fence_scope field*/3206#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 03207#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x000000033208#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 113209#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift)3210 3211/*define for reserved field*/3212#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 03213#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x000000073214#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 133215#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift)3216 3217/*define for op field*/3218#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 03219#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F3220#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 163221#define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift)3222 3223/*define for subop field*/3224#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 03225#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x000000073226#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 203227#define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift)3228 3229/*define for RESERVED_DW1 word*/3230/*define for reserved_dw1 field*/3231#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 13232#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF3233#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 03234#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift)3235 3236/*define for DEPENDENT_ADDR_0_LO word*/3237/*define for dependent_addr_0_31_0 field*/3238#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 23239#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF3240#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 03241#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift)3242 3243/*define for DEPENDENT_ADDR_0_HI word*/3244/*define for dependent_addr_0_63_32 field*/3245#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 33246#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF3247#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 03248#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift)3249 3250/*define for DEPENDENT_ADDR_1_LO word*/3251/*define for dependent_addr_1_31_0 field*/3252#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 43253#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF3254#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 03255#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift)3256 3257/*define for DEPENDENT_ADDR_1_HI word*/3258/*define for dependent_addr_1_63_32 field*/3259#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 53260#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF3261#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 03262#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift)3263 3264/*define for DEPENDENT_ADDR_2_LO word*/3265/*define for dependent_addr_2_31_0 field*/3266#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 63267#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF3268#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 03269#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift)3270 3271/*define for DEPENDENT_ADDR_2_HI word*/3272/*define for dependent_addr_2_63_32 field*/3273#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 73274#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF3275#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 03276#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift)3277 3278/*define for DEPENDENT_ADDR_3_LO word*/3279/*define for dependent_addr_3_31_0 field*/3280#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 83281#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF3282#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 03283#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift)3284 3285/*define for DEPENDENT_ADDR_3_HI word*/3286/*define for dependent_addr_3_63_32 field*/3287#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 93288#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF3289#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 03290#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift)3291 3292/*define for DEPENDENT_ADDR_4_LO word*/3293/*define for dependent_addr_4_31_0 field*/3294#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 103295#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF3296#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 03297#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift)3298 3299/*define for DEPENDENT_ADDR_4_HI word*/3300/*define for dependent_addr_4_63_32 field*/3301#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 113302#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF3303#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 03304#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift)3305 3306/*define for RESERVED_DW12 word*/3307/*define for reserved_dw12 field*/3308#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset 123309#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF3310#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift 03311#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift)3312 3313/*define for RESERVED_DW13 word*/3314/*define for reserved_dw13 field*/3315#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 133316#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF3317#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 03318#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift)3319 3320/*define for COMPLETION_SIGNAL_LO word*/3321/*define for completion_signal_31_0 field*/3322#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 143323#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF3324#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 03325#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift)3326 3327/*define for COMPLETION_SIGNAL_HI word*/3328/*define for completion_signal_63_32 field*/3329#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 153330#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF3331#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 03332#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift)3333 3334 3335#endif /* __SDMA_PKT_OPEN_H_ */3336