219 lines · c
1/* Copyright 2023 Advanced Micro Devices, Inc.2 *3 * Permission is hereby granted, free of charge, to any person obtaining a4 * copy of this software and associated documentation files (the "Software"),5 * to deal in the Software without restriction, including without limitation6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,7 * and/or sell copies of the Software, and to permit persons to whom the8 * Software is furnished to do so, subject to the following conditions:9 *10 * The above copyright notice and this permission notice shall be included in11 * all copies or substantial portions of the Software.12 *13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR19 * OTHER DEALINGS IN THE SOFTWARE.20 *21 * Authors: AMD22 *23 */24 25#ifndef __VPE_6_1_FW_IF_H_26#define __VPE_6_1_FW_IF_H_27 28/****************29 * VPE OP Codes30 ****************/31enum VPE_CMD_OPCODE {32 VPE_CMD_OPCODE_NOP = 0x0,33 VPE_CMD_OPCODE_VPE_DESC = 0x1,34 VPE_CMD_OPCODE_PLANE_CFG = 0x2,35 VPE_CMD_OPCODE_VPEP_CFG = 0x3,36 VPE_CMD_OPCODE_INDIRECT = 0x4,37 VPE_CMD_OPCODE_FENCE = 0x5,38 VPE_CMD_OPCODE_TRAP = 0x6,39 VPE_CMD_OPCODE_REG_WRITE = 0x7,40 VPE_CMD_OPCODE_POLL_REGMEM = 0x8,41 VPE_CMD_OPCODE_COND_EXE = 0x9,42 VPE_CMD_OPCODE_ATOMIC = 0xA,43 VPE_CMD_OPCODE_PRED_EXE = 0xB,44 VPE_CMD_OPCODE_COLLAB_SYNC = 0xC,45 VPE_CMD_OPCODE_TIMESTAMP = 0xD46};47 48/** Generic Command Header49 * Generic Commands include:50 * Noop, Fence, Trap,51 * RegisterWrite, PollRegisterWriteMemory,52 * SetLocalTimestamp, GetLocalTimestamp53 * GetGlobalGPUTimestamp */54#define VPE_HEADER_SUB_OPCODE__SHIFT 855#define VPE_HEADER_SUB_OPCODE_MASK 0x0000FF0056#define VPE_HEADER_OPCODE__SHIFT 057#define VPE_HEADER_OPCODE_MASK 0x000000FF58 59#define VPE_CMD_HEADER(op, subop) \60 (((subop << VPE_HEADER_SUB_OPCODE__SHIFT) & VPE_HEADER_SUB_OPCODE_MASK) | \61 ((op << VPE_HEADER_OPCODE__SHIFT) & VPE_HEADER_OPCODE_MASK))62 63 64 /***************************65 * VPE NOP66 ***************************/67#define VPE_CMD_NOP_HEADER_COUNT__SHIFT 1668#define VPE_CMD_NOP_HEADER_COUNT_MASK 0x00003FFF69 70#define VPE_CMD_NOP_HEADER_COUNT(count) \71 (((count) & VPE_CMD_NOP_HEADER_COUNT_MASK) << VPE_CMD_NOP_HEADER_COUNT__SHIFT)72 73 /***************************74 * VPE Descriptor75 ***************************/76#define VPE_DESC_CD__SHIFT 1677#define VPE_DESC_CD_MASK 0x000F000078 79#define VPE_DESC_CMD_HEADER(cd) \80 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPE_DESC, 0) | \81 (((cd) << VPE_DESC_CD__SHIFT) & VPE_DESC_CD_MASK))82 83 /***************************84 * VPE Plane Config85 ***************************/86enum VPE_PLANE_CFG_SUBOP {87 VPE_PLANE_CFG_SUBOP_1_TO_1 = 0x0,88 VPE_PLANE_CFG_SUBOP_2_TO_1 = 0x1,89 VPE_PLANE_CFG_SUBOP_2_TO_2 = 0x290};91 92#define VPE_PLANE_CFG_ONE_PLANE 093#define VPE_PLANE_CFG_TWO_PLANES 194 95#define VPE_PLANE_CFG_NPS0__SHIFT 1696#define VPE_PLANE_CFG_NPS0_MASK 0x0003000097 98#define VPE_PLANE_CFG_NPD0__SHIFT 1899#define VPE_PLANE_CFG_NPD0_MASK 0x000C0000100 101#define VPE_PLANE_CFG_NPS1__SHIFT 20102#define VPE_PLANE_CFG_NPS1_MASK 0x00300000103 104#define VPE_PLANE_CFG_NPD1__SHIFT 22105#define VPE_PLANE_CFG_NPD1_MASK 0x00C00000106 107#define VPE_PLANE_CFG_TMZ__SHIFT 16108#define VPE_PLANE_CFG_TMZ_MASK 0x00010000109 110#define VPE_PLANE_CFG_SWIZZLE_MODE__SHIFT 3111#define VPE_PLANE_CFG_SWIZZLE_MODE_MASK 0x000000F8112 113#define VPE_PLANE_CFG_ROTATION__SHIFT 0114#define VPE_PLANE_CFG_ROTATION_MASK 0x00000003115 116#define VPE_PLANE_ADDR_LO__SHIFT 0117#define VPE_PLANE_ADDR_LO_MASK 0xFFFFFF00118 119#define VPE_PLANE_CFG_PITCH__SHIFT 0120#define VPE_PLANE_CFG_PITCH_MASK 0x00003FFF121 122#define VPE_PLANE_CFG_VIEWPORT_Y__SHIFT 16123#define VPE_PLANE_CFG_VIEWPORT_Y_MASK 0x3FFF0000124#define VPE_PLANE_CFG_VIEWPORT_X__SHIFT 0125#define VPE_PLANE_CFG_VIEWPORT_X_MASK 0x00003FFF126 127 128#define VPE_PLANE_CFG_VIEWPORT_HEIGHT__SHIFT 16129#define VPE_PLANE_CFG_VIEWPORT_HEIGHT_MASK 0x1FFF0000130#define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE__SHIFT 13131#define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE_MASK 0x0000E000132#define VPE_PLANE_CFG_VIEWPORT_WIDTH__SHIFT 0133#define VPE_PLANE_CFG_VIEWPORT_WIDTH_MASK 0x00001FFF134 135enum VPE_PLANE_CFG_ELEMENT_SIZE {136 VPE_PLANE_CFG_ELEMENT_SIZE_8BPE = 0,137 VPE_PLANE_CFG_ELEMENT_SIZE_16BPE = 1,138 VPE_PLANE_CFG_ELEMENT_SIZE_32BPE = 2,139 VPE_PLANE_CFG_ELEMENT_SIZE_64BPE = 3140};141 142#define VPE_PLANE_CFG_CMD_HEADER(subop, nps0, npd0, nps1, npd1) \143 (VPE_CMD_HEADER(VPE_CMD_OPCODE_PLANE_CFG, subop) | \144 (((nps0) << VPE_PLANE_CFG_NPS0__SHIFT) & VPE_PLANE_CFG_NPS0_MASK) | \145 (((npd0) << VPE_PLANE_CFG_NPD0__SHIFT) & VPE_PLANE_CFG_NPD0_MASK) | \146 (((nps1) << VPE_PLANE_CFG_NPS1__SHIFT) & VPE_PLANE_CFG_NPS1_MASK) | \147 (((npd0) << VPE_PLANE_CFG_NPD1__SHIFT) & VPE_PLANE_CFG_NPD1_MASK))148 149 150/************************151 * VPEP Config152 ************************/153enum VPE_VPEP_CFG_SUBOP {154 VPE_VPEP_CFG_SUBOP_DIR_CFG = 0x0,155 VPE_VPEP_CFG_SUBOP_IND_CFG = 0x1156};157 158 159// Direct Config Command Header160#define VPE_DIR_CFG_HEADER_ARRAY_SIZE__SHIFT 16161#define VPE_DIR_CFG_HEADER_ARRAY_SIZE_MASK 0xFFFF0000162 163#define VPE_DIR_CFG_CMD_HEADER(subop, arr_sz) \164 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, subop) | \165 (((arr_sz) << VPE_DIR_CFG_HEADER_ARRAY_SIZE__SHIFT) & VPE_DIR_CFG_HEADER_ARRAY_SIZE_MASK))166 167 168#define VPE_DIR_CFG_PKT_REGISTER_OFFSET__SHIFT 2169#define VPE_DIR_CFG_PKT_REGISTER_OFFSET_MASK 0x000FFFFC170 171#define VPE_DIR_CFG_PKT_DATA_SIZE__SHIFT 20172#define VPE_DIR_CFG_PKT_DATA_SIZE_MASK 0xFFF00000173 174 175// InDirect Config Command Header176#define VPE_IND_CFG_HEADER_NUM_DST__SHIFT 28177#define VPE_IND_CFG_HEADER_NUM_DST_MASK 0xF0000000178 179#define VPE_IND_CFG_CMD_HEADER(subop, num_dst) \180 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, subop) | \181 (((num_dst) << VPE_IND_CFG_HEADER_NUM_DST__SHIFT) & VPE_IND_CFG_HEADER_NUM_DST_MASK))182 183// Indirect Buffer Command Header184#define VPE_CMD_INDIRECT_HEADER_VMID__SHIFT 16185#define VPE_CMD_INDIRECT_HEADER_VMID_MASK 0x0000000F186#define VPE_CMD_INDIRECT_HEADER_VMID(vmid) \187 (((vmid) & VPE_CMD_INDIRECT_HEADER_VMID_MASK) << VPE_CMD_INDIRECT_HEADER_VMID__SHIFT)188 189 190/**************************191 * Poll Reg/Mem Sub-OpCode192 **************************/193enum VPE_POLL_REGMEM_SUBOP {194 VPE_POLL_REGMEM_SUBOP_REGMEM = 0x0,195 VPE_POLL_REGMEM_SUBOP_REGMEM_WRITE = 0x1196};197 198#define VPE_CMD_POLL_REGMEM_HEADER_FUNC__SHIFT 28199#define VPE_CMD_POLL_REGMEM_HEADER_FUNC_MASK 0x00000007200#define VPE_CMD_POLL_REGMEM_HEADER_FUNC(func) \201 (((func) & VPE_CMD_POLL_REGMEM_HEADER_FUNC_MASK) << VPE_CMD_POLL_REGMEM_HEADER_FUNC__SHIFT)202 203#define VPE_CMD_POLL_REGMEM_HEADER_MEM__SHIFT 31204#define VPE_CMD_POLL_REGMEM_HEADER_MEM_MASK 0x00000001205#define VPE_CMD_POLL_REGMEM_HEADER_MEM(mem) \206 (((mem) & VPE_CMD_POLL_REGMEM_HEADER_MEM_MASK) << VPE_CMD_POLL_REGMEM_HEADER_MEM__SHIFT)207 208#define VPE_CMD_POLL_REGMEM_DW5_INTERVAL__SHIFT 0209#define VPE_CMD_POLL_REGMEM_DW5_INTERVAL_MASK 0x0000FFFF210#define VPE_CMD_POLL_REGMEM_DW5_INTERVAL(interval) \211 (((interval) & VPE_CMD_POLL_REGMEM_DW5_INTERVAL_MASK) << VPE_CMD_POLL_REGMEM_DW5_INTERVAL__SHIFT)212 213#define VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT__SHIFT 16214#define VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT_MASK 0x00000FFF215#define VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(count) \216 (((count) & VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT_MASK) << VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT__SHIFT)217 218#endif219