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1/*2 * Copyright 2015-2017 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22 23/* To compile this assembly code:24 * PROJECT=vi ./sp3 cwsr_trap_handler_gfx8.asm -hex tmp.hex25 */26 27/**************************************************************************/28/* variables */29/**************************************************************************/30var SQ_WAVE_STATUS_INST_ATC_SHIFT = 2331var SQ_WAVE_STATUS_INST_ATC_MASK = 0x0080000032var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 133var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x0000000634var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT = 035var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE = 136var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT = 337var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE = 2938 39var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 1240var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 941var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 842var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 643var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 2444var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits45 46var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x40047var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask48var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 1049var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x10050var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 851var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF52var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x053var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 1054var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF80055var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 1156var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 2157 58var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME59var SQ_WAVE_IB_STS_RCNT_SIZE = 4 //FIXME60var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME61var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE = 1 //FIXME62var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME63 64var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 2465var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 2766 67 68/* Save */69var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes70var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE71 72var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit73var S_SAVE_SPI_INIT_ATC_SHIFT = 2774var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype75var S_SAVE_SPI_INIT_MTYPE_SHIFT = 2876var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG77var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 2678 79var S_SAVE_PC_HI_RCNT_SHIFT = 28 //FIXME check with Brian to ensure all fields other than PC[47:0] can be used80var S_SAVE_PC_HI_RCNT_MASK = 0xF0000000 //FIXME81var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 27 //FIXME82var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x08000000 //FIXME83 84var s_save_spi_init_lo = exec_lo85var s_save_spi_init_hi = exec_hi86 87 //tba_lo and tba_hi need to be saved/restored88var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]}89var s_save_pc_hi = ttmp190var s_save_exec_lo = ttmp291var s_save_exec_hi = ttmp392var s_save_status = ttmp493var s_save_trapsts = ttmp5 //not really used until the end of the SAVE routine94var s_save_xnack_mask_lo = ttmp695var s_save_xnack_mask_hi = ttmp796var s_save_buf_rsrc0 = ttmp897var s_save_buf_rsrc1 = ttmp998var s_save_buf_rsrc2 = ttmp1099var s_save_buf_rsrc3 = ttmp11100 101var s_save_mem_offset = tma_lo102var s_save_alloc_size = s_save_trapsts //conflict103var s_save_tmp = s_save_buf_rsrc2 //shared with s_save_buf_rsrc2 (conflict: should not use mem access with s_save_tmp at the same time)104var s_save_m0 = tma_hi105 106/* Restore */107var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE108var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC109 110var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit111var S_RESTORE_SPI_INIT_ATC_SHIFT = 27112var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype113var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28114var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG115var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26116 117var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT118var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK119var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT120var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK121 122var s_restore_spi_init_lo = exec_lo123var s_restore_spi_init_hi = exec_hi124 125var s_restore_mem_offset = ttmp2126var s_restore_alloc_size = ttmp3127var s_restore_tmp = ttmp6 //tba_lo/hi need to be restored128var s_restore_mem_offset_save = s_restore_tmp //no conflict129 130var s_restore_m0 = s_restore_alloc_size //no conflict131 132var s_restore_mode = ttmp7133 134var s_restore_pc_lo = ttmp0135var s_restore_pc_hi = ttmp1136var s_restore_exec_lo = tma_lo //no conflict137var s_restore_exec_hi = tma_hi //no conflict138var s_restore_status = ttmp4139var s_restore_trapsts = ttmp5140var s_restore_xnack_mask_lo = xnack_mask_lo141var s_restore_xnack_mask_hi = xnack_mask_hi142var s_restore_buf_rsrc0 = ttmp8143var s_restore_buf_rsrc1 = ttmp9144var s_restore_buf_rsrc2 = ttmp10145var s_restore_buf_rsrc3 = ttmp11146 147/**************************************************************************/148/* trap handler entry points */149/**************************************************************************/150/* Shader Main*/151 152shader main153 asic(VI)154 type(CS)155 156 157 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save158 159L_JUMP_TO_RESTORE:160 s_branch L_RESTORE //restore161 162L_SKIP_RESTORE:163 164 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC165 s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK //check whether this is for save166 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS)167 s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save168 s_cbranch_scc1 L_SAVE //this is the operation for save169 170 // ********* Handle non-CWSR traps *******************171 172 /* read tba and tma for next level trap handler, ttmp4 is used as s_save_status */173 s_load_dwordx4 [ttmp8,ttmp9,ttmp10, ttmp11], [tma_lo,tma_hi], 0174 s_waitcnt lgkmcnt(0)175 s_or_b32 ttmp7, ttmp8, ttmp9176 s_cbranch_scc0 L_NO_NEXT_TRAP //next level trap handler not been set177 set_status_without_spi_prio(s_save_status, ttmp2) //restore HW status(SCC)178 s_setpc_b64 [ttmp8,ttmp9] //jump to next level trap handler179 180L_NO_NEXT_TRAP:181 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS)182 s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception183 s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly.184 s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0185 s_addc_u32 ttmp1, ttmp1, 0186L_EXCP_CASE:187 s_and_b32 ttmp1, ttmp1, 0xFFFF188 set_status_without_spi_prio(s_save_status, ttmp2) //restore HW status(SCC)189 s_rfe_b64 [ttmp0, ttmp1]190 191 // ********* End handling of non-CWSR traps *******************192 193/**************************************************************************/194/* save routine */195/**************************************************************************/196 197L_SAVE:198 s_mov_b32 s_save_tmp, 0 //clear saveCtx bit199 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit200 201 s_mov_b32 s_save_xnack_mask_lo, xnack_mask_lo //save XNACK_MASK202 s_mov_b32 s_save_xnack_mask_hi, xnack_mask_hi //save XNACK must before any memory operation203 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) //save RCNT204 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT205 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp206 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) //save FIRST_REPLAY207 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT208 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp209 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY in IB_STS210 s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG211 212 s_setreg_b32 hwreg(HW_REG_IB_STS), s_save_tmp213 214 /* inform SPI the readiness and wait for SPI's go signal */215 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI216 s_mov_b32 s_save_exec_hi, exec_hi217 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive218 219 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC220 221 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for.222 s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT)223 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_tmp224 225 L_SLEEP:226 s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0227 228 s_cbranch_execz L_SLEEP229 230 /* setup Resource Contants */231 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo232 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi233 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE234 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited235 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC236 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK237 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position238 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC239 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK240 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position241 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE242 243 //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?)244 s_mov_b32 s_save_m0, m0 //save M0245 246 /* global mem offset */247 s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0248 249 250 251 252 /* save HW registers */253 //////////////////////////////254 255 L_SAVE_HWREG:256 // HWREG SR memory offset : size(VGPR)+size(SGPR)257 get_vgpr_size_bytes(s_save_mem_offset)258 get_sgpr_size_bytes(s_save_tmp)259 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp260 261 262 s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes263 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes264 265 266 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0267 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC268 write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset)269 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC270 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset)271 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) //STATUS272 273 //s_save_trapsts conflicts with s_save_alloc_size274 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS)275 write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) //TRAPSTS276 277 write_hwreg_to_mem(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_LO278 write_hwreg_to_mem(s_save_xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_HI279 280 //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2281 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE282 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)283 write_hwreg_to_mem(tba_lo, s_save_buf_rsrc0, s_save_mem_offset) //TBA_LO284 write_hwreg_to_mem(tba_hi, s_save_buf_rsrc0, s_save_mem_offset) //TBA_HI285 286 287 288 /* the first wave in the threadgroup */289 // save fist_wave bits in tba_hi unused bit.26290 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit291 //s_or_b32 tba_hi, s_save_tmp, tba_hi // save first wave bit to tba_hi.bits[26]292 s_mov_b32 s_save_exec_hi, 0x0293 s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26]294 295 296 /* save SGPRs */297 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save...298 //////////////////////////////299 300 // SGPR SR memory offset : size(VGPR)301 get_vgpr_size_bytes(s_save_mem_offset)302 // TODO, change RSRC word to rearrange memory layout for SGPRS303 304 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size305 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1306 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value)307 308 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes309 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes310 311 // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0312 //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0313 s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0314 s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset315 s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0316 317 s_mov_b32 m0, 0x0 //SGPR initial index value =0318 L_SAVE_SGPR_LOOP:319 // SGPR is allocated in 16 SGPR granularity320 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0]321 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0]322 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0]323 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0]324 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0]325 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0]326 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0]327 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0]328 329 write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4330 s_add_u32 m0, m0, 16 //next sgpr index331 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0332 s_cbranch_scc1 L_SAVE_SGPR_LOOP //SGPR save is complete?333 // restore s_save_buf_rsrc0,1334 //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo335 s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo336 337 338 339 340 /* save first 4 VGPR, then LDS save could use */341 // each wave will alloc 4 vgprs at least...342 /////////////////////////////////////////////////////////////////////////////////////343 344 s_mov_b32 s_save_mem_offset, 0345 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on346 s_mov_b32 exec_hi, 0xFFFFFFFF347 348 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes349 350 // VGPR Allocated in 4-GPR granularity351 352 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1353 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256354 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2355 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3356 357 358 359 /* save LDS */360 //////////////////////////////361 362 L_SAVE_LDS:363 364 // Change EXEC to all threads...365 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on366 s_mov_b32 exec_hi, 0xFFFFFFFF367 368 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size369 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero?370 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE371 372 s_barrier //LDS is used? wait for other waves in the same TG373 //s_and_b32 s_save_tmp, tba_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here374 s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here375 s_cbranch_scc0 L_SAVE_LDS_DONE376 377 // first wave do LDS save;378 379 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw380 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes381 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes382 383 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG)384 //385 get_vgpr_size_bytes(s_save_mem_offset)386 get_sgpr_size_bytes(s_save_tmp)387 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp388 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes()389 390 391 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes392 s_mov_b32 m0, 0x0 //lds_offset initial value = 0393 394 395 v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0396 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid397 v_mul_i32_i24 v2, v3, 8 // tid*8398 v_mov_b32 v3, 256*2399 s_mov_b32 m0, 0x10000400 s_mov_b32 s0, s_save_buf_rsrc3401 s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF // disable add_tid402 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000 //DFMT403 404L_SAVE_LDS_LOOP_VECTOR:405 ds_read_b64 v[0:1], v2 //x =LDS[a], byte address406 s_waitcnt lgkmcnt(0)407 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1408// s_waitcnt vmcnt(0)409 v_add_u32 v2, vcc[0:1], v2, v3410 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size411 s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR412 413 // restore rsrc3414 s_mov_b32 s_save_buf_rsrc3, s0415 416L_SAVE_LDS_DONE:417 418 419 /* save VGPRs - set the Rest VGPRs */420 //////////////////////////////////////////////////////////////////////////////////////421 L_SAVE_VGPR:422 // VGPR SR memory offset: 0423 // TODO rearrange the RSRC words to use swizzle for VGPR save...424 425 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs426 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on427 s_mov_b32 exec_hi, 0xFFFFFFFF428 429 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size430 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1431 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible432 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4)433 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes434 435 // VGPR store using dw burst436 s_mov_b32 m0, 0x4 //VGPR initial index value =0437 s_cmp_lt_u32 m0, s_save_alloc_size438 s_cbranch_scc0 L_SAVE_VGPR_END439 440 441 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1442 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later443 444 L_SAVE_VGPR_LOOP:445 v_mov_b32 v0, v0 //v0 = v[0+m0]446 v_mov_b32 v1, v1 //v0 = v[0+m0]447 v_mov_b32 v2, v2 //v0 = v[0+m0]448 v_mov_b32 v3, v3 //v0 = v[0+m0]449 450 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1451 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256452 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2453 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3454 455 s_add_u32 m0, m0, 4 //next vgpr index456 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes457 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0458 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete?459 s_set_gpr_idx_off460 461L_SAVE_VGPR_END:462 s_branch L_END_PGM463 464 465 466/**************************************************************************/467/* restore routine */468/**************************************************************************/469 470L_RESTORE:471 /* Setup Resource Contants */472 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo473 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi474 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE475 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes)476 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC477 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK478 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position479 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC480 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK481 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position482 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE483 484 /* global mem offset */485// s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0486 487 /* the first wave in the threadgroup */488 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK489 s_cbranch_scc0 L_RESTORE_VGPR490 491 /* restore LDS */492 //////////////////////////////493 L_RESTORE_LDS:494 495 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead496 s_mov_b32 exec_hi, 0xFFFFFFFF497 498 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size499 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero?500 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR501 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw502 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes503 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes504 505 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG)506 //507 get_vgpr_size_bytes(s_restore_mem_offset)508 get_sgpr_size_bytes(s_restore_tmp)509 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp510 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow???511 512 513 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes514 s_mov_b32 m0, 0x0 //lds_offset initial value = 0515 516 L_RESTORE_LDS_LOOP:517 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW518 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW519 s_add_u32 m0, m0, 256*2 // 128 DW520 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW521 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0522 s_cbranch_scc1 L_RESTORE_LDS_LOOP //LDS restore is complete?523 524 525 /* restore VGPRs */526 //////////////////////////////527 L_RESTORE_VGPR:528 // VGPR SR memory offset : 0529 s_mov_b32 s_restore_mem_offset, 0x0530 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead531 s_mov_b32 exec_hi, 0xFFFFFFFF532 533 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size534 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1535 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value)536 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4)537 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes538 539 // VGPR load using dw burst540 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last541 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4542 s_mov_b32 m0, 4 //VGPR initial index value = 1543 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8544 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later545 546 L_RESTORE_VGPR_LOOP:547 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1548 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256549 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2550 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3551 s_waitcnt vmcnt(0) //ensure data ready552 v_mov_b32 v0, v0 //v[0+m0] = v0553 v_mov_b32 v1, v1554 v_mov_b32 v2, v2555 v_mov_b32 v3, v3556 s_add_u32 m0, m0, 4 //next vgpr index557 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes558 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0559 s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete?560 s_set_gpr_idx_off561 /* VGPR restore on v0 */562 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1563 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256564 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2565 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3566 s_waitcnt vmcnt(0)567 568 /* restore SGPRs */569 //////////////////////////////570 571 // SGPR SR memory offset : size(VGPR)572 get_vgpr_size_bytes(s_restore_mem_offset)573 get_sgpr_size_bytes(s_restore_tmp)574 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp575 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group576 // TODO, change RSRC word to rearrange memory layout for SGPRS577 578 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size579 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1580 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value)581 582 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes583 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes584 585 /* If 112 SGPRs ar allocated, 4 sgprs are not used TBA(108,109),TMA(110,111),586 However, we are safe to restore these 4 SGPRs anyway, since TBA,TMA will later be restored by HWREG587 */588 s_mov_b32 m0, s_restore_alloc_size589 590 L_RESTORE_SGPR_LOOP:591 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) //PV: further performance improvement can be made592 s_waitcnt lgkmcnt(0) //ensure data ready593 594 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0]595 596 s_movreld_b64 s0, s0 //s[0+m0] = s0597 s_movreld_b64 s2, s2598 s_movreld_b64 s4, s4599 s_movreld_b64 s6, s6600 s_movreld_b64 s8, s8601 s_movreld_b64 s10, s10602 s_movreld_b64 s12, s12603 s_movreld_b64 s14, s14604 605 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0606 s_cbranch_scc0 L_RESTORE_SGPR_LOOP //SGPR restore (except s0) is complete?607 608 /* restore HW registers */609 //////////////////////////////610 L_RESTORE_HWREG:611 612 // HWREG SR memory offset : size(VGPR)+size(SGPR)613 get_vgpr_size_bytes(s_restore_mem_offset)614 get_sgpr_size_bytes(s_restore_tmp)615 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp616 617 618 s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes619 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes620 621 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0622 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC623 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset)624 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //EXEC625 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset)626 read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) //STATUS627 read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) //TRAPSTS628 read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_LO629 read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_HI630 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) //MODE631 read_hwreg_from_mem(tba_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //TBA_LO632 read_hwreg_from_mem(tba_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //TBA_HI633 634 s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS635 636 s_mov_b32 m0, s_restore_m0637 s_mov_b32 exec_lo, s_restore_exec_lo638 s_mov_b32 exec_hi, s_restore_exec_hi639 640 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts641 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0642 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts643 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT644 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0645 //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore646 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode647 //reuse s_restore_m0 as a temp register648 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK649 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT650 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT651 s_mov_b32 s_restore_tmp, 0x0 //IB_STS is zero652 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0653 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK654 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT655 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT656 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0657 s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK658 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT659 s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_tmp660 661 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS662 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32663 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32664 set_status_without_spi_prio(s_restore_status, s_restore_tmp) // SCC is included, which is changed by previous salu665 666 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time667 668// s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution669 s_rfe_restore_b64 s_restore_pc_lo, s_restore_m0 // s_restore_m0[0] is used to set STATUS.inst_atc670 671 672/**************************************************************************/673/* the END */674/**************************************************************************/675L_END_PGM:676 s_endpgm677 678end679 680 681/**************************************************************************/682/* the helper functions */683/**************************************************************************/684 685//Only for save hwreg to mem686function write_hwreg_to_mem(s, s_rsrc, s_mem_offset)687 s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on688 s_mov_b32 m0, s_mem_offset689 s_buffer_store_dword s, s_rsrc, m0 glc:1690 s_add_u32 s_mem_offset, s_mem_offset, 4691 s_mov_b32 m0, exec_lo692end693 694 695// HWREG are saved before SGPRs, so all HWREG could be use.696function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset)697 698 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1699 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1700 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1701 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1702 s_add_u32 s_rsrc[0], s_rsrc[0], 4*16703 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc704end705 706 707function read_hwreg_from_mem(s, s_rsrc, s_mem_offset)708 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1709 s_add_u32 s_mem_offset, s_mem_offset, 4710end711 712function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset)713 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1714 s_sub_u32 s_mem_offset, s_mem_offset, 4*16715end716 717 718 719function get_lds_size_bytes(s_lds_size_byte)720 // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW721 s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) // lds_size722 s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW723end724 725function get_vgpr_size_bytes(s_vgpr_size_byte)726 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size727 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1728 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible729end730 731function get_sgpr_size_bytes(s_sgpr_size_byte)732 s_getreg_b32 s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size733 s_add_u32 s_sgpr_size_byte, s_sgpr_size_byte, 1734 s_lshl_b32 s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4 (non-zero value)735end736 737function get_hwreg_size_bytes738 return 128 //HWREG size 128 bytes739end740 741function set_status_without_spi_prio(status, tmp)742 // Do not restore STATUS.SPI_PRIO since scheduler may have raised it.743 s_lshr_b32 tmp, status, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT744 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE), tmp745 s_nop 0x2 // avoid S_SETREG => S_SETREG hazard746 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE), status747end748