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1/*2 * Copyright 2021 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22 23#include "kfd_priv.h"24#include "kfd_events.h"25#include "soc15_int.h"26#include "kfd_device_queue_manager.h"27#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"28#include "kfd_smi_events.h"29#include "kfd_debug.h"30 31/*32 * GFX11 SQ Interrupts33 *34 * There are 3 encoding types of interrupts sourced from SQ sent as a 44-bit35 * packet to the Interrupt Handler:36 * Auto - Generated by the SQG (various cmd overflows, timestamps etc)37 * Wave - Generated by S_SENDMSG through a shader program38 * Error - HW generated errors (Illegal instructions, Memviols, EDC etc)39 *40 * The 44-bit packet is mapped as {context_id1[7:0],context_id0[31:0]} plus41 * 4-bits for VMID (SOC15_VMID_FROM_IH_ENTRY) as such:42 *43 * - context_id1[7:6]44 * Encoding type (0 = Auto, 1 = Wave, 2 = Error)45 *46 * - context_id0[26]47 * PRIV bit indicates that Wave S_SEND or error occurred within trap48 *49 * - context_id0[24:0]50 * 25-bit data with the following layout per encoding type:51 * Auto - only context_id0[8:0] is used, which reports various interrupts52 * generated by SQG. The rest is 0.53 * Wave - user data sent from m0 via S_SENDMSG (context_id0[23:0])54 * Error - Error Type (context_id0[24:21]), Error Details (context_id0[20:0])55 *56 * The other context_id bits show coordinates (SE/SH/CU/SIMD/WGP) for wave57 * S_SENDMSG and Errors. These are 0 for Auto.58 */59 60enum SQ_INTERRUPT_WORD_ENCODING {61 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,62 SQ_INTERRUPT_WORD_ENCODING_INST,63 SQ_INTERRUPT_WORD_ENCODING_ERROR,64};65 66enum SQ_INTERRUPT_ERROR_TYPE {67 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0,68 SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST,69 SQ_INTERRUPT_ERROR_TYPE_MEMVIOL,70 SQ_INTERRUPT_ERROR_TYPE_EDC_FED,71};72 73/* SQ_INTERRUPT_WORD_AUTO_CTXID */74#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE__SHIFT 075#define SQ_INTERRUPT_WORD_AUTO_CTXID0__WLT__SHIFT 176#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF_FULL__SHIFT 277#define SQ_INTERRUPT_WORD_AUTO_CTXID0__REG_TIMESTAMP__SHIFT 378#define SQ_INTERRUPT_WORD_AUTO_CTXID0__CMD_TIMESTAMP__SHIFT 479#define SQ_INTERRUPT_WORD_AUTO_CTXID0__HOST_CMD_OVERFLOW__SHIFT 580#define SQ_INTERRUPT_WORD_AUTO_CTXID0__HOST_REG_OVERFLOW__SHIFT 681#define SQ_INTERRUPT_WORD_AUTO_CTXID0__IMMED_OVERFLOW__SHIFT 782#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_UTC_ERROR__SHIFT 883#define SQ_INTERRUPT_WORD_AUTO_CTXID1__ENCODING__SHIFT 684 85#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_MASK 0x0000000186#define SQ_INTERRUPT_WORD_AUTO_CTXID0__WLT_MASK 0x0000000287#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF_FULL_MASK 0x0000000488#define SQ_INTERRUPT_WORD_AUTO_CTXID0__REG_TIMESTAMP_MASK 0x0000000889#define SQ_INTERRUPT_WORD_AUTO_CTXID0__CMD_TIMESTAMP_MASK 0x0000001090#define SQ_INTERRUPT_WORD_AUTO_CTXID0__HOST_CMD_OVERFLOW_MASK 0x0000002091#define SQ_INTERRUPT_WORD_AUTO_CTXID0__HOST_REG_OVERFLOW_MASK 0x0000004092#define SQ_INTERRUPT_WORD_AUTO_CTXID0__IMMED_OVERFLOW_MASK 0x0000008093#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_UTC_ERROR_MASK 0x0000010094#define SQ_INTERRUPT_WORD_AUTO_CTXID1__ENCODING_MASK 0x000000c095 96/* SQ_INTERRUPT_WORD_WAVE_CTXID */97#define SQ_INTERRUPT_WORD_WAVE_CTXID0__DATA__SHIFT 098#define SQ_INTERRUPT_WORD_WAVE_CTXID0__SH_ID__SHIFT 2599#define SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV__SHIFT 26100#define SQ_INTERRUPT_WORD_WAVE_CTXID0__WAVE_ID__SHIFT 27101#define SQ_INTERRUPT_WORD_WAVE_CTXID1__SIMD_ID__SHIFT 0102#define SQ_INTERRUPT_WORD_WAVE_CTXID1__WGP_ID__SHIFT 2103#define SQ_INTERRUPT_WORD_WAVE_CTXID1__ENCODING__SHIFT 6104 105#define SQ_INTERRUPT_WORD_WAVE_CTXID0__DATA_MASK 0x00ffffff /* [23:0] */106#define SQ_INTERRUPT_WORD_WAVE_CTXID0__SH_ID_MASK 0x02000000 /* [25] */107#define SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV_MASK 0x04000000 /* [26] */108#define SQ_INTERRUPT_WORD_WAVE_CTXID0__WAVE_ID_MASK 0xf8000000 /* [31:27] */109#define SQ_INTERRUPT_WORD_WAVE_CTXID1__SIMD_ID_MASK 0x00000003 /* [33:32] */110#define SQ_INTERRUPT_WORD_WAVE_CTXID1__WGP_ID_MASK 0x0000003c /* [37:34] */111#define SQ_INTERRUPT_WORD_WAVE_CTXID1__ENCODING_MASK 0x000000c0 /* [39:38] */112 113/* SQ_INTERRUPT_WORD_ERROR_CTXID */114#define SQ_INTERRUPT_WORD_ERROR_CTXID0__DETAIL__SHIFT 0115#define SQ_INTERRUPT_WORD_ERROR_CTXID0__TYPE__SHIFT 21116#define SQ_INTERRUPT_WORD_ERROR_CTXID0__SH_ID__SHIFT 25117#define SQ_INTERRUPT_WORD_ERROR_CTXID0__PRIV__SHIFT 26118#define SQ_INTERRUPT_WORD_ERROR_CTXID0__WAVE_ID__SHIFT 27119#define SQ_INTERRUPT_WORD_ERROR_CTXID1__SIMD_ID__SHIFT 0120#define SQ_INTERRUPT_WORD_ERROR_CTXID1__WGP_ID__SHIFT 2121#define SQ_INTERRUPT_WORD_ERROR_CTXID1__ENCODING__SHIFT 6122 123#define SQ_INTERRUPT_WORD_ERROR_CTXID0__DETAIL_MASK 0x001fffff /* [20:0] */124#define SQ_INTERRUPT_WORD_ERROR_CTXID0__TYPE_MASK 0x01e00000 /* [24:21] */125#define SQ_INTERRUPT_WORD_ERROR_CTXID0__SH_ID_MASK 0x02000000 /* [25] */126#define SQ_INTERRUPT_WORD_ERROR_CTXID0__PRIV_MASK 0x04000000 /* [26] */127#define SQ_INTERRUPT_WORD_ERROR_CTXID0__WAVE_ID_MASK 0xf8000000 /* [31:27] */128#define SQ_INTERRUPT_WORD_ERROR_CTXID1__SIMD_ID_MASK 0x00000003 /* [33:32] */129#define SQ_INTERRUPT_WORD_ERROR_CTXID1__WGP_ID_MASK 0x0000003c /* [37:34] */130#define SQ_INTERRUPT_WORD_ERROR_CTXID1__ENCODING_MASK 0x000000c0 /* [39:38] */131 132/*133 * The debugger will send user data(m0) with PRIV=1 to indicate it requires134 * notification from the KFD with the following queue id (DOORBELL_ID) and135 * trap code (TRAP_CODE).136 */137#define KFD_CTXID0_TRAP_CODE_SHIFT 10138#define KFD_CTXID0_TRAP_CODE_MASK 0xfffc00139#define KFD_CTXID0_CP_BAD_OP_ECODE_MASK 0x3ffffff140#define KFD_CTXID0_DOORBELL_ID_MASK 0x0003ff141 142#define KFD_CTXID0_TRAP_CODE(ctxid0) (((ctxid0) & \143 KFD_CTXID0_TRAP_CODE_MASK) >> \144 KFD_CTXID0_TRAP_CODE_SHIFT)145#define KFD_CTXID0_CP_BAD_OP_ECODE(ctxid0) (((ctxid0) & \146 KFD_CTXID0_CP_BAD_OP_ECODE_MASK) >> \147 KFD_CTXID0_TRAP_CODE_SHIFT)148#define KFD_CTXID0_DOORBELL_ID(ctxid0) ((ctxid0) & \149 KFD_CTXID0_DOORBELL_ID_MASK)150 151static void print_sq_intr_info_auto(uint32_t context_id0, uint32_t context_id1)152{153 pr_debug_ratelimited(154 "sq_intr: auto, ttrace %d, wlt %d, ttrace_buf_full %d, reg_tms %d, cmd_tms %d, host_cmd_ovf %d, host_reg_ovf %d, immed_ovf %d, ttrace_utc_err %d\n",155 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE),156 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, WLT),157 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE_BUF_FULL),158 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, REG_TIMESTAMP),159 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, CMD_TIMESTAMP),160 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, HOST_CMD_OVERFLOW),161 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, HOST_REG_OVERFLOW),162 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, IMMED_OVERFLOW),163 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE_UTC_ERROR));164}165 166static void print_sq_intr_info_inst(uint32_t context_id0, uint32_t context_id1)167{168 pr_debug_ratelimited(169 "sq_intr: inst, data 0x%08x, sh %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n",170 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, DATA),171 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, SH_ID),172 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, PRIV),173 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, WAVE_ID),174 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1, SIMD_ID),175 REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1, WGP_ID));176}177 178static void print_sq_intr_info_error(uint32_t context_id0, uint32_t context_id1)179{180 pr_warn_ratelimited(181 "sq_intr: error, detail 0x%08x, type %d, sh %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n",182 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, DETAIL),183 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, TYPE),184 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, SH_ID),185 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, PRIV),186 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, WAVE_ID),187 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID1, SIMD_ID),188 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID1, WGP_ID));189}190 191static void event_interrupt_poison_consumption_v11(struct kfd_node *dev,192 uint16_t pasid, uint16_t source_id)193{194 enum amdgpu_ras_block block = 0;195 int ret = -EINVAL;196 uint32_t reset = 0;197 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);198 199 if (!p)200 return;201 202 /* all queues of a process will be unmapped in one time */203 if (atomic_read(&p->poison)) {204 kfd_unref_process(p);205 return;206 }207 208 atomic_set(&p->poison, 1);209 kfd_unref_process(p);210 211 switch (source_id) {212 case SOC15_INTSRC_SQ_INTERRUPT_MSG:213 if (dev->dqm->ops.reset_queues)214 ret = dev->dqm->ops.reset_queues(dev->dqm, pasid);215 block = AMDGPU_RAS_BLOCK__GFX;216 if (ret)217 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;218 break;219 case SOC21_INTSRC_SDMA_ECC:220 default:221 block = AMDGPU_RAS_BLOCK__GFX;222 reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;223 break;224 }225 226 kfd_signal_poison_consumed_event(dev, pasid);227 228 /* resetting queue passes, do page retirement without gpu reset229 resetting queue fails, fallback to gpu reset solution */230 amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, block, reset);231}232 233static bool event_interrupt_isr_v11(struct kfd_node *dev,234 const uint32_t *ih_ring_entry,235 uint32_t *patched_ihre,236 bool *patched_flag)237{238 uint16_t source_id, client_id, pasid, vmid;239 const uint32_t *data = ih_ring_entry;240 uint32_t context_id0;241 242 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);243 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);244 /* Only handle interrupts from KFD VMIDs */245 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);246 if (!KFD_IRQ_IS_FENCE(client_id, source_id) &&247 (vmid < dev->vm_info.first_vmid_kfd ||248 vmid > dev->vm_info.last_vmid_kfd))249 return false;250 251 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);252 context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);253 254 if ((source_id == SOC15_INTSRC_CP_END_OF_PIPE) &&255 (context_id0 & AMDGPU_FENCE_MES_QUEUE_FLAG))256 return false;257 258 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",259 client_id, source_id, vmid, pasid);260 pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n",261 data[0], data[1], data[2], data[3],262 data[4], data[5], data[6], data[7]);263 264 /* If there is no valid PASID, it's likely a bug */265 if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt"))266 return false;267 268 /* Interrupt types we care about: various signals and faults.269 * They will be forwarded to a work queue (see below).270 */271 return source_id == SOC15_INTSRC_CP_END_OF_PIPE ||272 source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG ||273 source_id == SOC15_INTSRC_CP_BAD_OPCODE ||274 source_id == SOC21_INTSRC_SDMA_TRAP ||275 KFD_IRQ_IS_FENCE(client_id, source_id) ||276 (((client_id == SOC21_IH_CLIENTID_VMC) ||277 ((client_id == SOC21_IH_CLIENTID_GFX) &&278 (source_id == UTCL2_1_0__SRCID__FAULT))) &&279 !amdgpu_no_queue_eviction_on_vm_fault);280}281 282static void event_interrupt_wq_v11(struct kfd_node *dev,283 const uint32_t *ih_ring_entry)284{285 uint16_t source_id, client_id, ring_id, pasid, vmid;286 uint32_t context_id0, context_id1;287 uint8_t sq_int_enc, sq_int_priv, sq_int_errtype;288 struct kfd_vm_fault_info info = {0};289 struct kfd_hsa_memory_exception_data exception_data;290 291 source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);292 client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);293 ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry);294 pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);295 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);296 context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);297 context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry);298 299 /* VMC, UTCL2 */300 if (client_id == SOC21_IH_CLIENTID_VMC ||301 ((client_id == SOC21_IH_CLIENTID_GFX) &&302 (source_id == UTCL2_1_0__SRCID__FAULT))) {303 304 info.vmid = vmid;305 info.mc_id = client_id;306 info.page_addr = ih_ring_entry[4] |307 (uint64_t)(ih_ring_entry[5] & 0xf) << 32;308 info.prot_valid = ring_id & 0x08;309 info.prot_read = ring_id & 0x10;310 info.prot_write = ring_id & 0x20;311 312 memset(&exception_data, 0, sizeof(exception_data));313 exception_data.gpu_id = dev->id;314 exception_data.va = (info.page_addr) << PAGE_SHIFT;315 exception_data.failure.NotPresent = info.prot_valid ? 1 : 0;316 exception_data.failure.NoExecute = info.prot_exec ? 1 : 0;317 exception_data.failure.ReadOnly = info.prot_write ? 1 : 0;318 exception_data.failure.imprecise = 0;319 320 kfd_set_dbg_ev_from_interrupt(dev, pasid, -1,321 KFD_EC_MASK(EC_DEVICE_MEMORY_VIOLATION),322 &exception_data, sizeof(exception_data));323 kfd_smi_event_update_vmfault(dev, pasid);324 325 /* GRBM, SDMA, SE, PMM */326 } else if (client_id == SOC21_IH_CLIENTID_GRBM_CP ||327 client_id == SOC21_IH_CLIENTID_GFX) {328 329 /* CP */330 if (source_id == SOC15_INTSRC_CP_END_OF_PIPE)331 kfd_signal_event_interrupt(pasid, context_id0, 32);332 else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE &&333 KFD_DBG_EC_TYPE_IS_PACKET(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0))) {334 u32 doorbell_id = KFD_CTXID0_DOORBELL_ID(context_id0);335 336 kfd_set_dbg_ev_from_interrupt(dev, pasid, doorbell_id,337 KFD_EC_MASK(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0)),338 NULL, 0);339 kfd_dqm_suspend_bad_queue_mes(dev, pasid, doorbell_id);340 }341 342 /* SDMA */343 else if (source_id == SOC21_INTSRC_SDMA_TRAP)344 kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);345 else if (source_id == SOC21_INTSRC_SDMA_ECC) {346 event_interrupt_poison_consumption_v11(dev, pasid, source_id);347 return;348 }349 350 /* SQ */351 else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) {352 sq_int_enc = REG_GET_FIELD(context_id1,353 SQ_INTERRUPT_WORD_WAVE_CTXID1, ENCODING);354 switch (sq_int_enc) {355 case SQ_INTERRUPT_WORD_ENCODING_AUTO:356 print_sq_intr_info_auto(context_id0, context_id1);357 break;358 case SQ_INTERRUPT_WORD_ENCODING_INST:359 print_sq_intr_info_inst(context_id0, context_id1);360 sq_int_priv = REG_GET_FIELD(context_id0,361 SQ_INTERRUPT_WORD_WAVE_CTXID0, PRIV);362 if (sq_int_priv && (kfd_set_dbg_ev_from_interrupt(dev, pasid,363 KFD_CTXID0_DOORBELL_ID(context_id0),364 KFD_CTXID0_TRAP_CODE(context_id0),365 NULL, 0)))366 return;367 break;368 case SQ_INTERRUPT_WORD_ENCODING_ERROR:369 print_sq_intr_info_error(context_id0, context_id1);370 sq_int_errtype = REG_GET_FIELD(context_id0,371 SQ_INTERRUPT_WORD_ERROR_CTXID0, TYPE);372 if (sq_int_errtype != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &&373 sq_int_errtype != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) {374 event_interrupt_poison_consumption_v11(375 dev, pasid, source_id);376 return;377 }378 break;379 default:380 break;381 }382 kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24);383 }384 385 } else if (KFD_IRQ_IS_FENCE(client_id, source_id)) {386 kfd_process_close_interrupt_drain(pasid);387 }388}389 390const struct kfd_event_interrupt_class event_interrupt_class_v11 = {391 .interrupt_isr = event_interrupt_isr_v11,392 .interrupt_wq = event_interrupt_wq_v11,393};394