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1/* SPDX-License-Identifier: GPL-2.0 OR MIT */2/*3 * Copyright 2014-2022 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 */23 24#ifndef __KFD_TOPOLOGY_H__25#define __KFD_TOPOLOGY_H__26 27#include <linux/types.h>28#include <linux/list.h>29#include <linux/kfd_sysfs.h>30#include "kfd_crat.h"31 32#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 3233 34#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9 635#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9_4_3 736#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 737#define HSA_DBG_WATCH_ADDR_MASK_HI_BIT \38 (29 << HSA_DBG_WATCH_ADDR_MASK_HI_BIT_SHIFT)39#define HSA_DBG_WATCH_ADDR_MASK_HI_BIT_GFX9_4_3 \40 (30 << HSA_DBG_WATCH_ADDR_MASK_HI_BIT_SHIFT)41 42struct kfd_node_properties {43 uint64_t hive_id;44 uint32_t cpu_cores_count;45 uint32_t simd_count;46 uint32_t mem_banks_count;47 uint32_t caches_count;48 uint32_t io_links_count;49 uint32_t p2p_links_count;50 uint32_t cpu_core_id_base;51 uint32_t simd_id_base;52 uint32_t capability;53 uint64_t debug_prop;54 uint32_t max_waves_per_simd;55 uint32_t lds_size_in_kb;56 uint32_t gds_size_in_kb;57 uint32_t num_gws;58 uint32_t wave_front_size;59 uint32_t array_count;60 uint32_t simd_arrays_per_engine;61 uint32_t cu_per_simd_array;62 uint32_t simd_per_cu;63 uint32_t max_slots_scratch_cu;64 uint32_t engine_id;65 uint32_t gfx_target_version;66 uint32_t vendor_id;67 uint32_t device_id;68 uint32_t location_id;69 uint32_t domain;70 uint32_t max_engine_clk_fcompute;71 uint32_t max_engine_clk_ccompute;72 int32_t drm_render_minor;73 uint32_t num_sdma_engines;74 uint32_t num_sdma_xgmi_engines;75 uint32_t num_sdma_queues_per_engine;76 uint32_t num_cp_queues;77 uint32_t cwsr_size;78 uint32_t ctl_stack_size;79 uint32_t eop_buffer_size;80 uint32_t debug_memory_size;81 char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];82};83 84struct kfd_mem_properties {85 struct list_head list;86 uint32_t heap_type;87 uint64_t size_in_bytes;88 uint32_t flags;89 uint32_t width;90 uint32_t mem_clk_max;91 struct kfd_node *gpu;92 struct kobject *kobj;93 struct attribute attr;94};95 96#define CACHE_SIBLINGMAP_SIZE 12897 98struct kfd_cache_properties {99 struct list_head list;100 uint32_t processor_id_low;101 uint32_t cache_level;102 uint32_t cache_size;103 uint32_t cacheline_size;104 uint32_t cachelines_per_tag;105 uint32_t cache_assoc;106 uint32_t cache_latency;107 uint32_t cache_type;108 uint8_t sibling_map[CACHE_SIBLINGMAP_SIZE];109 struct kfd_node *gpu;110 struct kobject *kobj;111 struct attribute attr;112 uint32_t sibling_map_size;113};114 115struct kfd_iolink_properties {116 struct list_head list;117 uint32_t iolink_type;118 uint32_t ver_maj;119 uint32_t ver_min;120 uint32_t node_from;121 uint32_t node_to;122 uint32_t weight;123 uint32_t min_latency;124 uint32_t max_latency;125 uint32_t min_bandwidth;126 uint32_t max_bandwidth;127 uint32_t rec_transfer_size;128 uint32_t rec_sdma_eng_id_mask;129 uint32_t flags;130 struct kfd_node *gpu;131 struct kobject *kobj;132 struct attribute attr;133};134 135struct kfd_perf_properties {136 struct list_head list;137 char block_name[16];138 uint32_t max_concurrent;139 struct attribute_group *attr_group;140};141 142struct kfd_topology_device {143 struct list_head list;144 uint32_t gpu_id;145 uint32_t proximity_domain;146 struct kfd_node_properties node_props;147 struct list_head mem_props;148 struct list_head cache_props;149 struct list_head io_link_props;150 struct list_head p2p_link_props;151 struct list_head perf_props;152 struct kfd_node *gpu;153 struct kobject *kobj_node;154 struct kobject *kobj_mem;155 struct kobject *kobj_cache;156 struct kobject *kobj_iolink;157 struct kobject *kobj_p2plink;158 struct kobject *kobj_perf;159 struct attribute attr_gpuid;160 struct attribute attr_name;161 struct attribute attr_props;162 union {163 uint8_t oem_id[CRAT_OEMID_LENGTH];164 uint64_t oem_id64;165 };166 uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];167 uint32_t oem_revision;168};169 170struct kfd_system_properties {171 uint32_t num_devices; /* Number of H-NUMA nodes */172 uint32_t generation_count;173 uint64_t platform_oem;174 uint64_t platform_id;175 uint64_t platform_rev;176 struct kobject *kobj_topology;177 struct kobject *kobj_nodes;178 struct attribute attr_genid;179 struct attribute attr_props;180};181 182struct kfd_topology_device *kfd_create_topology_device(183 struct list_head *device_list);184void kfd_release_topology_device_list(struct list_head *device_list);185 186#endif /* __KFD_TOPOLOGY_H__ */187