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1/*2 * Copyright 2015 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26/* The caprices of the preprocessor require that this be declared right here */27#define CREATE_TRACE_POINTS28 29#include "dm_services_types.h"30#include "dc.h"31#include "link_enc_cfg.h"32#include "dc/inc/core_types.h"33#include "dal_asic_id.h"34#include "dmub/dmub_srv.h"35#include "dc/inc/hw/dmcu.h"36#include "dc/inc/hw/abm.h"37#include "dc/dc_dmub_srv.h"38#include "dc/dc_edid_parser.h"39#include "dc/dc_stat.h"40#include "dc/dc_state.h"41#include "amdgpu_dm_trace.h"42#include "dpcd_defs.h"43#include "link/protocols/link_dpcd.h"44#include "link_service_types.h"45#include "link/protocols/link_dp_capability.h"46#include "link/protocols/link_ddc.h"47 48#include "vid.h"49#include "amdgpu.h"50#include "amdgpu_display.h"51#include "amdgpu_ucode.h"52#include "atom.h"53#include "amdgpu_dm.h"54#include "amdgpu_dm_plane.h"55#include "amdgpu_dm_crtc.h"56#include "amdgpu_dm_hdcp.h"57#include <drm/display/drm_hdcp_helper.h>58#include "amdgpu_dm_wb.h"59#include "amdgpu_pm.h"60#include "amdgpu_atombios.h"61 62#include "amd_shared.h"63#include "amdgpu_dm_irq.h"64#include "dm_helpers.h"65#include "amdgpu_dm_mst_types.h"66#if defined(CONFIG_DEBUG_FS)67#include "amdgpu_dm_debugfs.h"68#endif69#include "amdgpu_dm_psr.h"70#include "amdgpu_dm_replay.h"71 72#include "ivsrcid/ivsrcid_vislands30.h"73 74#include <linux/backlight.h>75#include <linux/module.h>76#include <linux/moduleparam.h>77#include <linux/types.h>78#include <linux/pm_runtime.h>79#include <linux/pci.h>80#include <linux/power_supply.h>81#include <linux/firmware.h>82#include <linux/component.h>83#include <linux/dmi.h>84#include <linux/sort.h>85 86#include <drm/display/drm_dp_mst_helper.h>87#include <drm/display/drm_hdmi_helper.h>88#include <drm/drm_atomic.h>89#include <drm/drm_atomic_uapi.h>90#include <drm/drm_atomic_helper.h>91#include <drm/drm_blend.h>92#include <drm/drm_fixed.h>93#include <drm/drm_fourcc.h>94#include <drm/drm_edid.h>95#include <drm/drm_eld.h>96#include <drm/drm_vblank.h>97#include <drm/drm_audio_component.h>98#include <drm/drm_gem_atomic_helper.h>99 100#include <acpi/video.h>101 102#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"103 104#include "dcn/dcn_1_0_offset.h"105#include "dcn/dcn_1_0_sh_mask.h"106#include "soc15_hw_ip.h"107#include "soc15_common.h"108#include "vega10_ip_offset.h"109 110#include "gc/gc_11_0_0_offset.h"111#include "gc/gc_11_0_0_sh_mask.h"112 113#include "modules/inc/mod_freesync.h"114#include "modules/power/power_helpers.h"115 116#define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"117MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);118#define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"119MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);120#define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"121MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);122#define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"123MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);124#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"125MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);126#define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"127MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);128#define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"129MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);130#define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"131MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);132#define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"133MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);134#define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"135MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);136#define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"137MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);138 139#define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"140MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);141#define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"142MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);143 144#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"145MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);146 147#define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"148MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);149 150#define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"151MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);152 153#define FIRMWARE_DCN_351_DMUB "amdgpu/dcn_3_5_1_dmcub.bin"154MODULE_FIRMWARE(FIRMWARE_DCN_351_DMUB);155 156#define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin"157MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB);158 159/* Number of bytes in PSP header for firmware. */160#define PSP_HEADER_BYTES 0x100161 162/* Number of bytes in PSP footer for firmware. */163#define PSP_FOOTER_BYTES 0x100164 165/**166 * DOC: overview167 *168 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,169 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM170 * requests into DC requests, and DC responses into DRM responses.171 *172 * The root control structure is &struct amdgpu_display_manager.173 */174 175/* basic init/fini API */176static int amdgpu_dm_init(struct amdgpu_device *adev);177static void amdgpu_dm_fini(struct amdgpu_device *adev);178static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);179static void reset_freesync_config_for_crtc(struct dm_crtc_state *new_crtc_state);180 181static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)182{183 switch (link->dpcd_caps.dongle_type) {184 case DISPLAY_DONGLE_NONE:185 return DRM_MODE_SUBCONNECTOR_Native;186 case DISPLAY_DONGLE_DP_VGA_CONVERTER:187 return DRM_MODE_SUBCONNECTOR_VGA;188 case DISPLAY_DONGLE_DP_DVI_CONVERTER:189 case DISPLAY_DONGLE_DP_DVI_DONGLE:190 return DRM_MODE_SUBCONNECTOR_DVID;191 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:192 case DISPLAY_DONGLE_DP_HDMI_DONGLE:193 return DRM_MODE_SUBCONNECTOR_HDMIA;194 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:195 default:196 return DRM_MODE_SUBCONNECTOR_Unknown;197 }198}199 200static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)201{202 struct dc_link *link = aconnector->dc_link;203 struct drm_connector *connector = &aconnector->base;204 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;205 206 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)207 return;208 209 if (aconnector->dc_sink)210 subconnector = get_subconnector_type(link);211 212 drm_object_property_set_value(&connector->base,213 connector->dev->mode_config.dp_subconnector_property,214 subconnector);215}216 217/*218 * initializes drm_device display related structures, based on the information219 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,220 * drm_encoder, drm_mode_config221 *222 * Returns 0 on success223 */224static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);225/* removes and deallocates the drm structures, created by the above function */226static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);227 228static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,229 struct amdgpu_dm_connector *amdgpu_dm_connector,230 u32 link_index,231 struct amdgpu_encoder *amdgpu_encoder);232static int amdgpu_dm_encoder_init(struct drm_device *dev,233 struct amdgpu_encoder *aencoder,234 uint32_t link_index);235 236static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);237 238static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);239 240static int amdgpu_dm_atomic_check(struct drm_device *dev,241 struct drm_atomic_state *state);242 243static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);244static void handle_hpd_rx_irq(void *param);245 246static bool247is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,248 struct drm_crtc_state *new_crtc_state);249/*250 * dm_vblank_get_counter251 *252 * @brief253 * Get counter for number of vertical blanks254 *255 * @param256 * struct amdgpu_device *adev - [in] desired amdgpu device257 * int disp_idx - [in] which CRTC to get the counter from258 *259 * @return260 * Counter for vertical blanks261 */262static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)263{264 struct amdgpu_crtc *acrtc = NULL;265 266 if (crtc >= adev->mode_info.num_crtc)267 return 0;268 269 acrtc = adev->mode_info.crtcs[crtc];270 271 if (!acrtc->dm_irq_params.stream) {272 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",273 crtc);274 return 0;275 }276 277 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);278}279 280static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,281 u32 *vbl, u32 *position)282{283 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0;284 struct amdgpu_crtc *acrtc = NULL;285 struct dc *dc = adev->dm.dc;286 287 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))288 return -EINVAL;289 290 acrtc = adev->mode_info.crtcs[crtc];291 292 if (!acrtc->dm_irq_params.stream) {293 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",294 crtc);295 return 0;296 }297 298 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)299 dc_allow_idle_optimizations(dc, false);300 301 /*302 * TODO rework base driver to use values directly.303 * for now parse it back into reg-format304 */305 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,306 &v_blank_start,307 &v_blank_end,308 &h_position,309 &v_position);310 311 *position = v_position | (h_position << 16);312 *vbl = v_blank_start | (v_blank_end << 16);313 314 return 0;315}316 317static bool dm_is_idle(void *handle)318{319 /* XXX todo */320 return true;321}322 323static int dm_wait_for_idle(void *handle)324{325 /* XXX todo */326 return 0;327}328 329static bool dm_check_soft_reset(void *handle)330{331 return false;332}333 334static int dm_soft_reset(void *handle)335{336 /* XXX todo */337 return 0;338}339 340static struct amdgpu_crtc *341get_crtc_by_otg_inst(struct amdgpu_device *adev,342 int otg_inst)343{344 struct drm_device *dev = adev_to_drm(adev);345 struct drm_crtc *crtc;346 struct amdgpu_crtc *amdgpu_crtc;347 348 if (WARN_ON(otg_inst == -1))349 return adev->mode_info.crtcs[0];350 351 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {352 amdgpu_crtc = to_amdgpu_crtc(crtc);353 354 if (amdgpu_crtc->otg_inst == otg_inst)355 return amdgpu_crtc;356 }357 358 return NULL;359}360 361static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,362 struct dm_crtc_state *new_state)363{364 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)365 return true;366 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))367 return true;368 else369 return false;370}371 372/*373 * DC will program planes with their z-order determined by their ordering374 * in the dc_surface_updates array. This comparator is used to sort them375 * by descending zpos.376 */377static int dm_plane_layer_index_cmp(const void *a, const void *b)378{379 const struct dc_surface_update *sa = (struct dc_surface_update *)a;380 const struct dc_surface_update *sb = (struct dc_surface_update *)b;381 382 /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */383 return sb->surface->layer_index - sa->surface->layer_index;384}385 386/**387 * update_planes_and_stream_adapter() - Send planes to be updated in DC388 *389 * DC has a generic way to update planes and stream via390 * dc_update_planes_and_stream function; however, DM might need some391 * adjustments and preparation before calling it. This function is a wrapper392 * for the dc_update_planes_and_stream that does any required configuration393 * before passing control to DC.394 *395 * @dc: Display Core control structure396 * @update_type: specify whether it is FULL/MEDIUM/FAST update397 * @planes_count: planes count to update398 * @stream: stream state399 * @stream_update: stream update400 * @array_of_surface_update: dc surface update pointer401 *402 */403static inline bool update_planes_and_stream_adapter(struct dc *dc,404 int update_type,405 int planes_count,406 struct dc_stream_state *stream,407 struct dc_stream_update *stream_update,408 struct dc_surface_update *array_of_surface_update)409{410 sort(array_of_surface_update, planes_count,411 sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL);412 413 /*414 * Previous frame finished and HW is ready for optimization.415 */416 if (update_type == UPDATE_TYPE_FAST)417 dc_post_update_surfaces_to_stream(dc);418 419 return dc_update_planes_and_stream(dc,420 array_of_surface_update,421 planes_count,422 stream,423 stream_update);424}425 426/**427 * dm_pflip_high_irq() - Handle pageflip interrupt428 * @interrupt_params: ignored429 *430 * Handles the pageflip interrupt by notifying all interested parties431 * that the pageflip has been completed.432 */433static void dm_pflip_high_irq(void *interrupt_params)434{435 struct amdgpu_crtc *amdgpu_crtc;436 struct common_irq_params *irq_params = interrupt_params;437 struct amdgpu_device *adev = irq_params->adev;438 struct drm_device *dev = adev_to_drm(adev);439 unsigned long flags;440 struct drm_pending_vblank_event *e;441 u32 vpos, hpos, v_blank_start, v_blank_end;442 bool vrr_active;443 444 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);445 446 /* IRQ could occur when in initial stage */447 /* TODO work and BO cleanup */448 if (amdgpu_crtc == NULL) {449 drm_dbg_state(dev, "CRTC is null, returning.\n");450 return;451 }452 453 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);454 455 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {456 drm_dbg_state(dev,457 "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",458 amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,459 amdgpu_crtc->crtc_id, amdgpu_crtc);460 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);461 return;462 }463 464 /* page flip completed. */465 e = amdgpu_crtc->event;466 amdgpu_crtc->event = NULL;467 468 WARN_ON(!e);469 470 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);471 472 /* Fixed refresh rate, or VRR scanout position outside front-porch? */473 if (!vrr_active ||474 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,475 &v_blank_end, &hpos, &vpos) ||476 (vpos < v_blank_start)) {477 /* Update to correct count and vblank timestamp if racing with478 * vblank irq. This also updates to the correct vblank timestamp479 * even in VRR mode, as scanout is past the front-porch atm.480 */481 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);482 483 /* Wake up userspace by sending the pageflip event with proper484 * count and timestamp of vblank of flip completion.485 */486 if (e) {487 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);488 489 /* Event sent, so done with vblank for this flip */490 drm_crtc_vblank_put(&amdgpu_crtc->base);491 }492 } else if (e) {493 /* VRR active and inside front-porch: vblank count and494 * timestamp for pageflip event will only be up to date after495 * drm_crtc_handle_vblank() has been executed from late vblank496 * irq handler after start of back-porch (vline 0). We queue the497 * pageflip event for send-out by drm_crtc_handle_vblank() with498 * updated timestamp and count, once it runs after us.499 *500 * We need to open-code this instead of using the helper501 * drm_crtc_arm_vblank_event(), as that helper would502 * call drm_crtc_accurate_vblank_count(), which we must503 * not call in VRR mode while we are in front-porch!504 */505 506 /* sequence will be replaced by real count during send-out. */507 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);508 e->pipe = amdgpu_crtc->crtc_id;509 510 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);511 e = NULL;512 }513 514 /* Keep track of vblank of this flip for flip throttling. We use the515 * cooked hw counter, as that one incremented at start of this vblank516 * of pageflip completion, so last_flip_vblank is the forbidden count517 * for queueing new pageflips if vsync + VRR is enabled.518 */519 amdgpu_crtc->dm_irq_params.last_flip_vblank =520 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);521 522 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;523 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);524 525 drm_dbg_state(dev,526 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",527 amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);528}529 530static void dm_vupdate_high_irq(void *interrupt_params)531{532 struct common_irq_params *irq_params = interrupt_params;533 struct amdgpu_device *adev = irq_params->adev;534 struct amdgpu_crtc *acrtc;535 struct drm_device *drm_dev;536 struct drm_vblank_crtc *vblank;537 ktime_t frame_duration_ns, previous_timestamp;538 unsigned long flags;539 int vrr_active;540 541 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);542 543 if (acrtc) {544 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);545 drm_dev = acrtc->base.dev;546 vblank = drm_crtc_vblank_crtc(&acrtc->base);547 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);548 frame_duration_ns = vblank->time - previous_timestamp;549 550 if (frame_duration_ns > 0) {551 trace_amdgpu_refresh_rate_track(acrtc->base.index,552 frame_duration_ns,553 ktime_divns(NSEC_PER_SEC, frame_duration_ns));554 atomic64_set(&irq_params->previous_timestamp, vblank->time);555 }556 557 drm_dbg_vbl(drm_dev,558 "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,559 vrr_active);560 561 /* Core vblank handling is done here after end of front-porch in562 * vrr mode, as vblank timestamping will give valid results563 * while now done after front-porch. This will also deliver564 * page-flip completion events that have been queued to us565 * if a pageflip happened inside front-porch.566 */567 if (vrr_active) {568 amdgpu_dm_crtc_handle_vblank(acrtc);569 570 /* BTR processing for pre-DCE12 ASICs */571 if (acrtc->dm_irq_params.stream &&572 adev->family < AMDGPU_FAMILY_AI) {573 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);574 mod_freesync_handle_v_update(575 adev->dm.freesync_module,576 acrtc->dm_irq_params.stream,577 &acrtc->dm_irq_params.vrr_params);578 579 dc_stream_adjust_vmin_vmax(580 adev->dm.dc,581 acrtc->dm_irq_params.stream,582 &acrtc->dm_irq_params.vrr_params.adjust);583 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);584 }585 }586 }587}588 589/**590 * dm_crtc_high_irq() - Handles CRTC interrupt591 * @interrupt_params: used for determining the CRTC instance592 *593 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK594 * event handler.595 */596static void dm_crtc_high_irq(void *interrupt_params)597{598 struct common_irq_params *irq_params = interrupt_params;599 struct amdgpu_device *adev = irq_params->adev;600 struct drm_writeback_job *job;601 struct amdgpu_crtc *acrtc;602 unsigned long flags;603 int vrr_active;604 605 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);606 if (!acrtc)607 return;608 609 if (acrtc->wb_conn) {610 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags);611 612 if (acrtc->wb_pending) {613 job = list_first_entry_or_null(&acrtc->wb_conn->job_queue,614 struct drm_writeback_job,615 list_entry);616 acrtc->wb_pending = false;617 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags);618 619 if (job) {620 unsigned int v_total, refresh_hz;621 struct dc_stream_state *stream = acrtc->dm_irq_params.stream;622 623 v_total = stream->adjust.v_total_max ?624 stream->adjust.v_total_max : stream->timing.v_total;625 refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz *626 100LL, (v_total * stream->timing.h_total));627 mdelay(1000 / refresh_hz);628 629 drm_writeback_signal_completion(acrtc->wb_conn, 0);630 dc_stream_fc_disable_writeback(adev->dm.dc,631 acrtc->dm_irq_params.stream, 0);632 }633 } else634 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags);635 }636 637 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);638 639 drm_dbg_vbl(adev_to_drm(adev),640 "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,641 vrr_active, acrtc->dm_irq_params.active_planes);642 643 /**644 * Core vblank handling at start of front-porch is only possible645 * in non-vrr mode, as only there vblank timestamping will give646 * valid results while done in front-porch. Otherwise defer it647 * to dm_vupdate_high_irq after end of front-porch.648 */649 if (!vrr_active)650 amdgpu_dm_crtc_handle_vblank(acrtc);651 652 /**653 * Following stuff must happen at start of vblank, for crc654 * computation and below-the-range btr support in vrr mode.655 */656 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);657 658 /* BTR updates need to happen before VUPDATE on Vega and above. */659 if (adev->family < AMDGPU_FAMILY_AI)660 return;661 662 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);663 664 if (acrtc->dm_irq_params.stream &&665 acrtc->dm_irq_params.vrr_params.supported &&666 acrtc->dm_irq_params.freesync_config.state ==667 VRR_STATE_ACTIVE_VARIABLE) {668 mod_freesync_handle_v_update(adev->dm.freesync_module,669 acrtc->dm_irq_params.stream,670 &acrtc->dm_irq_params.vrr_params);671 672 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,673 &acrtc->dm_irq_params.vrr_params.adjust);674 }675 676 /*677 * If there aren't any active_planes then DCH HUBP may be clock-gated.678 * In that case, pageflip completion interrupts won't fire and pageflip679 * completion events won't get delivered. Prevent this by sending680 * pending pageflip events from here if a flip is still pending.681 *682 * If any planes are enabled, use dm_pflip_high_irq() instead, to683 * avoid race conditions between flip programming and completion,684 * which could cause too early flip completion events.685 */686 if (adev->family >= AMDGPU_FAMILY_RV &&687 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&688 acrtc->dm_irq_params.active_planes == 0) {689 if (acrtc->event) {690 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);691 acrtc->event = NULL;692 drm_crtc_vblank_put(&acrtc->base);693 }694 acrtc->pflip_status = AMDGPU_FLIP_NONE;695 }696 697 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);698}699 700#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)701/**702 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for703 * DCN generation ASICs704 * @interrupt_params: interrupt parameters705 *706 * Used to set crc window/read out crc value at vertical line 0 position707 */708static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)709{710 struct common_irq_params *irq_params = interrupt_params;711 struct amdgpu_device *adev = irq_params->adev;712 struct amdgpu_crtc *acrtc;713 714 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);715 716 if (!acrtc)717 return;718 719 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);720}721#endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */722 723/**724 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.725 * @adev: amdgpu_device pointer726 * @notify: dmub notification structure727 *728 * Dmub AUX or SET_CONFIG command completion processing callback729 * Copies dmub notification to DM which is to be read by AUX command.730 * issuing thread and also signals the event to wake up the thread.731 */732static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,733 struct dmub_notification *notify)734{735 if (adev->dm.dmub_notify)736 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));737 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)738 complete(&adev->dm.dmub_aux_transfer_done);739}740 741/**742 * dmub_hpd_callback - DMUB HPD interrupt processing callback.743 * @adev: amdgpu_device pointer744 * @notify: dmub notification structure745 *746 * Dmub Hpd interrupt processing callback. Gets displayindex through the747 * ink index and calls helper to do the processing.748 */749static void dmub_hpd_callback(struct amdgpu_device *adev,750 struct dmub_notification *notify)751{752 struct amdgpu_dm_connector *aconnector;753 struct amdgpu_dm_connector *hpd_aconnector = NULL;754 struct drm_connector *connector;755 struct drm_connector_list_iter iter;756 struct dc_link *link;757 u8 link_index = 0;758 struct drm_device *dev;759 760 if (adev == NULL)761 return;762 763 if (notify == NULL) {764 DRM_ERROR("DMUB HPD callback notification was NULL");765 return;766 }767 768 if (notify->link_index > adev->dm.dc->link_count) {769 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);770 return;771 }772 773 /* Skip DMUB HPD IRQ in suspend/resume. We will probe them later. */774 if (notify->type == DMUB_NOTIFICATION_HPD && adev->in_suspend) {775 DRM_INFO("Skip DMUB HPD IRQ callback in suspend/resume\n");776 return;777 }778 779 link_index = notify->link_index;780 link = adev->dm.dc->links[link_index];781 dev = adev->dm.ddev;782 783 drm_connector_list_iter_begin(dev, &iter);784 drm_for_each_connector_iter(connector, &iter) {785 786 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)787 continue;788 789 aconnector = to_amdgpu_dm_connector(connector);790 if (link && aconnector->dc_link == link) {791 if (notify->type == DMUB_NOTIFICATION_HPD)792 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);793 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)794 DRM_INFO("DMUB HPD RX IRQ callback: link_index=%u\n", link_index);795 else796 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",797 notify->type, link_index);798 799 hpd_aconnector = aconnector;800 break;801 }802 }803 drm_connector_list_iter_end(&iter);804 805 if (hpd_aconnector) {806 if (notify->type == DMUB_NOTIFICATION_HPD) {807 if (hpd_aconnector->dc_link->hpd_status == (notify->hpd_status == DP_HPD_PLUG))808 DRM_WARN("DMUB reported hpd status unchanged. link_index=%u\n", link_index);809 handle_hpd_irq_helper(hpd_aconnector);810 } else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) {811 handle_hpd_rx_irq(hpd_aconnector);812 }813 }814}815 816/**817 * dmub_hpd_sense_callback - DMUB HPD sense processing callback.818 * @adev: amdgpu_device pointer819 * @notify: dmub notification structure820 *821 * HPD sense changes can occur during low power states and need to be822 * notified from firmware to driver.823 */824static void dmub_hpd_sense_callback(struct amdgpu_device *adev,825 struct dmub_notification *notify)826{827 DRM_DEBUG_DRIVER("DMUB HPD SENSE callback.\n");828}829 830/**831 * register_dmub_notify_callback - Sets callback for DMUB notify832 * @adev: amdgpu_device pointer833 * @type: Type of dmub notification834 * @callback: Dmub interrupt callback function835 * @dmub_int_thread_offload: offload indicator836 *837 * API to register a dmub callback handler for a dmub notification838 * Also sets indicator whether callback processing to be offloaded.839 * to dmub interrupt handling thread840 * Return: true if successfully registered, false if there is existing registration841 */842static bool register_dmub_notify_callback(struct amdgpu_device *adev,843 enum dmub_notification_type type,844 dmub_notify_interrupt_callback_t callback,845 bool dmub_int_thread_offload)846{847 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {848 adev->dm.dmub_callback[type] = callback;849 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;850 } else851 return false;852 853 return true;854}855 856static void dm_handle_hpd_work(struct work_struct *work)857{858 struct dmub_hpd_work *dmub_hpd_wrk;859 860 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);861 862 if (!dmub_hpd_wrk->dmub_notify) {863 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");864 return;865 }866 867 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {868 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,869 dmub_hpd_wrk->dmub_notify);870 }871 872 kfree(dmub_hpd_wrk->dmub_notify);873 kfree(dmub_hpd_wrk);874 875}876 877#define DMUB_TRACE_MAX_READ 64878/**879 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt880 * @interrupt_params: used for determining the Outbox instance881 *882 * Handles the Outbox Interrupt883 * event handler.884 */885static void dm_dmub_outbox1_low_irq(void *interrupt_params)886{887 struct dmub_notification notify = {0};888 struct common_irq_params *irq_params = interrupt_params;889 struct amdgpu_device *adev = irq_params->adev;890 struct amdgpu_display_manager *dm = &adev->dm;891 struct dmcub_trace_buf_entry entry = { 0 };892 u32 count = 0;893 struct dmub_hpd_work *dmub_hpd_wrk;894 static const char *const event_type[] = {895 "NO_DATA",896 "AUX_REPLY",897 "HPD",898 "HPD_IRQ",899 "SET_CONFIGC_REPLY",900 "DPIA_NOTIFICATION",901 "HPD_SENSE_NOTIFY",902 };903 904 do {905 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {906 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,907 entry.param0, entry.param1);908 909 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",910 entry.trace_code, entry.tick_count, entry.param0, entry.param1);911 } else912 break;913 914 count++;915 916 } while (count <= DMUB_TRACE_MAX_READ);917 918 if (count > DMUB_TRACE_MAX_READ)919 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");920 921 if (dc_enable_dmub_notifications(adev->dm.dc) &&922 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {923 924 do {925 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify);926 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {927 DRM_ERROR("DM: notify type %d invalid!", notify.type);928 continue;929 }930 if (!dm->dmub_callback[notify.type]) {931 DRM_WARN("DMUB notification skipped due to no handler: type=%s\n",932 event_type[notify.type]);933 continue;934 }935 if (dm->dmub_thread_offload[notify.type] == true) {936 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);937 if (!dmub_hpd_wrk) {938 DRM_ERROR("Failed to allocate dmub_hpd_wrk");939 return;940 }941 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification),942 GFP_ATOMIC);943 if (!dmub_hpd_wrk->dmub_notify) {944 kfree(dmub_hpd_wrk);945 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");946 return;947 }948 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);949 dmub_hpd_wrk->adev = adev;950 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);951 } else {952 dm->dmub_callback[notify.type](adev, ¬ify);953 }954 } while (notify.pending_notification);955 }956}957 958static int dm_set_clockgating_state(void *handle,959 enum amd_clockgating_state state)960{961 return 0;962}963 964static int dm_set_powergating_state(void *handle,965 enum amd_powergating_state state)966{967 return 0;968}969 970/* Prototypes of private functions */971static int dm_early_init(void *handle);972 973/* Allocate memory for FBC compressed data */974static void amdgpu_dm_fbc_init(struct drm_connector *connector)975{976 struct amdgpu_device *adev = drm_to_adev(connector->dev);977 struct dm_compressor_info *compressor = &adev->dm.compressor;978 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);979 struct drm_display_mode *mode;980 unsigned long max_size = 0;981 982 if (adev->dm.dc->fbc_compressor == NULL)983 return;984 985 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)986 return;987 988 if (compressor->bo_ptr)989 return;990 991 992 list_for_each_entry(mode, &connector->modes, head) {993 if (max_size < (unsigned long) mode->htotal * mode->vtotal)994 max_size = (unsigned long) mode->htotal * mode->vtotal;995 }996 997 if (max_size) {998 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,999 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,1000 &compressor->gpu_addr, &compressor->cpu_addr);1001 1002 if (r)1003 DRM_ERROR("DM: Failed to initialize FBC\n");1004 else {1005 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;1006 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);1007 }1008 1009 }1010 1011}1012 1013static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,1014 int pipe, bool *enabled,1015 unsigned char *buf, int max_bytes)1016{1017 struct drm_device *dev = dev_get_drvdata(kdev);1018 struct amdgpu_device *adev = drm_to_adev(dev);1019 struct drm_connector *connector;1020 struct drm_connector_list_iter conn_iter;1021 struct amdgpu_dm_connector *aconnector;1022 int ret = 0;1023 1024 *enabled = false;1025 1026 mutex_lock(&adev->dm.audio_lock);1027 1028 drm_connector_list_iter_begin(dev, &conn_iter);1029 drm_for_each_connector_iter(connector, &conn_iter) {1030 1031 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)1032 continue;1033 1034 aconnector = to_amdgpu_dm_connector(connector);1035 if (aconnector->audio_inst != port)1036 continue;1037 1038 *enabled = true;1039 ret = drm_eld_size(connector->eld);1040 memcpy(buf, connector->eld, min(max_bytes, ret));1041 1042 break;1043 }1044 drm_connector_list_iter_end(&conn_iter);1045 1046 mutex_unlock(&adev->dm.audio_lock);1047 1048 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);1049 1050 return ret;1051}1052 1053static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {1054 .get_eld = amdgpu_dm_audio_component_get_eld,1055};1056 1057static int amdgpu_dm_audio_component_bind(struct device *kdev,1058 struct device *hda_kdev, void *data)1059{1060 struct drm_device *dev = dev_get_drvdata(kdev);1061 struct amdgpu_device *adev = drm_to_adev(dev);1062 struct drm_audio_component *acomp = data;1063 1064 acomp->ops = &amdgpu_dm_audio_component_ops;1065 acomp->dev = kdev;1066 adev->dm.audio_component = acomp;1067 1068 return 0;1069}1070 1071static void amdgpu_dm_audio_component_unbind(struct device *kdev,1072 struct device *hda_kdev, void *data)1073{1074 struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev));1075 struct drm_audio_component *acomp = data;1076 1077 acomp->ops = NULL;1078 acomp->dev = NULL;1079 adev->dm.audio_component = NULL;1080}1081 1082static const struct component_ops amdgpu_dm_audio_component_bind_ops = {1083 .bind = amdgpu_dm_audio_component_bind,1084 .unbind = amdgpu_dm_audio_component_unbind,1085};1086 1087static int amdgpu_dm_audio_init(struct amdgpu_device *adev)1088{1089 int i, ret;1090 1091 if (!amdgpu_audio)1092 return 0;1093 1094 adev->mode_info.audio.enabled = true;1095 1096 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;1097 1098 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {1099 adev->mode_info.audio.pin[i].channels = -1;1100 adev->mode_info.audio.pin[i].rate = -1;1101 adev->mode_info.audio.pin[i].bits_per_sample = -1;1102 adev->mode_info.audio.pin[i].status_bits = 0;1103 adev->mode_info.audio.pin[i].category_code = 0;1104 adev->mode_info.audio.pin[i].connected = false;1105 adev->mode_info.audio.pin[i].id =1106 adev->dm.dc->res_pool->audios[i]->inst;1107 adev->mode_info.audio.pin[i].offset = 0;1108 }1109 1110 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);1111 if (ret < 0)1112 return ret;1113 1114 adev->dm.audio_registered = true;1115 1116 return 0;1117}1118 1119static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)1120{1121 if (!amdgpu_audio)1122 return;1123 1124 if (!adev->mode_info.audio.enabled)1125 return;1126 1127 if (adev->dm.audio_registered) {1128 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);1129 adev->dm.audio_registered = false;1130 }1131 1132 /* TODO: Disable audio? */1133 1134 adev->mode_info.audio.enabled = false;1135}1136 1137static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)1138{1139 struct drm_audio_component *acomp = adev->dm.audio_component;1140 1141 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {1142 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);1143 1144 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,1145 pin, -1);1146 }1147}1148 1149static int dm_dmub_hw_init(struct amdgpu_device *adev)1150{1151 const struct dmcub_firmware_header_v1_0 *hdr;1152 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;1153 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;1154 const struct firmware *dmub_fw = adev->dm.dmub_fw;1155 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;1156 struct abm *abm = adev->dm.dc->res_pool->abm;1157 struct dc_context *ctx = adev->dm.dc->ctx;1158 struct dmub_srv_hw_params hw_params;1159 enum dmub_status status;1160 const unsigned char *fw_inst_const, *fw_bss_data;1161 u32 i, fw_inst_const_size, fw_bss_data_size;1162 bool has_hw_support;1163 1164 if (!dmub_srv)1165 /* DMUB isn't supported on the ASIC. */1166 return 0;1167 1168 if (!fb_info) {1169 DRM_ERROR("No framebuffer info for DMUB service.\n");1170 return -EINVAL;1171 }1172 1173 if (!dmub_fw) {1174 /* Firmware required for DMUB support. */1175 DRM_ERROR("No firmware provided for DMUB.\n");1176 return -EINVAL;1177 }1178 1179 /* initialize register offsets for ASICs with runtime initialization available */1180 if (dmub_srv->hw_funcs.init_reg_offsets)1181 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);1182 1183 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);1184 if (status != DMUB_STATUS_OK) {1185 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);1186 return -EINVAL;1187 }1188 1189 if (!has_hw_support) {1190 DRM_INFO("DMUB unsupported on ASIC\n");1191 return 0;1192 }1193 1194 /* Reset DMCUB if it was previously running - before we overwrite its memory. */1195 status = dmub_srv_hw_reset(dmub_srv);1196 if (status != DMUB_STATUS_OK)1197 DRM_WARN("Error resetting DMUB HW: %d\n", status);1198 1199 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;1200 1201 fw_inst_const = dmub_fw->data +1202 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +1203 PSP_HEADER_BYTES;1204 1205 fw_bss_data = dmub_fw->data +1206 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +1207 le32_to_cpu(hdr->inst_const_bytes);1208 1209 /* Copy firmware and bios info into FB memory. */1210 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -1211 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;1212 1213 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);1214 1215 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,1216 * amdgpu_ucode_init_single_fw will load dmub firmware1217 * fw_inst_const part to cw0; otherwise, the firmware back door load1218 * will be done by dm_dmub_hw_init1219 */1220 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {1221 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,1222 fw_inst_const_size);1223 }1224 1225 if (fw_bss_data_size)1226 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,1227 fw_bss_data, fw_bss_data_size);1228 1229 /* Copy firmware bios info into FB memory. */1230 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,1231 adev->bios_size);1232 1233 /* Reset regions that need to be reset. */1234 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,1235 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);1236 1237 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,1238 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);1239 1240 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,1241 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);1242 1243 memset(fb_info->fb[DMUB_WINDOW_SHARED_STATE].cpu_addr, 0,1244 fb_info->fb[DMUB_WINDOW_SHARED_STATE].size);1245 1246 /* Initialize hardware. */1247 memset(&hw_params, 0, sizeof(hw_params));1248 hw_params.fb_base = adev->gmc.fb_start;1249 hw_params.fb_offset = adev->vm_manager.vram_base_offset;1250 1251 /* backdoor load firmware and trigger dmub running */1252 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)1253 hw_params.load_inst_const = true;1254 1255 if (dmcu)1256 hw_params.psp_version = dmcu->psp_version;1257 1258 for (i = 0; i < fb_info->num_fb; ++i)1259 hw_params.fb[i] = &fb_info->fb[i];1260 1261 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {1262 case IP_VERSION(3, 1, 3):1263 case IP_VERSION(3, 1, 4):1264 case IP_VERSION(3, 5, 0):1265 case IP_VERSION(3, 5, 1):1266 case IP_VERSION(4, 0, 1):1267 hw_params.dpia_supported = true;1268 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;1269 break;1270 default:1271 break;1272 }1273 1274 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {1275 case IP_VERSION(3, 5, 0):1276 case IP_VERSION(3, 5, 1):1277 hw_params.ips_sequential_ono = adev->external_rev_id > 0x10;1278 break;1279 default:1280 break;1281 }1282 1283 status = dmub_srv_hw_init(dmub_srv, &hw_params);1284 if (status != DMUB_STATUS_OK) {1285 DRM_ERROR("Error initializing DMUB HW: %d\n", status);1286 return -EINVAL;1287 }1288 1289 /* Wait for firmware load to finish. */1290 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);1291 if (status != DMUB_STATUS_OK)1292 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);1293 1294 /* Init DMCU and ABM if available. */1295 if (dmcu && abm) {1296 dmcu->funcs->dmcu_init(dmcu);1297 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);1298 }1299 1300 if (!adev->dm.dc->ctx->dmub_srv)1301 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);1302 if (!adev->dm.dc->ctx->dmub_srv) {1303 DRM_ERROR("Couldn't allocate DC DMUB server!\n");1304 return -ENOMEM;1305 }1306 1307 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",1308 adev->dm.dmcub_fw_version);1309 1310 return 0;1311}1312 1313static void dm_dmub_hw_resume(struct amdgpu_device *adev)1314{1315 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;1316 enum dmub_status status;1317 bool init;1318 int r;1319 1320 if (!dmub_srv) {1321 /* DMUB isn't supported on the ASIC. */1322 return;1323 }1324 1325 status = dmub_srv_is_hw_init(dmub_srv, &init);1326 if (status != DMUB_STATUS_OK)1327 DRM_WARN("DMUB hardware init check failed: %d\n", status);1328 1329 if (status == DMUB_STATUS_OK && init) {1330 /* Wait for firmware load to finish. */1331 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);1332 if (status != DMUB_STATUS_OK)1333 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);1334 } else {1335 /* Perform the full hardware initialization. */1336 r = dm_dmub_hw_init(adev);1337 if (r)1338 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);1339 }1340}1341 1342static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)1343{1344 u64 pt_base;1345 u32 logical_addr_low;1346 u32 logical_addr_high;1347 u32 agp_base, agp_bot, agp_top;1348 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;1349 1350 memset(pa_config, 0, sizeof(*pa_config));1351 1352 agp_base = 0;1353 agp_bot = adev->gmc.agp_start >> 24;1354 agp_top = adev->gmc.agp_end >> 24;1355 1356 /* AGP aperture is disabled */1357 if (agp_bot > agp_top) {1358 logical_addr_low = adev->gmc.fb_start >> 18;1359 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |1360 AMD_APU_IS_RENOIR |1361 AMD_APU_IS_GREEN_SARDINE))1362 /*1363 * Raven2 has a HW issue that it is unable to use the vram which1364 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the1365 * workaround that increase system aperture high address (add 1)1366 * to get rid of the VM fault and hardware hang.1367 */1368 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;1369 else1370 logical_addr_high = adev->gmc.fb_end >> 18;1371 } else {1372 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;1373 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |1374 AMD_APU_IS_RENOIR |1375 AMD_APU_IS_GREEN_SARDINE))1376 /*1377 * Raven2 has a HW issue that it is unable to use the vram which1378 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the1379 * workaround that increase system aperture high address (add 1)1380 * to get rid of the VM fault and hardware hang.1381 */1382 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);1383 else1384 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;1385 }1386 1387 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);1388 1389 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>1390 AMDGPU_GPU_PAGE_SHIFT);1391 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>1392 AMDGPU_GPU_PAGE_SHIFT);1393 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>1394 AMDGPU_GPU_PAGE_SHIFT);1395 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>1396 AMDGPU_GPU_PAGE_SHIFT);1397 page_table_base.high_part = upper_32_bits(pt_base);1398 page_table_base.low_part = lower_32_bits(pt_base);1399 1400 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;1401 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;1402 1403 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;1404 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;1405 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;1406 1407 pa_config->system_aperture.fb_base = adev->gmc.fb_start;1408 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;1409 pa_config->system_aperture.fb_top = adev->gmc.fb_end;1410 1411 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;1412 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;1413 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;1414 1415 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;1416 1417}1418 1419static void force_connector_state(1420 struct amdgpu_dm_connector *aconnector,1421 enum drm_connector_force force_state)1422{1423 struct drm_connector *connector = &aconnector->base;1424 1425 mutex_lock(&connector->dev->mode_config.mutex);1426 aconnector->base.force = force_state;1427 mutex_unlock(&connector->dev->mode_config.mutex);1428 1429 mutex_lock(&aconnector->hpd_lock);1430 drm_kms_helper_connector_hotplug_event(connector);1431 mutex_unlock(&aconnector->hpd_lock);1432}1433 1434static void dm_handle_hpd_rx_offload_work(struct work_struct *work)1435{1436 struct hpd_rx_irq_offload_work *offload_work;1437 struct amdgpu_dm_connector *aconnector;1438 struct dc_link *dc_link;1439 struct amdgpu_device *adev;1440 enum dc_connection_type new_connection_type = dc_connection_none;1441 unsigned long flags;1442 union test_response test_response;1443 1444 memset(&test_response, 0, sizeof(test_response));1445 1446 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);1447 aconnector = offload_work->offload_wq->aconnector;1448 1449 if (!aconnector) {1450 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");1451 goto skip;1452 }1453 1454 adev = drm_to_adev(aconnector->base.dev);1455 dc_link = aconnector->dc_link;1456 1457 mutex_lock(&aconnector->hpd_lock);1458 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))1459 DRM_ERROR("KMS: Failed to detect connector\n");1460 mutex_unlock(&aconnector->hpd_lock);1461 1462 if (new_connection_type == dc_connection_none)1463 goto skip;1464 1465 if (amdgpu_in_reset(adev))1466 goto skip;1467 1468 if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||1469 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {1470 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);1471 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);1472 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;1473 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);1474 goto skip;1475 }1476 1477 mutex_lock(&adev->dm.dc_lock);1478 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {1479 dc_link_dp_handle_automated_test(dc_link);1480 1481 if (aconnector->timing_changed) {1482 /* force connector disconnect and reconnect */1483 force_connector_state(aconnector, DRM_FORCE_OFF);1484 msleep(100);1485 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);1486 }1487 1488 test_response.bits.ACK = 1;1489 1490 core_link_write_dpcd(1491 dc_link,1492 DP_TEST_RESPONSE,1493 &test_response.raw,1494 sizeof(test_response));1495 } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&1496 dc_link_check_link_loss_status(dc_link, &offload_work->data) &&1497 dc_link_dp_allow_hpd_rx_irq(dc_link)) {1498 /* offload_work->data is from handle_hpd_rx_irq->1499 * schedule_hpd_rx_offload_work.this is defer handle1500 * for hpd short pulse. upon here, link status may be1501 * changed, need get latest link status from dpcd1502 * registers. if link status is good, skip run link1503 * training again.1504 */1505 union hpd_irq_data irq_data;1506 1507 memset(&irq_data, 0, sizeof(irq_data));1508 1509 /* before dc_link_dp_handle_link_loss, allow new link lost handle1510 * request be added to work queue if link lost at end of dc_link_1511 * dp_handle_link_loss1512 */1513 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);1514 offload_work->offload_wq->is_handling_link_loss = false;1515 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);1516 1517 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&1518 dc_link_check_link_loss_status(dc_link, &irq_data))1519 dc_link_dp_handle_link_loss(dc_link);1520 }1521 mutex_unlock(&adev->dm.dc_lock);1522 1523skip:1524 kfree(offload_work);1525 1526}1527 1528static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)1529{1530 int max_caps = dc->caps.max_links;1531 int i = 0;1532 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;1533 1534 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);1535 1536 if (!hpd_rx_offload_wq)1537 return NULL;1538 1539 1540 for (i = 0; i < max_caps; i++) {1541 hpd_rx_offload_wq[i].wq =1542 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");1543 1544 if (hpd_rx_offload_wq[i].wq == NULL) {1545 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");1546 goto out_err;1547 }1548 1549 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);1550 }1551 1552 return hpd_rx_offload_wq;1553 1554out_err:1555 for (i = 0; i < max_caps; i++) {1556 if (hpd_rx_offload_wq[i].wq)1557 destroy_workqueue(hpd_rx_offload_wq[i].wq);1558 }1559 kfree(hpd_rx_offload_wq);1560 return NULL;1561}1562 1563struct amdgpu_stutter_quirk {1564 u16 chip_vendor;1565 u16 chip_device;1566 u16 subsys_vendor;1567 u16 subsys_device;1568 u8 revision;1569};1570 1571static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {1572 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */1573 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },1574 { 0, 0, 0, 0, 0 },1575};1576 1577static bool dm_should_disable_stutter(struct pci_dev *pdev)1578{1579 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;1580 1581 while (p && p->chip_device != 0) {1582 if (pdev->vendor == p->chip_vendor &&1583 pdev->device == p->chip_device &&1584 pdev->subsystem_vendor == p->subsys_vendor &&1585 pdev->subsystem_device == p->subsys_device &&1586 pdev->revision == p->revision) {1587 return true;1588 }1589 ++p;1590 }1591 return false;1592}1593 1594static const struct dmi_system_id hpd_disconnect_quirk_table[] = {1595 {1596 .matches = {1597 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),1598 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),1599 },1600 },1601 {1602 .matches = {1603 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),1604 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),1605 },1606 },1607 {1608 .matches = {1609 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),1610 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),1611 },1612 },1613 {1614 .matches = {1615 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),1616 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),1617 },1618 },1619 {1620 .matches = {1621 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),1622 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),1623 },1624 },1625 {1626 .matches = {1627 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),1628 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),1629 },1630 },1631 {1632 .matches = {1633 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),1634 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),1635 },1636 },1637 {1638 .matches = {1639 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),1640 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),1641 },1642 },1643 {1644 .matches = {1645 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),1646 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),1647 },1648 },1649 {}1650 /* TODO: refactor this from a fixed table to a dynamic option */1651};1652 1653static void retrieve_dmi_info(struct amdgpu_display_manager *dm)1654{1655 const struct dmi_system_id *dmi_id;1656 1657 dm->aux_hpd_discon_quirk = false;1658 1659 dmi_id = dmi_first_match(hpd_disconnect_quirk_table);1660 if (dmi_id) {1661 dm->aux_hpd_discon_quirk = true;1662 DRM_INFO("aux_hpd_discon_quirk attached\n");1663 }1664}1665 1666void*1667dm_allocate_gpu_mem(1668 struct amdgpu_device *adev,1669 enum dc_gpu_mem_alloc_type type,1670 size_t size,1671 long long *addr)1672{1673 struct dal_allocation *da;1674 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?1675 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;1676 int ret;1677 1678 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);1679 if (!da)1680 return NULL;1681 1682 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,1683 domain, &da->bo,1684 &da->gpu_addr, &da->cpu_ptr);1685 1686 *addr = da->gpu_addr;1687 1688 if (ret) {1689 kfree(da);1690 return NULL;1691 }1692 1693 /* add da to list in dm */1694 list_add(&da->list, &adev->dm.da_list);1695 1696 return da->cpu_ptr;1697}1698 1699static enum dmub_status1700dm_dmub_send_vbios_gpint_command(struct amdgpu_device *adev,1701 enum dmub_gpint_command command_code,1702 uint16_t param,1703 uint32_t timeout_us)1704{1705 union dmub_gpint_data_register reg, test;1706 uint32_t i;1707 1708 /* Assume that VBIOS DMUB is ready to take commands */1709 1710 reg.bits.status = 1;1711 reg.bits.command_code = command_code;1712 reg.bits.param = param;1713 1714 cgs_write_register(adev->dm.cgs_device, 0x34c0 + 0x01f8, reg.all);1715 1716 for (i = 0; i < timeout_us; ++i) {1717 udelay(1);1718 1719 /* Check if our GPINT got acked */1720 reg.bits.status = 0;1721 test = (union dmub_gpint_data_register)1722 cgs_read_register(adev->dm.cgs_device, 0x34c0 + 0x01f8);1723 1724 if (test.all == reg.all)1725 return DMUB_STATUS_OK;1726 }1727 1728 return DMUB_STATUS_TIMEOUT;1729}1730 1731static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev)1732{1733 struct dml2_soc_bb *bb;1734 long long addr;1735 int i = 0;1736 uint16_t chunk;1737 enum dmub_gpint_command send_addrs[] = {1738 DMUB_GPINT__SET_BB_ADDR_WORD0,1739 DMUB_GPINT__SET_BB_ADDR_WORD1,1740 DMUB_GPINT__SET_BB_ADDR_WORD2,1741 DMUB_GPINT__SET_BB_ADDR_WORD3,1742 };1743 enum dmub_status ret;1744 1745 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {1746 case IP_VERSION(4, 0, 1):1747 break;1748 default:1749 return NULL;1750 }1751 1752 bb = dm_allocate_gpu_mem(adev,1753 DC_MEM_ALLOC_TYPE_GART,1754 sizeof(struct dml2_soc_bb),1755 &addr);1756 if (!bb)1757 return NULL;1758 1759 for (i = 0; i < 4; i++) {1760 /* Extract 16-bit chunk */1761 chunk = ((uint64_t) addr >> (i * 16)) & 0xFFFF;1762 /* Send the chunk */1763 ret = dm_dmub_send_vbios_gpint_command(adev, send_addrs[i], chunk, 30000);1764 if (ret != DMUB_STATUS_OK)1765 /* No need to free bb here since it shall be done in dm_sw_fini() */1766 return NULL;1767 }1768 1769 /* Now ask DMUB to copy the bb */1770 ret = dm_dmub_send_vbios_gpint_command(adev, DMUB_GPINT__BB_COPY, 1, 200000);1771 if (ret != DMUB_STATUS_OK)1772 return NULL;1773 1774 return bb;1775}1776 1777static enum dmub_ips_disable_type dm_get_default_ips_mode(1778 struct amdgpu_device *adev)1779{1780 enum dmub_ips_disable_type ret = DMUB_IPS_ENABLE;1781 1782 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {1783 case IP_VERSION(3, 5, 0):1784 /*1785 * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to1786 * cause a hard hang. A fix exists for newer PMFW.1787 *1788 * As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest1789 * IPS state in all cases, except for s0ix and all displays off (DPMS),1790 * where IPS2 is allowed.1791 *1792 * When checking pmfw version, use the major and minor only.1793 */1794 if ((adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)1795 ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;1796 else if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(11, 5, 0))1797 /*1798 * Other ASICs with DCN35 that have residency issues with1799 * IPS2 in idle.1800 * We want them to use IPS2 only in display off cases.1801 */1802 ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;1803 break;1804 case IP_VERSION(3, 5, 1):1805 ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;1806 break;1807 default:1808 /* ASICs older than DCN35 do not have IPSs */1809 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0))1810 ret = DMUB_IPS_DISABLE_ALL;1811 break;1812 }1813 1814 return ret;1815}1816 1817static int amdgpu_dm_init(struct amdgpu_device *adev)1818{1819 struct dc_init_data init_data;1820 struct dc_callback_init init_params;1821 int r;1822 1823 adev->dm.ddev = adev_to_drm(adev);1824 adev->dm.adev = adev;1825 1826 /* Zero all the fields */1827 memset(&init_data, 0, sizeof(init_data));1828 memset(&init_params, 0, sizeof(init_params));1829 1830 mutex_init(&adev->dm.dpia_aux_lock);1831 mutex_init(&adev->dm.dc_lock);1832 mutex_init(&adev->dm.audio_lock);1833 1834 if (amdgpu_dm_irq_init(adev)) {1835 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");1836 goto error;1837 }1838 1839 init_data.asic_id.chip_family = adev->family;1840 1841 init_data.asic_id.pci_revision_id = adev->pdev->revision;1842 init_data.asic_id.hw_internal_rev = adev->external_rev_id;1843 init_data.asic_id.chip_id = adev->pdev->device;1844 1845 init_data.asic_id.vram_width = adev->gmc.vram_width;1846 /* TODO: initialize init_data.asic_id.vram_type here!!!! */1847 init_data.asic_id.atombios_base_address =1848 adev->mode_info.atom_context->bios;1849 1850 init_data.driver = adev;1851 1852 /* cgs_device was created in dm_sw_init() */1853 init_data.cgs_device = adev->dm.cgs_device;1854 1855 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;1856 1857 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {1858 case IP_VERSION(2, 1, 0):1859 switch (adev->dm.dmcub_fw_version) {1860 case 0: /* development */1861 case 0x1: /* linux-firmware.git hash 6d9f399 */1862 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */1863 init_data.flags.disable_dmcu = false;1864 break;1865 default:1866 init_data.flags.disable_dmcu = true;1867 }1868 break;1869 case IP_VERSION(2, 0, 3):1870 init_data.flags.disable_dmcu = true;1871 break;1872 default:1873 break;1874 }1875 1876 /* APU support S/G display by default except:1877 * ASICs before Carrizo,1878 * RAVEN1 (Users reported stability issue)1879 */1880 1881 if (adev->asic_type < CHIP_CARRIZO) {1882 init_data.flags.gpu_vm_support = false;1883 } else if (adev->asic_type == CHIP_RAVEN) {1884 if (adev->apu_flags & AMD_APU_IS_RAVEN)1885 init_data.flags.gpu_vm_support = false;1886 else1887 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);1888 } else {1889 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);1890 }1891 1892 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;1893 1894 if (amdgpu_dc_feature_mask & DC_FBC_MASK)1895 init_data.flags.fbc_support = true;1896 1897 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)1898 init_data.flags.multi_mon_pp_mclk_switch = true;1899 1900 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)1901 init_data.flags.disable_fractional_pwm = true;1902 1903 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)1904 init_data.flags.edp_no_power_sequencing = true;1905 1906 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)1907 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;1908 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)1909 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;1910 1911 init_data.flags.seamless_boot_edp_requested = false;1912 1913 if (amdgpu_device_seamless_boot_supported(adev)) {1914 init_data.flags.seamless_boot_edp_requested = true;1915 init_data.flags.allow_seamless_boot_optimization = true;1916 DRM_INFO("Seamless boot condition check passed\n");1917 }1918 1919 init_data.flags.enable_mipi_converter_optimization = true;1920 1921 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];1922 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];1923 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];1924 1925 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS)1926 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;1927 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC)1928 init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC;1929 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC)1930 init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;1931 else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE)1932 init_data.flags.disable_ips = DMUB_IPS_ENABLE;1933 else1934 init_data.flags.disable_ips = dm_get_default_ips_mode(adev);1935 1936 init_data.flags.disable_ips_in_vpb = 0;1937 1938 /* Enable DWB for tested platforms only */1939 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0))1940 init_data.num_virtual_links = 1;1941 1942 retrieve_dmi_info(&adev->dm);1943 1944 if (adev->dm.bb_from_dmub)1945 init_data.bb_from_dmub = adev->dm.bb_from_dmub;1946 else1947 init_data.bb_from_dmub = NULL;1948 1949 /* Display Core create. */1950 adev->dm.dc = dc_create(&init_data);1951 1952 if (adev->dm.dc) {1953 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,1954 dce_version_to_string(adev->dm.dc->ctx->dce_version));1955 } else {1956 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);1957 goto error;1958 }1959 1960 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {1961 adev->dm.dc->debug.force_single_disp_pipe_split = false;1962 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;1963 }1964 1965 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)1966 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;1967 if (dm_should_disable_stutter(adev->pdev))1968 adev->dm.dc->debug.disable_stutter = true;1969 1970 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)1971 adev->dm.dc->debug.disable_stutter = true;1972 1973 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)1974 adev->dm.dc->debug.disable_dsc = true;1975 1976 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)1977 adev->dm.dc->debug.disable_clock_gate = true;1978 1979 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)1980 adev->dm.dc->debug.force_subvp_mclk_switch = true;1981 1982 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) {1983 adev->dm.dc->debug.using_dml2 = true;1984 adev->dm.dc->debug.using_dml21 = true;1985 }1986 1987 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;1988 1989 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */1990 adev->dm.dc->debug.ignore_cable_id = true;1991 1992 if (adev->dm.dc->caps.dp_hdmi21_pcon_support)1993 DRM_INFO("DP-HDMI FRL PCON supported\n");1994 1995 r = dm_dmub_hw_init(adev);1996 if (r) {1997 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);1998 goto error;1999 }2000 2001 dc_hardware_init(adev->dm.dc);2002 2003 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);2004 if (!adev->dm.hpd_rx_offload_wq) {2005 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");2006 goto error;2007 }2008 2009 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {2010 struct dc_phy_addr_space_config pa_config;2011 2012 mmhub_read_system_context(adev, &pa_config);2013 2014 // Call the DC init_memory func2015 dc_setup_system_context(adev->dm.dc, &pa_config);2016 }2017 2018 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);2019 if (!adev->dm.freesync_module) {2020 DRM_ERROR(2021 "amdgpu: failed to initialize freesync_module.\n");2022 } else2023 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",2024 adev->dm.freesync_module);2025 2026 amdgpu_dm_init_color_mod();2027 2028 if (adev->dm.dc->caps.max_links > 0) {2029 adev->dm.vblank_control_workqueue =2030 create_singlethread_workqueue("dm_vblank_control_workqueue");2031 if (!adev->dm.vblank_control_workqueue)2032 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");2033 }2034 2035 if (adev->dm.dc->caps.ips_support &&2036 adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL)2037 adev->dm.idle_workqueue = idle_create_workqueue(adev);2038 2039 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {2040 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);2041 2042 if (!adev->dm.hdcp_workqueue)2043 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");2044 else2045 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);2046 2047 dc_init_callbacks(adev->dm.dc, &init_params);2048 }2049 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {2050 init_completion(&adev->dm.dmub_aux_transfer_done);2051 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);2052 if (!adev->dm.dmub_notify) {2053 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");2054 goto error;2055 }2056 2057 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");2058 if (!adev->dm.delayed_hpd_wq) {2059 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");2060 goto error;2061 }2062 2063 amdgpu_dm_outbox_init(adev);2064 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,2065 dmub_aux_setconfig_callback, false)) {2066 DRM_ERROR("amdgpu: fail to register dmub aux callback");2067 goto error;2068 }2069 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.2070 * It is expected that DMUB will resend any pending notifications at this point. Note2071 * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to2072 * align legacy interface initialization sequence. Connection status will be proactivly2073 * detected once in the amdgpu_dm_initialize_drm_device.2074 */2075 dc_enable_dmub_outbox(adev->dm.dc);2076 2077 /* DPIA trace goes to dmesg logs only if outbox is enabled */2078 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)2079 dc_dmub_srv_enable_dpia_trace(adev->dm.dc);2080 }2081 2082 if (amdgpu_dm_initialize_drm_device(adev)) {2083 DRM_ERROR(2084 "amdgpu: failed to initialize sw for display support.\n");2085 goto error;2086 }2087 2088 /* create fake encoders for MST */2089 dm_dp_create_fake_mst_encoders(adev);2090 2091 /* TODO: Add_display_info? */2092 2093 /* TODO use dynamic cursor width */2094 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;2095 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;2096 2097 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {2098 DRM_ERROR(2099 "amdgpu: failed to initialize sw for display support.\n");2100 goto error;2101 }2102 2103#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)2104 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);2105 if (!adev->dm.secure_display_ctxs)2106 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");2107#endif2108 2109 DRM_DEBUG_DRIVER("KMS initialized.\n");2110 2111 return 0;2112error:2113 amdgpu_dm_fini(adev);2114 2115 return -EINVAL;2116}2117 2118static int amdgpu_dm_early_fini(void *handle)2119{2120 struct amdgpu_device *adev = (struct amdgpu_device *)handle;2121 2122 amdgpu_dm_audio_fini(adev);2123 2124 return 0;2125}2126 2127static void amdgpu_dm_fini(struct amdgpu_device *adev)2128{2129 int i;2130 2131 if (adev->dm.vblank_control_workqueue) {2132 destroy_workqueue(adev->dm.vblank_control_workqueue);2133 adev->dm.vblank_control_workqueue = NULL;2134 }2135 2136 if (adev->dm.idle_workqueue) {2137 if (adev->dm.idle_workqueue->running) {2138 adev->dm.idle_workqueue->enable = false;2139 flush_work(&adev->dm.idle_workqueue->work);2140 }2141 2142 kfree(adev->dm.idle_workqueue);2143 adev->dm.idle_workqueue = NULL;2144 }2145 2146 amdgpu_dm_destroy_drm_device(&adev->dm);2147 2148#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)2149 if (adev->dm.secure_display_ctxs) {2150 for (i = 0; i < adev->mode_info.num_crtc; i++) {2151 if (adev->dm.secure_display_ctxs[i].crtc) {2152 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);2153 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);2154 }2155 }2156 kfree(adev->dm.secure_display_ctxs);2157 adev->dm.secure_display_ctxs = NULL;2158 }2159#endif2160 if (adev->dm.hdcp_workqueue) {2161 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);2162 adev->dm.hdcp_workqueue = NULL;2163 }2164 2165 if (adev->dm.dc) {2166 dc_deinit_callbacks(adev->dm.dc);2167 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);2168 if (dc_enable_dmub_notifications(adev->dm.dc)) {2169 kfree(adev->dm.dmub_notify);2170 adev->dm.dmub_notify = NULL;2171 destroy_workqueue(adev->dm.delayed_hpd_wq);2172 adev->dm.delayed_hpd_wq = NULL;2173 }2174 }2175 2176 if (adev->dm.dmub_bo)2177 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,2178 &adev->dm.dmub_bo_gpu_addr,2179 &adev->dm.dmub_bo_cpu_addr);2180 2181 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) {2182 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {2183 if (adev->dm.hpd_rx_offload_wq[i].wq) {2184 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);2185 adev->dm.hpd_rx_offload_wq[i].wq = NULL;2186 }2187 }2188 2189 kfree(adev->dm.hpd_rx_offload_wq);2190 adev->dm.hpd_rx_offload_wq = NULL;2191 }2192 2193 /* DC Destroy TODO: Replace destroy DAL */2194 if (adev->dm.dc)2195 dc_destroy(&adev->dm.dc);2196 /*2197 * TODO: pageflip, vlank interrupt2198 *2199 * amdgpu_dm_irq_fini(adev);2200 */2201 2202 if (adev->dm.cgs_device) {2203 amdgpu_cgs_destroy_device(adev->dm.cgs_device);2204 adev->dm.cgs_device = NULL;2205 }2206 if (adev->dm.freesync_module) {2207 mod_freesync_destroy(adev->dm.freesync_module);2208 adev->dm.freesync_module = NULL;2209 }2210 2211 mutex_destroy(&adev->dm.audio_lock);2212 mutex_destroy(&adev->dm.dc_lock);2213 mutex_destroy(&adev->dm.dpia_aux_lock);2214}2215 2216static int load_dmcu_fw(struct amdgpu_device *adev)2217{2218 const char *fw_name_dmcu = NULL;2219 int r;2220 const struct dmcu_firmware_header_v1_0 *hdr;2221 2222 switch (adev->asic_type) {2223#if defined(CONFIG_DRM_AMD_DC_SI)2224 case CHIP_TAHITI:2225 case CHIP_PITCAIRN:2226 case CHIP_VERDE:2227 case CHIP_OLAND:2228#endif2229 case CHIP_BONAIRE:2230 case CHIP_HAWAII:2231 case CHIP_KAVERI:2232 case CHIP_KABINI:2233 case CHIP_MULLINS:2234 case CHIP_TONGA:2235 case CHIP_FIJI:2236 case CHIP_CARRIZO:2237 case CHIP_STONEY:2238 case CHIP_POLARIS11:2239 case CHIP_POLARIS10:2240 case CHIP_POLARIS12:2241 case CHIP_VEGAM:2242 case CHIP_VEGA10:2243 case CHIP_VEGA12:2244 case CHIP_VEGA20:2245 return 0;2246 case CHIP_NAVI12:2247 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;2248 break;2249 case CHIP_RAVEN:2250 if (ASICREV_IS_PICASSO(adev->external_rev_id))2251 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;2252 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))2253 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;2254 else2255 return 0;2256 break;2257 default:2258 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {2259 case IP_VERSION(2, 0, 2):2260 case IP_VERSION(2, 0, 3):2261 case IP_VERSION(2, 0, 0):2262 case IP_VERSION(2, 1, 0):2263 case IP_VERSION(3, 0, 0):2264 case IP_VERSION(3, 0, 2):2265 case IP_VERSION(3, 0, 3):2266 case IP_VERSION(3, 0, 1):2267 case IP_VERSION(3, 1, 2):2268 case IP_VERSION(3, 1, 3):2269 case IP_VERSION(3, 1, 4):2270 case IP_VERSION(3, 1, 5):2271 case IP_VERSION(3, 1, 6):2272 case IP_VERSION(3, 2, 0):2273 case IP_VERSION(3, 2, 1):2274 case IP_VERSION(3, 5, 0):2275 case IP_VERSION(3, 5, 1):2276 case IP_VERSION(4, 0, 1):2277 return 0;2278 default:2279 break;2280 }2281 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);2282 return -EINVAL;2283 }2284 2285 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {2286 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");2287 return 0;2288 }2289 2290 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, "%s", fw_name_dmcu);2291 if (r == -ENODEV) {2292 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */2293 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");2294 adev->dm.fw_dmcu = NULL;2295 return 0;2296 }2297 if (r) {2298 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",2299 fw_name_dmcu);2300 amdgpu_ucode_release(&adev->dm.fw_dmcu);2301 return r;2302 }2303 2304 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;2305 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;2306 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;2307 adev->firmware.fw_size +=2308 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);2309 2310 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;2311 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;2312 adev->firmware.fw_size +=2313 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);2314 2315 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);2316 2317 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");2318 2319 return 0;2320}2321 2322static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)2323{2324 struct amdgpu_device *adev = ctx;2325 2326 return dm_read_reg(adev->dm.dc->ctx, address);2327}2328 2329static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,2330 uint32_t value)2331{2332 struct amdgpu_device *adev = ctx;2333 2334 return dm_write_reg(adev->dm.dc->ctx, address, value);2335}2336 2337static int dm_dmub_sw_init(struct amdgpu_device *adev)2338{2339 struct dmub_srv_create_params create_params;2340 struct dmub_srv_region_params region_params;2341 struct dmub_srv_region_info region_info;2342 struct dmub_srv_memory_params memory_params;2343 struct dmub_srv_fb_info *fb_info;2344 struct dmub_srv *dmub_srv;2345 const struct dmcub_firmware_header_v1_0 *hdr;2346 enum dmub_asic dmub_asic;2347 enum dmub_status status;2348 static enum dmub_window_memory_type window_memory_type[DMUB_WINDOW_TOTAL] = {2349 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_0_INST_CONST2350 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_1_STACK2351 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_2_BSS_DATA2352 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_3_VBIOS2353 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_4_MAILBOX2354 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_5_TRACEBUFF2355 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_6_FW_STATE2356 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_7_SCRATCH_MEM2357 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_SHARED_STATE2358 };2359 int r;2360 2361 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {2362 case IP_VERSION(2, 1, 0):2363 dmub_asic = DMUB_ASIC_DCN21;2364 break;2365 case IP_VERSION(3, 0, 0):2366 dmub_asic = DMUB_ASIC_DCN30;2367 break;2368 case IP_VERSION(3, 0, 1):2369 dmub_asic = DMUB_ASIC_DCN301;2370 break;2371 case IP_VERSION(3, 0, 2):2372 dmub_asic = DMUB_ASIC_DCN302;2373 break;2374 case IP_VERSION(3, 0, 3):2375 dmub_asic = DMUB_ASIC_DCN303;2376 break;2377 case IP_VERSION(3, 1, 2):2378 case IP_VERSION(3, 1, 3):2379 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;2380 break;2381 case IP_VERSION(3, 1, 4):2382 dmub_asic = DMUB_ASIC_DCN314;2383 break;2384 case IP_VERSION(3, 1, 5):2385 dmub_asic = DMUB_ASIC_DCN315;2386 break;2387 case IP_VERSION(3, 1, 6):2388 dmub_asic = DMUB_ASIC_DCN316;2389 break;2390 case IP_VERSION(3, 2, 0):2391 dmub_asic = DMUB_ASIC_DCN32;2392 break;2393 case IP_VERSION(3, 2, 1):2394 dmub_asic = DMUB_ASIC_DCN321;2395 break;2396 case IP_VERSION(3, 5, 0):2397 case IP_VERSION(3, 5, 1):2398 dmub_asic = DMUB_ASIC_DCN35;2399 break;2400 case IP_VERSION(4, 0, 1):2401 dmub_asic = DMUB_ASIC_DCN401;2402 break;2403 2404 default:2405 /* ASIC doesn't support DMUB. */2406 return 0;2407 }2408 2409 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;2410 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);2411 2412 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {2413 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =2414 AMDGPU_UCODE_ID_DMCUB;2415 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =2416 adev->dm.dmub_fw;2417 adev->firmware.fw_size +=2418 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);2419 2420 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",2421 adev->dm.dmcub_fw_version);2422 }2423 2424 2425 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);2426 dmub_srv = adev->dm.dmub_srv;2427 2428 if (!dmub_srv) {2429 DRM_ERROR("Failed to allocate DMUB service!\n");2430 return -ENOMEM;2431 }2432 2433 memset(&create_params, 0, sizeof(create_params));2434 create_params.user_ctx = adev;2435 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;2436 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;2437 create_params.asic = dmub_asic;2438 2439 /* Create the DMUB service. */2440 status = dmub_srv_create(dmub_srv, &create_params);2441 if (status != DMUB_STATUS_OK) {2442 DRM_ERROR("Error creating DMUB service: %d\n", status);2443 return -EINVAL;2444 }2445 2446 /* Calculate the size of all the regions for the DMUB service. */2447 memset(®ion_params, 0, sizeof(region_params));2448 2449 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -2450 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;2451 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);2452 region_params.vbios_size = adev->bios_size;2453 region_params.fw_bss_data = region_params.bss_data_size ?2454 adev->dm.dmub_fw->data +2455 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +2456 le32_to_cpu(hdr->inst_const_bytes) : NULL;2457 region_params.fw_inst_const =2458 adev->dm.dmub_fw->data +2459 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +2460 PSP_HEADER_BYTES;2461 region_params.window_memory_type = window_memory_type;2462 2463 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,2464 ®ion_info);2465 2466 if (status != DMUB_STATUS_OK) {2467 DRM_ERROR("Error calculating DMUB region info: %d\n", status);2468 return -EINVAL;2469 }2470 2471 /*2472 * Allocate a framebuffer based on the total size of all the regions.2473 * TODO: Move this into GART.2474 */2475 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,2476 AMDGPU_GEM_DOMAIN_VRAM |2477 AMDGPU_GEM_DOMAIN_GTT,2478 &adev->dm.dmub_bo,2479 &adev->dm.dmub_bo_gpu_addr,2480 &adev->dm.dmub_bo_cpu_addr);2481 if (r)2482 return r;2483 2484 /* Rebase the regions on the framebuffer address. */2485 memset(&memory_params, 0, sizeof(memory_params));2486 memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr;2487 memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr;2488 memory_params.region_info = ®ion_info;2489 memory_params.window_memory_type = window_memory_type;2490 2491 adev->dm.dmub_fb_info =2492 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);2493 fb_info = adev->dm.dmub_fb_info;2494 2495 if (!fb_info) {2496 DRM_ERROR(2497 "Failed to allocate framebuffer info for DMUB service!\n");2498 return -ENOMEM;2499 }2500 2501 status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);2502 if (status != DMUB_STATUS_OK) {2503 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);2504 return -EINVAL;2505 }2506 2507 adev->dm.bb_from_dmub = dm_dmub_get_vbios_bounding_box(adev);2508 2509 return 0;2510}2511 2512static int dm_sw_init(void *handle)2513{2514 struct amdgpu_device *adev = (struct amdgpu_device *)handle;2515 int r;2516 2517 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);2518 2519 if (!adev->dm.cgs_device) {2520 DRM_ERROR("amdgpu: failed to create cgs device.\n");2521 return -EINVAL;2522 }2523 2524 /* Moved from dm init since we need to use allocations for storing bounding box data */2525 INIT_LIST_HEAD(&adev->dm.da_list);2526 2527 r = dm_dmub_sw_init(adev);2528 if (r)2529 return r;2530 2531 return load_dmcu_fw(adev);2532}2533 2534static int dm_sw_fini(void *handle)2535{2536 struct amdgpu_device *adev = (struct amdgpu_device *)handle;2537 struct dal_allocation *da;2538 2539 list_for_each_entry(da, &adev->dm.da_list, list) {2540 if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) {2541 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);2542 list_del(&da->list);2543 kfree(da);2544 break;2545 }2546 }2547 2548 adev->dm.bb_from_dmub = NULL;2549 2550 kfree(adev->dm.dmub_fb_info);2551 adev->dm.dmub_fb_info = NULL;2552 2553 if (adev->dm.dmub_srv) {2554 dmub_srv_destroy(adev->dm.dmub_srv);2555 kfree(adev->dm.dmub_srv);2556 adev->dm.dmub_srv = NULL;2557 }2558 2559 amdgpu_ucode_release(&adev->dm.dmub_fw);2560 amdgpu_ucode_release(&adev->dm.fw_dmcu);2561 2562 return 0;2563}2564 2565static int detect_mst_link_for_all_connectors(struct drm_device *dev)2566{2567 struct amdgpu_dm_connector *aconnector;2568 struct drm_connector *connector;2569 struct drm_connector_list_iter iter;2570 int ret = 0;2571 2572 drm_connector_list_iter_begin(dev, &iter);2573 drm_for_each_connector_iter(connector, &iter) {2574 2575 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)2576 continue;2577 2578 aconnector = to_amdgpu_dm_connector(connector);2579 if (aconnector->dc_link->type == dc_connection_mst_branch &&2580 aconnector->mst_mgr.aux) {2581 drm_dbg_kms(dev, "DM_MST: starting TM on aconnector: %p [id: %d]\n",2582 aconnector,2583 aconnector->base.base.id);2584 2585 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);2586 if (ret < 0) {2587 drm_err(dev, "DM_MST: Failed to start MST\n");2588 aconnector->dc_link->type =2589 dc_connection_single;2590 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,2591 aconnector->dc_link);2592 break;2593 }2594 }2595 }2596 drm_connector_list_iter_end(&iter);2597 2598 return ret;2599}2600 2601static int dm_late_init(void *handle)2602{2603 struct amdgpu_device *adev = (struct amdgpu_device *)handle;2604 2605 struct dmcu_iram_parameters params;2606 unsigned int linear_lut[16];2607 int i;2608 struct dmcu *dmcu = NULL;2609 2610 dmcu = adev->dm.dc->res_pool->dmcu;2611 2612 for (i = 0; i < 16; i++)2613 linear_lut[i] = 0xFFFF * i / 15;2614 2615 params.set = 0;2616 params.backlight_ramping_override = false;2617 params.backlight_ramping_start = 0xCCCC;2618 params.backlight_ramping_reduction = 0xCCCCCCCC;2619 params.backlight_lut_array_size = 16;2620 params.backlight_lut_array = linear_lut;2621 2622 /* Min backlight level after ABM reduction, Don't allow below 1%2623 * 0xFFFF x 0.01 = 0x28F2624 */2625 params.min_abm_backlight = 0x28F;2626 /* In the case where abm is implemented on dmcub,2627 * dmcu object will be null.2628 * ABM 2.4 and up are implemented on dmcub.2629 */2630 if (dmcu) {2631 if (!dmcu_load_iram(dmcu, params))2632 return -EINVAL;2633 } else if (adev->dm.dc->ctx->dmub_srv) {2634 struct dc_link *edp_links[MAX_NUM_EDP];2635 int edp_num;2636 2637 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);2638 for (i = 0; i < edp_num; i++) {2639 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))2640 return -EINVAL;2641 }2642 }2643 2644 return detect_mst_link_for_all_connectors(adev_to_drm(adev));2645}2646 2647static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)2648{2649 u8 buf[UUID_SIZE];2650 guid_t guid;2651 int ret;2652 2653 mutex_lock(&mgr->lock);2654 if (!mgr->mst_primary)2655 goto out_fail;2656 2657 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {2658 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");2659 goto out_fail;2660 }2661 2662 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,2663 DP_MST_EN |2664 DP_UP_REQ_EN |2665 DP_UPSTREAM_IS_SRC);2666 if (ret < 0) {2667 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");2668 goto out_fail;2669 }2670 2671 /* Some hubs forget their guids after they resume */2672 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf));2673 if (ret != sizeof(buf)) {2674 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");2675 goto out_fail;2676 }2677 2678 import_guid(&guid, buf);2679 2680 if (guid_is_null(&guid)) {2681 guid_gen(&guid);2682 export_guid(buf, &guid);2683 2684 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf));2685 2686 if (ret != sizeof(buf)) {2687 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");2688 goto out_fail;2689 }2690 }2691 2692 guid_copy(&mgr->mst_primary->guid, &guid);2693 2694out_fail:2695 mutex_unlock(&mgr->lock);2696}2697 2698static void s3_handle_mst(struct drm_device *dev, bool suspend)2699{2700 struct amdgpu_dm_connector *aconnector;2701 struct drm_connector *connector;2702 struct drm_connector_list_iter iter;2703 struct drm_dp_mst_topology_mgr *mgr;2704 2705 drm_connector_list_iter_begin(dev, &iter);2706 drm_for_each_connector_iter(connector, &iter) {2707 2708 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)2709 continue;2710 2711 aconnector = to_amdgpu_dm_connector(connector);2712 if (aconnector->dc_link->type != dc_connection_mst_branch ||2713 aconnector->mst_root)2714 continue;2715 2716 mgr = &aconnector->mst_mgr;2717 2718 if (suspend) {2719 drm_dp_mst_topology_mgr_suspend(mgr);2720 } else {2721 /* if extended timeout is supported in hardware,2722 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer2723 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.2724 */2725 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);2726 if (!dp_is_lttpr_present(aconnector->dc_link))2727 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);2728 2729 /* TODO: move resume_mst_branch_status() into drm mst resume again2730 * once topology probing work is pulled out from mst resume into mst2731 * resume 2nd step. mst resume 2nd step should be called after old2732 * state getting restored (i.e. drm_atomic_helper_resume()).2733 */2734 resume_mst_branch_status(mgr);2735 }2736 }2737 drm_connector_list_iter_end(&iter);2738}2739 2740static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)2741{2742 int ret = 0;2743 2744 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends2745 * on window driver dc implementation.2746 * For Navi1x, clock settings of dcn watermarks are fixed. the settings2747 * should be passed to smu during boot up and resume from s3.2748 * boot up: dc calculate dcn watermark clock settings within dc_create,2749 * dcn20_resource_construct2750 * then call pplib functions below to pass the settings to smu:2751 * smu_set_watermarks_for_clock_ranges2752 * smu_set_watermarks_table2753 * navi10_set_watermarks_table2754 * smu_write_watermarks_table2755 *2756 * For Renoir, clock settings of dcn watermark are also fixed values.2757 * dc has implemented different flow for window driver:2758 * dc_hardware_init / dc_set_power_state2759 * dcn10_init_hw2760 * notify_wm_ranges2761 * set_wm_ranges2762 * -- Linux2763 * smu_set_watermarks_for_clock_ranges2764 * renoir_set_watermarks_table2765 * smu_write_watermarks_table2766 *2767 * For Linux,2768 * dc_hardware_init -> amdgpu_dm_init2769 * dc_set_power_state --> dm_resume2770 *2771 * therefore, this function apply to navi10/12/14 but not Renoir2772 * *2773 */2774 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {2775 case IP_VERSION(2, 0, 2):2776 case IP_VERSION(2, 0, 0):2777 break;2778 default:2779 return 0;2780 }2781 2782 ret = amdgpu_dpm_write_watermarks_table(adev);2783 if (ret) {2784 DRM_ERROR("Failed to update WMTABLE!\n");2785 return ret;2786 }2787 2788 return 0;2789}2790 2791/**2792 * dm_hw_init() - Initialize DC device2793 * @handle: The base driver device containing the amdgpu_dm device.2794 *2795 * Initialize the &struct amdgpu_display_manager device. This involves calling2796 * the initializers of each DM component, then populating the struct with them.2797 *2798 * Although the function implies hardware initialization, both hardware and2799 * software are initialized here. Splitting them out to their relevant init2800 * hooks is a future TODO item.2801 *2802 * Some notable things that are initialized here:2803 *2804 * - Display Core, both software and hardware2805 * - DC modules that we need (freesync and color management)2806 * - DRM software states2807 * - Interrupt sources and handlers2808 * - Vblank support2809 * - Debug FS entries, if enabled2810 */2811static int dm_hw_init(void *handle)2812{2813 struct amdgpu_device *adev = (struct amdgpu_device *)handle;2814 int r;2815 2816 /* Create DAL display manager */2817 r = amdgpu_dm_init(adev);2818 if (r)2819 return r;2820 amdgpu_dm_hpd_init(adev);2821 2822 return 0;2823}2824 2825/**2826 * dm_hw_fini() - Teardown DC device2827 * @handle: The base driver device containing the amdgpu_dm device.2828 *2829 * Teardown components within &struct amdgpu_display_manager that require2830 * cleanup. This involves cleaning up the DRM device, DC, and any modules that2831 * were loaded. Also flush IRQ workqueues and disable them.2832 */2833static int dm_hw_fini(void *handle)2834{2835 struct amdgpu_device *adev = (struct amdgpu_device *)handle;2836 2837 amdgpu_dm_hpd_fini(adev);2838 2839 amdgpu_dm_irq_fini(adev);2840 amdgpu_dm_fini(adev);2841 return 0;2842}2843 2844 2845static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,2846 struct dc_state *state, bool enable)2847{2848 enum dc_irq_source irq_source;2849 struct amdgpu_crtc *acrtc;2850 int rc = -EBUSY;2851 int i = 0;2852 2853 for (i = 0; i < state->stream_count; i++) {2854 acrtc = get_crtc_by_otg_inst(2855 adev, state->stream_status[i].primary_otg_inst);2856 2857 if (acrtc && state->stream_status[i].plane_count != 0) {2858 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;2859 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;2860 if (rc)2861 DRM_WARN("Failed to %s pflip interrupts\n",2862 enable ? "enable" : "disable");2863 2864 if (enable) {2865 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))2866 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);2867 } else2868 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);2869 2870 if (rc)2871 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");2872 2873 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;2874 /* During gpu-reset we disable and then enable vblank irq, so2875 * don't use amdgpu_irq_get/put() to avoid refcount change.2876 */2877 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))2878 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");2879 }2880 }2881 2882}2883 2884static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)2885{2886 struct dc_state *context = NULL;2887 enum dc_status res = DC_ERROR_UNEXPECTED;2888 int i;2889 struct dc_stream_state *del_streams[MAX_PIPES];2890 int del_streams_count = 0;2891 struct dc_commit_streams_params params = {};2892 2893 memset(del_streams, 0, sizeof(del_streams));2894 2895 context = dc_state_create_current_copy(dc);2896 if (context == NULL)2897 goto context_alloc_fail;2898 2899 /* First remove from context all streams */2900 for (i = 0; i < context->stream_count; i++) {2901 struct dc_stream_state *stream = context->streams[i];2902 2903 del_streams[del_streams_count++] = stream;2904 }2905 2906 /* Remove all planes for removed streams and then remove the streams */2907 for (i = 0; i < del_streams_count; i++) {2908 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) {2909 res = DC_FAIL_DETACH_SURFACES;2910 goto fail;2911 }2912 2913 res = dc_state_remove_stream(dc, context, del_streams[i]);2914 if (res != DC_OK)2915 goto fail;2916 }2917 2918 params.streams = context->streams;2919 params.stream_count = context->stream_count;2920 res = dc_commit_streams(dc, ¶ms);2921 2922fail:2923 dc_state_release(context);2924 2925context_alloc_fail:2926 return res;2927}2928 2929static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)2930{2931 int i;2932 2933 if (dm->hpd_rx_offload_wq) {2934 for (i = 0; i < dm->dc->caps.max_links; i++)2935 flush_workqueue(dm->hpd_rx_offload_wq[i].wq);2936 }2937}2938 2939static int dm_suspend(void *handle)2940{2941 struct amdgpu_device *adev = handle;2942 struct amdgpu_display_manager *dm = &adev->dm;2943 int ret = 0;2944 2945 if (amdgpu_in_reset(adev)) {2946 mutex_lock(&dm->dc_lock);2947 2948 dc_allow_idle_optimizations(adev->dm.dc, false);2949 2950 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state);2951 2952 if (dm->cached_dc_state)2953 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);2954 2955 amdgpu_dm_commit_zero_streams(dm->dc);2956 2957 amdgpu_dm_irq_suspend(adev);2958 2959 hpd_rx_irq_work_suspend(dm);2960 2961 return ret;2962 }2963 2964 WARN_ON(adev->dm.cached_state);2965 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));2966 if (IS_ERR(adev->dm.cached_state))2967 return PTR_ERR(adev->dm.cached_state);2968 2969 s3_handle_mst(adev_to_drm(adev), true);2970 2971 amdgpu_dm_irq_suspend(adev);2972 2973 hpd_rx_irq_work_suspend(dm);2974 2975 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);2976 2977 if (dm->dc->caps.ips_support && adev->in_s0ix)2978 dc_allow_idle_optimizations(dm->dc, true);2979 2980 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);2981 2982 return 0;2983}2984 2985struct drm_connector *2986amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,2987 struct drm_crtc *crtc)2988{2989 u32 i;2990 struct drm_connector_state *new_con_state;2991 struct drm_connector *connector;2992 struct drm_crtc *crtc_from_state;2993 2994 for_each_new_connector_in_state(state, connector, new_con_state, i) {2995 crtc_from_state = new_con_state->crtc;2996 2997 if (crtc_from_state == crtc)2998 return connector;2999 }3000 3001 return NULL;3002}3003 3004static void emulated_link_detect(struct dc_link *link)3005{3006 struct dc_sink_init_data sink_init_data = { 0 };3007 struct display_sink_capability sink_caps = { 0 };3008 enum dc_edid_status edid_status;3009 struct dc_context *dc_ctx = link->ctx;3010 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context);3011 struct dc_sink *sink = NULL;3012 struct dc_sink *prev_sink = NULL;3013 3014 link->type = dc_connection_none;3015 prev_sink = link->local_sink;3016 3017 if (prev_sink)3018 dc_sink_release(prev_sink);3019 3020 switch (link->connector_signal) {3021 case SIGNAL_TYPE_HDMI_TYPE_A: {3022 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;3023 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;3024 break;3025 }3026 3027 case SIGNAL_TYPE_DVI_SINGLE_LINK: {3028 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;3029 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;3030 break;3031 }3032 3033 case SIGNAL_TYPE_DVI_DUAL_LINK: {3034 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;3035 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;3036 break;3037 }3038 3039 case SIGNAL_TYPE_LVDS: {3040 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;3041 sink_caps.signal = SIGNAL_TYPE_LVDS;3042 break;3043 }3044 3045 case SIGNAL_TYPE_EDP: {3046 sink_caps.transaction_type =3047 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;3048 sink_caps.signal = SIGNAL_TYPE_EDP;3049 break;3050 }3051 3052 case SIGNAL_TYPE_DISPLAY_PORT: {3053 sink_caps.transaction_type =3054 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;3055 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;3056 break;3057 }3058 3059 default:3060 drm_err(dev, "Invalid connector type! signal:%d\n",3061 link->connector_signal);3062 return;3063 }3064 3065 sink_init_data.link = link;3066 sink_init_data.sink_signal = sink_caps.signal;3067 3068 sink = dc_sink_create(&sink_init_data);3069 if (!sink) {3070 drm_err(dev, "Failed to create sink!\n");3071 return;3072 }3073 3074 /* dc_sink_create returns a new reference */3075 link->local_sink = sink;3076 3077 edid_status = dm_helpers_read_local_edid(3078 link->ctx,3079 link,3080 sink);3081 3082 if (edid_status != EDID_OK)3083 drm_err(dev, "Failed to read EDID\n");3084 3085}3086 3087static void dm_gpureset_commit_state(struct dc_state *dc_state,3088 struct amdgpu_display_manager *dm)3089{3090 struct {3091 struct dc_surface_update surface_updates[MAX_SURFACES];3092 struct dc_plane_info plane_infos[MAX_SURFACES];3093 struct dc_scaling_info scaling_infos[MAX_SURFACES];3094 struct dc_flip_addrs flip_addrs[MAX_SURFACES];3095 struct dc_stream_update stream_update;3096 } *bundle;3097 int k, m;3098 3099 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);3100 3101 if (!bundle) {3102 drm_err(dm->ddev, "Failed to allocate update bundle\n");3103 goto cleanup;3104 }3105 3106 for (k = 0; k < dc_state->stream_count; k++) {3107 bundle->stream_update.stream = dc_state->streams[k];3108 3109 for (m = 0; m < dc_state->stream_status->plane_count; m++) {3110 bundle->surface_updates[m].surface =3111 dc_state->stream_status->plane_states[m];3112 bundle->surface_updates[m].surface->force_full_update =3113 true;3114 }3115 3116 update_planes_and_stream_adapter(dm->dc,3117 UPDATE_TYPE_FULL,3118 dc_state->stream_status->plane_count,3119 dc_state->streams[k],3120 &bundle->stream_update,3121 bundle->surface_updates);3122 }3123 3124cleanup:3125 kfree(bundle);3126}3127 3128static int dm_resume(void *handle)3129{3130 struct amdgpu_device *adev = handle;3131 struct drm_device *ddev = adev_to_drm(adev);3132 struct amdgpu_display_manager *dm = &adev->dm;3133 struct amdgpu_dm_connector *aconnector;3134 struct drm_connector *connector;3135 struct drm_connector_list_iter iter;3136 struct drm_crtc *crtc;3137 struct drm_crtc_state *new_crtc_state;3138 struct dm_crtc_state *dm_new_crtc_state;3139 struct drm_plane *plane;3140 struct drm_plane_state *new_plane_state;3141 struct dm_plane_state *dm_new_plane_state;3142 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);3143 enum dc_connection_type new_connection_type = dc_connection_none;3144 struct dc_state *dc_state;3145 int i, r, j, ret;3146 bool need_hotplug = false;3147 struct dc_commit_streams_params commit_params = {};3148 3149 if (dm->dc->caps.ips_support) {3150 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);3151 }3152 3153 if (amdgpu_in_reset(adev)) {3154 dc_state = dm->cached_dc_state;3155 3156 /*3157 * The dc->current_state is backed up into dm->cached_dc_state3158 * before we commit 0 streams.3159 *3160 * DC will clear link encoder assignments on the real state3161 * but the changes won't propagate over to the copy we made3162 * before the 0 streams commit.3163 *3164 * DC expects that link encoder assignments are *not* valid3165 * when committing a state, so as a workaround we can copy3166 * off of the current state.3167 *3168 * We lose the previous assignments, but we had already3169 * commit 0 streams anyway.3170 */3171 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);3172 3173 r = dm_dmub_hw_init(adev);3174 if (r)3175 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);3176 3177 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);3178 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);3179 3180 dc_resume(dm->dc);3181 3182 amdgpu_dm_irq_resume_early(adev);3183 3184 for (i = 0; i < dc_state->stream_count; i++) {3185 dc_state->streams[i]->mode_changed = true;3186 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {3187 dc_state->stream_status[i].plane_states[j]->update_flags.raw3188 = 0xffffffff;3189 }3190 }3191 3192 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {3193 amdgpu_dm_outbox_init(adev);3194 dc_enable_dmub_outbox(adev->dm.dc);3195 }3196 3197 commit_params.streams = dc_state->streams;3198 commit_params.stream_count = dc_state->stream_count;3199 dc_exit_ips_for_hw_access(dm->dc);3200 WARN_ON(!dc_commit_streams(dm->dc, &commit_params));3201 3202 dm_gpureset_commit_state(dm->cached_dc_state, dm);3203 3204 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);3205 3206 dc_state_release(dm->cached_dc_state);3207 dm->cached_dc_state = NULL;3208 3209 amdgpu_dm_irq_resume_late(adev);3210 3211 mutex_unlock(&dm->dc_lock);3212 3213 return 0;3214 }3215 /* Recreate dc_state - DC invalidates it when setting power state to S3. */3216 dc_state_release(dm_state->context);3217 dm_state->context = dc_state_create(dm->dc, NULL);3218 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */3219 3220 /* Before powering on DC we need to re-initialize DMUB. */3221 dm_dmub_hw_resume(adev);3222 3223 /* Re-enable outbox interrupts for DPIA. */3224 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {3225 amdgpu_dm_outbox_init(adev);3226 dc_enable_dmub_outbox(adev->dm.dc);3227 }3228 3229 /* power on hardware */3230 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);3231 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);3232 3233 /* program HPD filter */3234 dc_resume(dm->dc);3235 3236 /*3237 * early enable HPD Rx IRQ, should be done before set mode as short3238 * pulse interrupts are used for MST3239 */3240 amdgpu_dm_irq_resume_early(adev);3241 3242 /* On resume we need to rewrite the MSTM control bits to enable MST*/3243 s3_handle_mst(ddev, false);3244 3245 /* Do detection*/3246 drm_connector_list_iter_begin(ddev, &iter);3247 drm_for_each_connector_iter(connector, &iter) {3248 3249 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)3250 continue;3251 3252 aconnector = to_amdgpu_dm_connector(connector);3253 3254 if (!aconnector->dc_link)3255 continue;3256 3257 /*3258 * this is the case when traversing through already created end sink3259 * MST connectors, should be skipped3260 */3261 if (aconnector->mst_root)3262 continue;3263 3264 mutex_lock(&aconnector->hpd_lock);3265 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))3266 DRM_ERROR("KMS: Failed to detect connector\n");3267 3268 if (aconnector->base.force && new_connection_type == dc_connection_none) {3269 emulated_link_detect(aconnector->dc_link);3270 } else {3271 mutex_lock(&dm->dc_lock);3272 dc_exit_ips_for_hw_access(dm->dc);3273 dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4);3274 mutex_unlock(&dm->dc_lock);3275 }3276 3277 if (aconnector->fake_enable && aconnector->dc_link->local_sink)3278 aconnector->fake_enable = false;3279 3280 if (aconnector->dc_sink)3281 dc_sink_release(aconnector->dc_sink);3282 aconnector->dc_sink = NULL;3283 amdgpu_dm_update_connector_after_detect(aconnector);3284 mutex_unlock(&aconnector->hpd_lock);3285 }3286 drm_connector_list_iter_end(&iter);3287 3288 /* Force mode set in atomic commit */3289 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {3290 new_crtc_state->active_changed = true;3291 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);3292 reset_freesync_config_for_crtc(dm_new_crtc_state);3293 }3294 3295 /*3296 * atomic_check is expected to create the dc states. We need to release3297 * them here, since they were duplicated as part of the suspend3298 * procedure.3299 */3300 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {3301 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);3302 if (dm_new_crtc_state->stream) {3303 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);3304 dc_stream_release(dm_new_crtc_state->stream);3305 dm_new_crtc_state->stream = NULL;3306 }3307 dm_new_crtc_state->base.color_mgmt_changed = true;3308 }3309 3310 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {3311 dm_new_plane_state = to_dm_plane_state(new_plane_state);3312 if (dm_new_plane_state->dc_state) {3313 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);3314 dc_plane_state_release(dm_new_plane_state->dc_state);3315 dm_new_plane_state->dc_state = NULL;3316 }3317 }3318 3319 drm_atomic_helper_resume(ddev, dm->cached_state);3320 3321 dm->cached_state = NULL;3322 3323 /* Do mst topology probing after resuming cached state*/3324 drm_connector_list_iter_begin(ddev, &iter);3325 drm_for_each_connector_iter(connector, &iter) {3326 3327 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)3328 continue;3329 3330 aconnector = to_amdgpu_dm_connector(connector);3331 if (aconnector->dc_link->type != dc_connection_mst_branch ||3332 aconnector->mst_root)3333 continue;3334 3335 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);3336 3337 if (ret < 0) {3338 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,3339 aconnector->dc_link);3340 need_hotplug = true;3341 }3342 }3343 drm_connector_list_iter_end(&iter);3344 3345 if (need_hotplug)3346 drm_kms_helper_hotplug_event(ddev);3347 3348 amdgpu_dm_irq_resume_late(adev);3349 3350 amdgpu_dm_smu_write_watermarks_table(adev);3351 3352 return 0;3353}3354 3355/**3356 * DOC: DM Lifecycle3357 *3358 * DM (and consequently DC) is registered in the amdgpu base driver as a IP3359 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to3360 * the base driver's device list to be initialized and torn down accordingly.3361 *3362 * The functions to do so are provided as hooks in &struct amd_ip_funcs.3363 */3364 3365static const struct amd_ip_funcs amdgpu_dm_funcs = {3366 .name = "dm",3367 .early_init = dm_early_init,3368 .late_init = dm_late_init,3369 .sw_init = dm_sw_init,3370 .sw_fini = dm_sw_fini,3371 .early_fini = amdgpu_dm_early_fini,3372 .hw_init = dm_hw_init,3373 .hw_fini = dm_hw_fini,3374 .suspend = dm_suspend,3375 .resume = dm_resume,3376 .is_idle = dm_is_idle,3377 .wait_for_idle = dm_wait_for_idle,3378 .check_soft_reset = dm_check_soft_reset,3379 .soft_reset = dm_soft_reset,3380 .set_clockgating_state = dm_set_clockgating_state,3381 .set_powergating_state = dm_set_powergating_state,3382 .dump_ip_state = NULL,3383 .print_ip_state = NULL,3384};3385 3386const struct amdgpu_ip_block_version dm_ip_block = {3387 .type = AMD_IP_BLOCK_TYPE_DCE,3388 .major = 1,3389 .minor = 0,3390 .rev = 0,3391 .funcs = &amdgpu_dm_funcs,3392};3393 3394 3395/**3396 * DOC: atomic3397 *3398 * *WIP*3399 */3400 3401static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {3402 .fb_create = amdgpu_display_user_framebuffer_create,3403 .get_format_info = amdgpu_dm_plane_get_format_info,3404 .atomic_check = amdgpu_dm_atomic_check,3405 .atomic_commit = drm_atomic_helper_commit,3406};3407 3408static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {3409 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,3410 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,3411};3412 3413static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)3414{3415 struct amdgpu_dm_backlight_caps *caps;3416 struct drm_connector *conn_base;3417 struct amdgpu_device *adev;3418 struct drm_luminance_range_info *luminance_range;3419 3420 if (aconnector->bl_idx == -1 ||3421 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)3422 return;3423 3424 conn_base = &aconnector->base;3425 adev = drm_to_adev(conn_base->dev);3426 3427 caps = &adev->dm.backlight_caps[aconnector->bl_idx];3428 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;3429 caps->aux_support = false;3430 3431 if (caps->ext_caps->bits.oled == 13432 /*3433 * ||3434 * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||3435 * caps->ext_caps->bits.hdr_aux_backlight_control == 13436 */)3437 caps->aux_support = true;3438 3439 if (amdgpu_backlight == 0)3440 caps->aux_support = false;3441 else if (amdgpu_backlight == 1)3442 caps->aux_support = true;3443 3444 luminance_range = &conn_base->display_info.luminance_range;3445 3446 if (luminance_range->max_luminance) {3447 caps->aux_min_input_signal = luminance_range->min_luminance;3448 caps->aux_max_input_signal = luminance_range->max_luminance;3449 } else {3450 caps->aux_min_input_signal = 0;3451 caps->aux_max_input_signal = 512;3452 }3453}3454 3455void amdgpu_dm_update_connector_after_detect(3456 struct amdgpu_dm_connector *aconnector)3457{3458 struct drm_connector *connector = &aconnector->base;3459 struct drm_device *dev = connector->dev;3460 struct dc_sink *sink;3461 3462 /* MST handled by drm_mst framework */3463 if (aconnector->mst_mgr.mst_state == true)3464 return;3465 3466 sink = aconnector->dc_link->local_sink;3467 if (sink)3468 dc_sink_retain(sink);3469 3470 /*3471 * Edid mgmt connector gets first update only in mode_valid hook and then3472 * the connector sink is set to either fake or physical sink depends on link status.3473 * Skip if already done during boot.3474 */3475 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED3476 && aconnector->dc_em_sink) {3477 3478 /*3479 * For S3 resume with headless use eml_sink to fake stream3480 * because on resume connector->sink is set to NULL3481 */3482 mutex_lock(&dev->mode_config.mutex);3483 3484 if (sink) {3485 if (aconnector->dc_sink) {3486 amdgpu_dm_update_freesync_caps(connector, NULL);3487 /*3488 * retain and release below are used to3489 * bump up refcount for sink because the link doesn't point3490 * to it anymore after disconnect, so on next crtc to connector3491 * reshuffle by UMD we will get into unwanted dc_sink release3492 */3493 dc_sink_release(aconnector->dc_sink);3494 }3495 aconnector->dc_sink = sink;3496 dc_sink_retain(aconnector->dc_sink);3497 amdgpu_dm_update_freesync_caps(connector,3498 aconnector->edid);3499 } else {3500 amdgpu_dm_update_freesync_caps(connector, NULL);3501 if (!aconnector->dc_sink) {3502 aconnector->dc_sink = aconnector->dc_em_sink;3503 dc_sink_retain(aconnector->dc_sink);3504 }3505 }3506 3507 mutex_unlock(&dev->mode_config.mutex);3508 3509 if (sink)3510 dc_sink_release(sink);3511 return;3512 }3513 3514 /*3515 * TODO: temporary guard to look for proper fix3516 * if this sink is MST sink, we should not do anything3517 */3518 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {3519 dc_sink_release(sink);3520 return;3521 }3522 3523 if (aconnector->dc_sink == sink) {3524 /*3525 * We got a DP short pulse (Link Loss, DP CTS, etc...).3526 * Do nothing!!3527 */3528 drm_dbg_kms(dev, "DCHPD: connector_id=%d: dc_sink didn't change.\n",3529 aconnector->connector_id);3530 if (sink)3531 dc_sink_release(sink);3532 return;3533 }3534 3535 drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",3536 aconnector->connector_id, aconnector->dc_sink, sink);3537 3538 mutex_lock(&dev->mode_config.mutex);3539 3540 /*3541 * 1. Update status of the drm connector3542 * 2. Send an event and let userspace tell us what to do3543 */3544 if (sink) {3545 /*3546 * TODO: check if we still need the S3 mode update workaround.3547 * If yes, put it here.3548 */3549 if (aconnector->dc_sink) {3550 amdgpu_dm_update_freesync_caps(connector, NULL);3551 dc_sink_release(aconnector->dc_sink);3552 }3553 3554 aconnector->dc_sink = sink;3555 dc_sink_retain(aconnector->dc_sink);3556 if (sink->dc_edid.length == 0) {3557 aconnector->edid = NULL;3558 if (aconnector->dc_link->aux_mode) {3559 drm_dp_cec_unset_edid(3560 &aconnector->dm_dp_aux.aux);3561 }3562 } else {3563 aconnector->edid =3564 (struct edid *)sink->dc_edid.raw_edid;3565 3566 if (aconnector->dc_link->aux_mode)3567 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,3568 aconnector->edid);3569 }3570 3571 if (!aconnector->timing_requested) {3572 aconnector->timing_requested =3573 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);3574 if (!aconnector->timing_requested)3575 drm_err(dev,3576 "failed to create aconnector->requested_timing\n");3577 }3578 3579 drm_connector_update_edid_property(connector, aconnector->edid);3580 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);3581 update_connector_ext_caps(aconnector);3582 } else {3583 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);3584 amdgpu_dm_update_freesync_caps(connector, NULL);3585 drm_connector_update_edid_property(connector, NULL);3586 aconnector->num_modes = 0;3587 dc_sink_release(aconnector->dc_sink);3588 aconnector->dc_sink = NULL;3589 aconnector->edid = NULL;3590 kfree(aconnector->timing_requested);3591 aconnector->timing_requested = NULL;3592 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */3593 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)3594 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;3595 }3596 3597 mutex_unlock(&dev->mode_config.mutex);3598 3599 update_subconnector_property(aconnector);3600 3601 if (sink)3602 dc_sink_release(sink);3603}3604 3605static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)3606{3607 struct drm_connector *connector = &aconnector->base;3608 struct drm_device *dev = connector->dev;3609 enum dc_connection_type new_connection_type = dc_connection_none;3610 struct amdgpu_device *adev = drm_to_adev(dev);3611 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);3612 struct dc *dc = aconnector->dc_link->ctx->dc;3613 bool ret = false;3614 3615 if (adev->dm.disable_hpd_irq)3616 return;3617 3618 /*3619 * In case of failure or MST no need to update connector status or notify the OS3620 * since (for MST case) MST does this in its own context.3621 */3622 mutex_lock(&aconnector->hpd_lock);3623 3624 if (adev->dm.hdcp_workqueue) {3625 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);3626 dm_con_state->update_hdcp = true;3627 }3628 if (aconnector->fake_enable)3629 aconnector->fake_enable = false;3630 3631 aconnector->timing_changed = false;3632 3633 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))3634 DRM_ERROR("KMS: Failed to detect connector\n");3635 3636 if (aconnector->base.force && new_connection_type == dc_connection_none) {3637 emulated_link_detect(aconnector->dc_link);3638 3639 drm_modeset_lock_all(dev);3640 dm_restore_drm_connector_state(dev, connector);3641 drm_modeset_unlock_all(dev);3642 3643 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)3644 drm_kms_helper_connector_hotplug_event(connector);3645 } else {3646 mutex_lock(&adev->dm.dc_lock);3647 dc_exit_ips_for_hw_access(dc);3648 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);3649 mutex_unlock(&adev->dm.dc_lock);3650 if (ret) {3651 amdgpu_dm_update_connector_after_detect(aconnector);3652 3653 drm_modeset_lock_all(dev);3654 dm_restore_drm_connector_state(dev, connector);3655 drm_modeset_unlock_all(dev);3656 3657 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)3658 drm_kms_helper_connector_hotplug_event(connector);3659 }3660 }3661 mutex_unlock(&aconnector->hpd_lock);3662 3663}3664 3665static void handle_hpd_irq(void *param)3666{3667 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;3668 3669 handle_hpd_irq_helper(aconnector);3670 3671}3672 3673static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,3674 union hpd_irq_data hpd_irq_data)3675{3676 struct hpd_rx_irq_offload_work *offload_work =3677 kzalloc(sizeof(*offload_work), GFP_KERNEL);3678 3679 if (!offload_work) {3680 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");3681 return;3682 }3683 3684 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);3685 offload_work->data = hpd_irq_data;3686 offload_work->offload_wq = offload_wq;3687 3688 queue_work(offload_wq->wq, &offload_work->work);3689 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");3690}3691 3692static void handle_hpd_rx_irq(void *param)3693{3694 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;3695 struct drm_connector *connector = &aconnector->base;3696 struct drm_device *dev = connector->dev;3697 struct dc_link *dc_link = aconnector->dc_link;3698 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;3699 bool result = false;3700 enum dc_connection_type new_connection_type = dc_connection_none;3701 struct amdgpu_device *adev = drm_to_adev(dev);3702 union hpd_irq_data hpd_irq_data;3703 bool link_loss = false;3704 bool has_left_work = false;3705 int idx = dc_link->link_index;3706 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];3707 struct dc *dc = aconnector->dc_link->ctx->dc;3708 3709 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));3710 3711 if (adev->dm.disable_hpd_irq)3712 return;3713 3714 /*3715 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio3716 * conflict, after implement i2c helper, this mutex should be3717 * retired.3718 */3719 mutex_lock(&aconnector->hpd_lock);3720 3721 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,3722 &link_loss, true, &has_left_work);3723 3724 if (!has_left_work)3725 goto out;3726 3727 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {3728 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);3729 goto out;3730 }3731 3732 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {3733 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||3734 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {3735 bool skip = false;3736 3737 /*3738 * DOWN_REP_MSG_RDY is also handled by polling method3739 * mgr->cbs->poll_hpd_irq()3740 */3741 spin_lock(&offload_wq->offload_lock);3742 skip = offload_wq->is_handling_mst_msg_rdy_event;3743 3744 if (!skip)3745 offload_wq->is_handling_mst_msg_rdy_event = true;3746 3747 spin_unlock(&offload_wq->offload_lock);3748 3749 if (!skip)3750 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);3751 3752 goto out;3753 }3754 3755 if (link_loss) {3756 bool skip = false;3757 3758 spin_lock(&offload_wq->offload_lock);3759 skip = offload_wq->is_handling_link_loss;3760 3761 if (!skip)3762 offload_wq->is_handling_link_loss = true;3763 3764 spin_unlock(&offload_wq->offload_lock);3765 3766 if (!skip)3767 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);3768 3769 goto out;3770 }3771 }3772 3773out:3774 if (result && !is_mst_root_connector) {3775 /* Downstream Port status changed. */3776 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))3777 DRM_ERROR("KMS: Failed to detect connector\n");3778 3779 if (aconnector->base.force && new_connection_type == dc_connection_none) {3780 emulated_link_detect(dc_link);3781 3782 if (aconnector->fake_enable)3783 aconnector->fake_enable = false;3784 3785 amdgpu_dm_update_connector_after_detect(aconnector);3786 3787 3788 drm_modeset_lock_all(dev);3789 dm_restore_drm_connector_state(dev, connector);3790 drm_modeset_unlock_all(dev);3791 3792 drm_kms_helper_connector_hotplug_event(connector);3793 } else {3794 bool ret = false;3795 3796 mutex_lock(&adev->dm.dc_lock);3797 dc_exit_ips_for_hw_access(dc);3798 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);3799 mutex_unlock(&adev->dm.dc_lock);3800 3801 if (ret) {3802 if (aconnector->fake_enable)3803 aconnector->fake_enable = false;3804 3805 amdgpu_dm_update_connector_after_detect(aconnector);3806 3807 drm_modeset_lock_all(dev);3808 dm_restore_drm_connector_state(dev, connector);3809 drm_modeset_unlock_all(dev);3810 3811 drm_kms_helper_connector_hotplug_event(connector);3812 }3813 }3814 }3815 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {3816 if (adev->dm.hdcp_workqueue)3817 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);3818 }3819 3820 if (dc_link->type != dc_connection_mst_branch)3821 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);3822 3823 mutex_unlock(&aconnector->hpd_lock);3824}3825 3826static int register_hpd_handlers(struct amdgpu_device *adev)3827{3828 struct drm_device *dev = adev_to_drm(adev);3829 struct drm_connector *connector;3830 struct amdgpu_dm_connector *aconnector;3831 const struct dc_link *dc_link;3832 struct dc_interrupt_params int_params = {0};3833 3834 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;3835 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;3836 3837 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {3838 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD,3839 dmub_hpd_callback, true)) {3840 DRM_ERROR("amdgpu: fail to register dmub hpd callback");3841 return -EINVAL;3842 }3843 3844 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ,3845 dmub_hpd_callback, true)) {3846 DRM_ERROR("amdgpu: fail to register dmub hpd callback");3847 return -EINVAL;3848 }3849 3850 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_SENSE_NOTIFY,3851 dmub_hpd_sense_callback, true)) {3852 DRM_ERROR("amdgpu: fail to register dmub hpd sense callback");3853 return -EINVAL;3854 }3855 }3856 3857 list_for_each_entry(connector,3858 &dev->mode_config.connector_list, head) {3859 3860 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)3861 continue;3862 3863 aconnector = to_amdgpu_dm_connector(connector);3864 dc_link = aconnector->dc_link;3865 3866 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {3867 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;3868 int_params.irq_source = dc_link->irq_source_hpd;3869 3870 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||3871 int_params.irq_source < DC_IRQ_SOURCE_HPD1 ||3872 int_params.irq_source > DC_IRQ_SOURCE_HPD6) {3873 DRM_ERROR("Failed to register hpd irq!\n");3874 return -EINVAL;3875 }3876 3877 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,3878 handle_hpd_irq, (void *) aconnector))3879 return -ENOMEM;3880 }3881 3882 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {3883 3884 /* Also register for DP short pulse (hpd_rx). */3885 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;3886 int_params.irq_source = dc_link->irq_source_hpd_rx;3887 3888 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||3889 int_params.irq_source < DC_IRQ_SOURCE_HPD1RX ||3890 int_params.irq_source > DC_IRQ_SOURCE_HPD6RX) {3891 DRM_ERROR("Failed to register hpd rx irq!\n");3892 return -EINVAL;3893 }3894 3895 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,3896 handle_hpd_rx_irq, (void *) aconnector))3897 return -ENOMEM;3898 }3899 }3900 return 0;3901}3902 3903#if defined(CONFIG_DRM_AMD_DC_SI)3904/* Register IRQ sources and initialize IRQ callbacks */3905static int dce60_register_irq_handlers(struct amdgpu_device *adev)3906{3907 struct dc *dc = adev->dm.dc;3908 struct common_irq_params *c_irq_params;3909 struct dc_interrupt_params int_params = {0};3910 int r;3911 int i;3912 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;3913 3914 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;3915 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;3916 3917 /*3918 * Actions of amdgpu_irq_add_id():3919 * 1. Register a set() function with base driver.3920 * Base driver will call set() function to enable/disable an3921 * interrupt in DC hardware.3922 * 2. Register amdgpu_dm_irq_handler().3923 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts3924 * coming from DC hardware.3925 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC3926 * for acknowledging and handling.3927 */3928 3929 /* Use VBLANK interrupt */3930 for (i = 0; i < adev->mode_info.num_crtc; i++) {3931 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);3932 if (r) {3933 DRM_ERROR("Failed to add crtc irq id!\n");3934 return r;3935 }3936 3937 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;3938 int_params.irq_source =3939 dc_interrupt_to_irq_source(dc, i + 1, 0);3940 3941 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||3942 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 ||3943 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) {3944 DRM_ERROR("Failed to register vblank irq!\n");3945 return -EINVAL;3946 }3947 3948 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];3949 3950 c_irq_params->adev = adev;3951 c_irq_params->irq_src = int_params.irq_source;3952 3953 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,3954 dm_crtc_high_irq, c_irq_params))3955 return -ENOMEM;3956 }3957 3958 /* Use GRPH_PFLIP interrupt */3959 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;3960 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {3961 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);3962 if (r) {3963 DRM_ERROR("Failed to add page flip irq id!\n");3964 return r;3965 }3966 3967 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;3968 int_params.irq_source =3969 dc_interrupt_to_irq_source(dc, i, 0);3970 3971 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||3972 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST ||3973 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) {3974 DRM_ERROR("Failed to register pflip irq!\n");3975 return -EINVAL;3976 }3977 3978 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];3979 3980 c_irq_params->adev = adev;3981 c_irq_params->irq_src = int_params.irq_source;3982 3983 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,3984 dm_pflip_high_irq, c_irq_params))3985 return -ENOMEM;3986 }3987 3988 /* HPD */3989 r = amdgpu_irq_add_id(adev, client_id,3990 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);3991 if (r) {3992 DRM_ERROR("Failed to add hpd irq id!\n");3993 return r;3994 }3995 3996 r = register_hpd_handlers(adev);3997 3998 return r;3999}4000#endif4001 4002/* Register IRQ sources and initialize IRQ callbacks */4003static int dce110_register_irq_handlers(struct amdgpu_device *adev)4004{4005 struct dc *dc = adev->dm.dc;4006 struct common_irq_params *c_irq_params;4007 struct dc_interrupt_params int_params = {0};4008 int r;4009 int i;4010 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;4011 4012 if (adev->family >= AMDGPU_FAMILY_AI)4013 client_id = SOC15_IH_CLIENTID_DCE;4014 4015 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;4016 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;4017 4018 /*4019 * Actions of amdgpu_irq_add_id():4020 * 1. Register a set() function with base driver.4021 * Base driver will call set() function to enable/disable an4022 * interrupt in DC hardware.4023 * 2. Register amdgpu_dm_irq_handler().4024 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts4025 * coming from DC hardware.4026 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC4027 * for acknowledging and handling.4028 */4029 4030 /* Use VBLANK interrupt */4031 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {4032 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);4033 if (r) {4034 DRM_ERROR("Failed to add crtc irq id!\n");4035 return r;4036 }4037 4038 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;4039 int_params.irq_source =4040 dc_interrupt_to_irq_source(dc, i, 0);4041 4042 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||4043 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 ||4044 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) {4045 DRM_ERROR("Failed to register vblank irq!\n");4046 return -EINVAL;4047 }4048 4049 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];4050 4051 c_irq_params->adev = adev;4052 c_irq_params->irq_src = int_params.irq_source;4053 4054 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,4055 dm_crtc_high_irq, c_irq_params))4056 return -ENOMEM;4057 }4058 4059 /* Use VUPDATE interrupt */4060 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {4061 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);4062 if (r) {4063 DRM_ERROR("Failed to add vupdate irq id!\n");4064 return r;4065 }4066 4067 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;4068 int_params.irq_source =4069 dc_interrupt_to_irq_source(dc, i, 0);4070 4071 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||4072 int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 ||4073 int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) {4074 DRM_ERROR("Failed to register vupdate irq!\n");4075 return -EINVAL;4076 }4077 4078 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];4079 4080 c_irq_params->adev = adev;4081 c_irq_params->irq_src = int_params.irq_source;4082 4083 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,4084 dm_vupdate_high_irq, c_irq_params))4085 return -ENOMEM;4086 }4087 4088 /* Use GRPH_PFLIP interrupt */4089 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;4090 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {4091 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);4092 if (r) {4093 DRM_ERROR("Failed to add page flip irq id!\n");4094 return r;4095 }4096 4097 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;4098 int_params.irq_source =4099 dc_interrupt_to_irq_source(dc, i, 0);4100 4101 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||4102 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST ||4103 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) {4104 DRM_ERROR("Failed to register pflip irq!\n");4105 return -EINVAL;4106 }4107 4108 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];4109 4110 c_irq_params->adev = adev;4111 c_irq_params->irq_src = int_params.irq_source;4112 4113 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,4114 dm_pflip_high_irq, c_irq_params))4115 return -ENOMEM;4116 }4117 4118 /* HPD */4119 r = amdgpu_irq_add_id(adev, client_id,4120 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);4121 if (r) {4122 DRM_ERROR("Failed to add hpd irq id!\n");4123 return r;4124 }4125 4126 r = register_hpd_handlers(adev);4127 4128 return r;4129}4130 4131/* Register IRQ sources and initialize IRQ callbacks */4132static int dcn10_register_irq_handlers(struct amdgpu_device *adev)4133{4134 struct dc *dc = adev->dm.dc;4135 struct common_irq_params *c_irq_params;4136 struct dc_interrupt_params int_params = {0};4137 int r;4138 int i;4139#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)4140 static const unsigned int vrtl_int_srcid[] = {4141 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,4142 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,4143 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,4144 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,4145 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,4146 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL4147 };4148#endif4149 4150 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;4151 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;4152 4153 /*4154 * Actions of amdgpu_irq_add_id():4155 * 1. Register a set() function with base driver.4156 * Base driver will call set() function to enable/disable an4157 * interrupt in DC hardware.4158 * 2. Register amdgpu_dm_irq_handler().4159 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts4160 * coming from DC hardware.4161 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC4162 * for acknowledging and handling.4163 */4164 4165 /* Use VSTARTUP interrupt */4166 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;4167 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;4168 i++) {4169 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);4170 4171 if (r) {4172 DRM_ERROR("Failed to add crtc irq id!\n");4173 return r;4174 }4175 4176 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;4177 int_params.irq_source =4178 dc_interrupt_to_irq_source(dc, i, 0);4179 4180 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||4181 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 ||4182 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) {4183 DRM_ERROR("Failed to register vblank irq!\n");4184 return -EINVAL;4185 }4186 4187 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];4188 4189 c_irq_params->adev = adev;4190 c_irq_params->irq_src = int_params.irq_source;4191 4192 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,4193 dm_crtc_high_irq, c_irq_params))4194 return -ENOMEM;4195 }4196 4197 /* Use otg vertical line interrupt */4198#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)4199 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {4200 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,4201 vrtl_int_srcid[i], &adev->vline0_irq);4202 4203 if (r) {4204 DRM_ERROR("Failed to add vline0 irq id!\n");4205 return r;4206 }4207 4208 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;4209 int_params.irq_source =4210 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);4211 4212 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||4213 int_params.irq_source < DC_IRQ_SOURCE_DC1_VLINE0 ||4214 int_params.irq_source > DC_IRQ_SOURCE_DC6_VLINE0) {4215 DRM_ERROR("Failed to register vline0 irq!\n");4216 return -EINVAL;4217 }4218 4219 c_irq_params = &adev->dm.vline0_params[int_params.irq_source4220 - DC_IRQ_SOURCE_DC1_VLINE0];4221 4222 c_irq_params->adev = adev;4223 c_irq_params->irq_src = int_params.irq_source;4224 4225 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,4226 dm_dcn_vertical_interrupt0_high_irq,4227 c_irq_params))4228 return -ENOMEM;4229 }4230#endif4231 4232 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to4233 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx4234 * to trigger at end of each vblank, regardless of state of the lock,4235 * matching DCE behaviour.4236 */4237 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;4238 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;4239 i++) {4240 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);4241 4242 if (r) {4243 DRM_ERROR("Failed to add vupdate irq id!\n");4244 return r;4245 }4246 4247 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;4248 int_params.irq_source =4249 dc_interrupt_to_irq_source(dc, i, 0);4250 4251 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||4252 int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 ||4253 int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) {4254 DRM_ERROR("Failed to register vupdate irq!\n");4255 return -EINVAL;4256 }4257 4258 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];4259 4260 c_irq_params->adev = adev;4261 c_irq_params->irq_src = int_params.irq_source;4262 4263 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,4264 dm_vupdate_high_irq, c_irq_params))4265 return -ENOMEM;4266 }4267 4268 /* Use GRPH_PFLIP interrupt */4269 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;4270 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;4271 i++) {4272 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);4273 if (r) {4274 DRM_ERROR("Failed to add page flip irq id!\n");4275 return r;4276 }4277 4278 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;4279 int_params.irq_source =4280 dc_interrupt_to_irq_source(dc, i, 0);4281 4282 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||4283 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST ||4284 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) {4285 DRM_ERROR("Failed to register pflip irq!\n");4286 return -EINVAL;4287 }4288 4289 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];4290 4291 c_irq_params->adev = adev;4292 c_irq_params->irq_src = int_params.irq_source;4293 4294 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,4295 dm_pflip_high_irq, c_irq_params))4296 return -ENOMEM;4297 }4298 4299 /* HPD */4300 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,4301 &adev->hpd_irq);4302 if (r) {4303 DRM_ERROR("Failed to add hpd irq id!\n");4304 return r;4305 }4306 4307 r = register_hpd_handlers(adev);4308 4309 return r;4310}4311/* Register Outbox IRQ sources and initialize IRQ callbacks */4312static int register_outbox_irq_handlers(struct amdgpu_device *adev)4313{4314 struct dc *dc = adev->dm.dc;4315 struct common_irq_params *c_irq_params;4316 struct dc_interrupt_params int_params = {0};4317 int r, i;4318 4319 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;4320 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;4321 4322 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,4323 &adev->dmub_outbox_irq);4324 if (r) {4325 DRM_ERROR("Failed to add outbox irq id!\n");4326 return r;4327 }4328 4329 if (dc->ctx->dmub_srv) {4330 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;4331 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;4332 int_params.irq_source =4333 dc_interrupt_to_irq_source(dc, i, 0);4334 4335 c_irq_params = &adev->dm.dmub_outbox_params[0];4336 4337 c_irq_params->adev = adev;4338 c_irq_params->irq_src = int_params.irq_source;4339 4340 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,4341 dm_dmub_outbox1_low_irq, c_irq_params))4342 return -ENOMEM;4343 }4344 4345 return 0;4346}4347 4348/*4349 * Acquires the lock for the atomic state object and returns4350 * the new atomic state.4351 *4352 * This should only be called during atomic check.4353 */4354int dm_atomic_get_state(struct drm_atomic_state *state,4355 struct dm_atomic_state **dm_state)4356{4357 struct drm_device *dev = state->dev;4358 struct amdgpu_device *adev = drm_to_adev(dev);4359 struct amdgpu_display_manager *dm = &adev->dm;4360 struct drm_private_state *priv_state;4361 4362 if (*dm_state)4363 return 0;4364 4365 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);4366 if (IS_ERR(priv_state))4367 return PTR_ERR(priv_state);4368 4369 *dm_state = to_dm_atomic_state(priv_state);4370 4371 return 0;4372}4373 4374static struct dm_atomic_state *4375dm_atomic_get_new_state(struct drm_atomic_state *state)4376{4377 struct drm_device *dev = state->dev;4378 struct amdgpu_device *adev = drm_to_adev(dev);4379 struct amdgpu_display_manager *dm = &adev->dm;4380 struct drm_private_obj *obj;4381 struct drm_private_state *new_obj_state;4382 int i;4383 4384 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {4385 if (obj->funcs == dm->atomic_obj.funcs)4386 return to_dm_atomic_state(new_obj_state);4387 }4388 4389 return NULL;4390}4391 4392static struct drm_private_state *4393dm_atomic_duplicate_state(struct drm_private_obj *obj)4394{4395 struct dm_atomic_state *old_state, *new_state;4396 4397 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);4398 if (!new_state)4399 return NULL;4400 4401 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);4402 4403 old_state = to_dm_atomic_state(obj->state);4404 4405 if (old_state && old_state->context)4406 new_state->context = dc_state_create_copy(old_state->context);4407 4408 if (!new_state->context) {4409 kfree(new_state);4410 return NULL;4411 }4412 4413 return &new_state->base;4414}4415 4416static void dm_atomic_destroy_state(struct drm_private_obj *obj,4417 struct drm_private_state *state)4418{4419 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);4420 4421 if (dm_state && dm_state->context)4422 dc_state_release(dm_state->context);4423 4424 kfree(dm_state);4425}4426 4427static struct drm_private_state_funcs dm_atomic_state_funcs = {4428 .atomic_duplicate_state = dm_atomic_duplicate_state,4429 .atomic_destroy_state = dm_atomic_destroy_state,4430};4431 4432static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)4433{4434 struct dm_atomic_state *state;4435 int r;4436 4437 adev->mode_info.mode_config_initialized = true;4438 4439 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;4440 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;4441 4442 adev_to_drm(adev)->mode_config.max_width = 16384;4443 adev_to_drm(adev)->mode_config.max_height = 16384;4444 4445 adev_to_drm(adev)->mode_config.preferred_depth = 24;4446 if (adev->asic_type == CHIP_HAWAII)4447 /* disable prefer shadow for now due to hibernation issues */4448 adev_to_drm(adev)->mode_config.prefer_shadow = 0;4449 else4450 adev_to_drm(adev)->mode_config.prefer_shadow = 1;4451 /* indicates support for immediate flip */4452 adev_to_drm(adev)->mode_config.async_page_flip = true;4453 4454 state = kzalloc(sizeof(*state), GFP_KERNEL);4455 if (!state)4456 return -ENOMEM;4457 4458 state->context = dc_state_create_current_copy(adev->dm.dc);4459 if (!state->context) {4460 kfree(state);4461 return -ENOMEM;4462 }4463 4464 drm_atomic_private_obj_init(adev_to_drm(adev),4465 &adev->dm.atomic_obj,4466 &state->base,4467 &dm_atomic_state_funcs);4468 4469 r = amdgpu_display_modeset_create_props(adev);4470 if (r) {4471 dc_state_release(state->context);4472 kfree(state);4473 return r;4474 }4475 4476#ifdef AMD_PRIVATE_COLOR4477 if (amdgpu_dm_create_color_properties(adev)) {4478 dc_state_release(state->context);4479 kfree(state);4480 return -ENOMEM;4481 }4482#endif4483 4484 r = amdgpu_dm_audio_init(adev);4485 if (r) {4486 dc_state_release(state->context);4487 kfree(state);4488 return r;4489 }4490 4491 return 0;4492}4493 4494#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 124495#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 2554496#define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2)4497#define AUX_BL_DEFAULT_TRANSITION_TIME_MS 504498 4499static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,4500 int bl_idx)4501{4502#if defined(CONFIG_ACPI)4503 struct amdgpu_dm_backlight_caps caps;4504 4505 memset(&caps, 0, sizeof(caps));4506 4507 if (dm->backlight_caps[bl_idx].caps_valid)4508 return;4509 4510 amdgpu_acpi_get_backlight_caps(&caps);4511 4512 /* validate the firmware value is sane */4513 if (caps.caps_valid) {4514 int spread = caps.max_input_signal - caps.min_input_signal;4515 4516 if (caps.max_input_signal > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||4517 caps.min_input_signal < 0 ||4518 spread > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||4519 spread < AMDGPU_DM_MIN_SPREAD) {4520 DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n",4521 caps.min_input_signal, caps.max_input_signal);4522 caps.caps_valid = false;4523 }4524 }4525 4526 if (caps.caps_valid) {4527 dm->backlight_caps[bl_idx].caps_valid = true;4528 if (caps.aux_support)4529 return;4530 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;4531 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;4532 } else {4533 dm->backlight_caps[bl_idx].min_input_signal =4534 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;4535 dm->backlight_caps[bl_idx].max_input_signal =4536 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;4537 }4538#else4539 if (dm->backlight_caps[bl_idx].aux_support)4540 return;4541 4542 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;4543 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;4544#endif4545}4546 4547static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,4548 unsigned int *min, unsigned int *max)4549{4550 if (!caps)4551 return 0;4552 4553 if (caps->aux_support) {4554 // Firmware limits are in nits, DC API wants millinits.4555 *max = 1000 * caps->aux_max_input_signal;4556 *min = 1000 * caps->aux_min_input_signal;4557 } else {4558 // Firmware limits are 8-bit, PWM control is 16-bit.4559 *max = 0x101 * caps->max_input_signal;4560 *min = 0x101 * caps->min_input_signal;4561 }4562 return 1;4563}4564 4565static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,4566 uint32_t brightness)4567{4568 unsigned int min, max;4569 4570 if (!get_brightness_range(caps, &min, &max))4571 return brightness;4572 4573 // Rescale 0..255 to min..max4574 return min + DIV_ROUND_CLOSEST((max - min) * brightness,4575 AMDGPU_MAX_BL_LEVEL);4576}4577 4578static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,4579 uint32_t brightness)4580{4581 unsigned int min, max;4582 4583 if (!get_brightness_range(caps, &min, &max))4584 return brightness;4585 4586 if (brightness < min)4587 return 0;4588 // Rescale min..max to 0..2554589 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),4590 max - min);4591}4592 4593static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,4594 int bl_idx,4595 u32 user_brightness)4596{4597 struct amdgpu_dm_backlight_caps caps;4598 struct dc_link *link;4599 u32 brightness;4600 bool rc, reallow_idle = false;4601 4602 amdgpu_dm_update_backlight_caps(dm, bl_idx);4603 caps = dm->backlight_caps[bl_idx];4604 4605 dm->brightness[bl_idx] = user_brightness;4606 /* update scratch register */4607 if (bl_idx == 0)4608 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);4609 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);4610 link = (struct dc_link *)dm->backlight_link[bl_idx];4611 4612 /* Change brightness based on AUX property */4613 mutex_lock(&dm->dc_lock);4614 if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {4615 dc_allow_idle_optimizations(dm->dc, false);4616 reallow_idle = true;4617 }4618 4619 if (caps.aux_support) {4620 rc = dc_link_set_backlight_level_nits(link, true, brightness,4621 AUX_BL_DEFAULT_TRANSITION_TIME_MS);4622 if (!rc)4623 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);4624 } else {4625 rc = dc_link_set_backlight_level(link, brightness, 0);4626 if (!rc)4627 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);4628 }4629 4630 if (dm->dc->caps.ips_support && reallow_idle)4631 dc_allow_idle_optimizations(dm->dc, true);4632 4633 mutex_unlock(&dm->dc_lock);4634 4635 if (rc)4636 dm->actual_brightness[bl_idx] = user_brightness;4637}4638 4639static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)4640{4641 struct amdgpu_display_manager *dm = bl_get_data(bd);4642 int i;4643 4644 for (i = 0; i < dm->num_of_edps; i++) {4645 if (bd == dm->backlight_dev[i])4646 break;4647 }4648 if (i >= AMDGPU_DM_MAX_NUM_EDP)4649 i = 0;4650 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);4651 4652 return 0;4653}4654 4655static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,4656 int bl_idx)4657{4658 int ret;4659 struct amdgpu_dm_backlight_caps caps;4660 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];4661 4662 amdgpu_dm_update_backlight_caps(dm, bl_idx);4663 caps = dm->backlight_caps[bl_idx];4664 4665 if (caps.aux_support) {4666 u32 avg, peak;4667 bool rc;4668 4669 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);4670 if (!rc)4671 return dm->brightness[bl_idx];4672 return convert_brightness_to_user(&caps, avg);4673 }4674 4675 ret = dc_link_get_backlight_level(link);4676 4677 if (ret == DC_ERROR_UNEXPECTED)4678 return dm->brightness[bl_idx];4679 4680 return convert_brightness_to_user(&caps, ret);4681}4682 4683static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)4684{4685 struct amdgpu_display_manager *dm = bl_get_data(bd);4686 int i;4687 4688 for (i = 0; i < dm->num_of_edps; i++) {4689 if (bd == dm->backlight_dev[i])4690 break;4691 }4692 if (i >= AMDGPU_DM_MAX_NUM_EDP)4693 i = 0;4694 return amdgpu_dm_backlight_get_level(dm, i);4695}4696 4697static const struct backlight_ops amdgpu_dm_backlight_ops = {4698 .options = BL_CORE_SUSPENDRESUME,4699 .get_brightness = amdgpu_dm_backlight_get_brightness,4700 .update_status = amdgpu_dm_backlight_update_status,4701};4702 4703static void4704amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)4705{4706 struct drm_device *drm = aconnector->base.dev;4707 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;4708 struct backlight_properties props = { 0 };4709 struct amdgpu_dm_backlight_caps caps = { 0 };4710 char bl_name[16];4711 4712 if (aconnector->bl_idx == -1)4713 return;4714 4715 if (!acpi_video_backlight_use_native()) {4716 drm_info(drm, "Skipping amdgpu DM backlight registration\n");4717 /* Try registering an ACPI video backlight device instead. */4718 acpi_video_register_backlight();4719 return;4720 }4721 4722 amdgpu_acpi_get_backlight_caps(&caps);4723 if (caps.caps_valid) {4724 if (power_supply_is_system_supplied() > 0)4725 props.brightness = caps.ac_level;4726 else4727 props.brightness = caps.dc_level;4728 } else4729 props.brightness = AMDGPU_MAX_BL_LEVEL;4730 4731 props.max_brightness = AMDGPU_MAX_BL_LEVEL;4732 props.type = BACKLIGHT_RAW;4733 4734 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",4735 drm->primary->index + aconnector->bl_idx);4736 4737 dm->backlight_dev[aconnector->bl_idx] =4738 backlight_device_register(bl_name, aconnector->base.kdev, dm,4739 &amdgpu_dm_backlight_ops, &props);4740 4741 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {4742 DRM_ERROR("DM: Backlight registration failed!\n");4743 dm->backlight_dev[aconnector->bl_idx] = NULL;4744 } else4745 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);4746}4747 4748static int initialize_plane(struct amdgpu_display_manager *dm,4749 struct amdgpu_mode_info *mode_info, int plane_id,4750 enum drm_plane_type plane_type,4751 const struct dc_plane_cap *plane_cap)4752{4753 struct drm_plane *plane;4754 unsigned long possible_crtcs;4755 int ret = 0;4756 4757 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);4758 if (!plane) {4759 DRM_ERROR("KMS: Failed to allocate plane\n");4760 return -ENOMEM;4761 }4762 plane->type = plane_type;4763 4764 /*4765 * HACK: IGT tests expect that the primary plane for a CRTC4766 * can only have one possible CRTC. Only expose support for4767 * any CRTC if they're not going to be used as a primary plane4768 * for a CRTC - like overlay or underlay planes.4769 */4770 possible_crtcs = 1 << plane_id;4771 if (plane_id >= dm->dc->caps.max_streams)4772 possible_crtcs = 0xff;4773 4774 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);4775 4776 if (ret) {4777 DRM_ERROR("KMS: Failed to initialize plane\n");4778 kfree(plane);4779 return ret;4780 }4781 4782 if (mode_info)4783 mode_info->planes[plane_id] = plane;4784 4785 return ret;4786}4787 4788 4789static void setup_backlight_device(struct amdgpu_display_manager *dm,4790 struct amdgpu_dm_connector *aconnector)4791{4792 struct dc_link *link = aconnector->dc_link;4793 int bl_idx = dm->num_of_edps;4794 4795 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||4796 link->type == dc_connection_none)4797 return;4798 4799 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {4800 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");4801 return;4802 }4803 4804 aconnector->bl_idx = bl_idx;4805 4806 amdgpu_dm_update_backlight_caps(dm, bl_idx);4807 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;4808 dm->backlight_link[bl_idx] = link;4809 dm->num_of_edps++;4810 4811 update_connector_ext_caps(aconnector);4812}4813 4814static void amdgpu_set_panel_orientation(struct drm_connector *connector);4815 4816/*4817 * In this architecture, the association4818 * connector -> encoder -> crtc4819 * id not really requried. The crtc and connector will hold the4820 * display_index as an abstraction to use with DAL component4821 *4822 * Returns 0 on success4823 */4824static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)4825{4826 struct amdgpu_display_manager *dm = &adev->dm;4827 s32 i;4828 struct amdgpu_dm_connector *aconnector = NULL;4829 struct amdgpu_encoder *aencoder = NULL;4830 struct amdgpu_mode_info *mode_info = &adev->mode_info;4831 u32 link_cnt;4832 s32 primary_planes;4833 enum dc_connection_type new_connection_type = dc_connection_none;4834 const struct dc_plane_cap *plane;4835 bool psr_feature_enabled = false;4836 bool replay_feature_enabled = false;4837 int max_overlay = dm->dc->caps.max_slave_planes;4838 4839 dm->display_indexes_num = dm->dc->caps.max_streams;4840 /* Update the actual used number of crtc */4841 adev->mode_info.num_crtc = adev->dm.display_indexes_num;4842 4843 amdgpu_dm_set_irq_funcs(adev);4844 4845 link_cnt = dm->dc->caps.max_links;4846 if (amdgpu_dm_mode_config_init(dm->adev)) {4847 DRM_ERROR("DM: Failed to initialize mode config\n");4848 return -EINVAL;4849 }4850 4851 /* There is one primary plane per CRTC */4852 primary_planes = dm->dc->caps.max_streams;4853 if (primary_planes > AMDGPU_MAX_PLANES) {4854 DRM_ERROR("DM: Plane nums out of 6 planes\n");4855 return -EINVAL;4856 }4857 4858 /*4859 * Initialize primary planes, implicit planes for legacy IOCTLS.4860 * Order is reversed to match iteration order in atomic check.4861 */4862 for (i = (primary_planes - 1); i >= 0; i--) {4863 plane = &dm->dc->caps.planes[i];4864 4865 if (initialize_plane(dm, mode_info, i,4866 DRM_PLANE_TYPE_PRIMARY, plane)) {4867 DRM_ERROR("KMS: Failed to initialize primary plane\n");4868 goto fail;4869 }4870 }4871 4872 /*4873 * Initialize overlay planes, index starting after primary planes.4874 * These planes have a higher DRM index than the primary planes since4875 * they should be considered as having a higher z-order.4876 * Order is reversed to match iteration order in atomic check.4877 *4878 * Only support DCN for now, and only expose one so we don't encourage4879 * userspace to use up all the pipes.4880 */4881 for (i = 0; i < dm->dc->caps.max_planes; ++i) {4882 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];4883 4884 /* Do not create overlay if MPO disabled */4885 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)4886 break;4887 4888 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)4889 continue;4890 4891 if (!plane->pixel_format_support.argb8888)4892 continue;4893 4894 if (max_overlay-- == 0)4895 break;4896 4897 if (initialize_plane(dm, NULL, primary_planes + i,4898 DRM_PLANE_TYPE_OVERLAY, plane)) {4899 DRM_ERROR("KMS: Failed to initialize overlay plane\n");4900 goto fail;4901 }4902 }4903 4904 for (i = 0; i < dm->dc->caps.max_streams; i++)4905 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {4906 DRM_ERROR("KMS: Failed to initialize crtc\n");4907 goto fail;4908 }4909 4910 /* Use Outbox interrupt */4911 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {4912 case IP_VERSION(3, 0, 0):4913 case IP_VERSION(3, 1, 2):4914 case IP_VERSION(3, 1, 3):4915 case IP_VERSION(3, 1, 4):4916 case IP_VERSION(3, 1, 5):4917 case IP_VERSION(3, 1, 6):4918 case IP_VERSION(3, 2, 0):4919 case IP_VERSION(3, 2, 1):4920 case IP_VERSION(2, 1, 0):4921 case IP_VERSION(3, 5, 0):4922 case IP_VERSION(3, 5, 1):4923 case IP_VERSION(4, 0, 1):4924 if (register_outbox_irq_handlers(dm->adev)) {4925 DRM_ERROR("DM: Failed to initialize IRQ\n");4926 goto fail;4927 }4928 break;4929 default:4930 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",4931 amdgpu_ip_version(adev, DCE_HWIP, 0));4932 }4933 4934 /* Determine whether to enable PSR support by default. */4935 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {4936 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {4937 case IP_VERSION(3, 1, 2):4938 case IP_VERSION(3, 1, 3):4939 case IP_VERSION(3, 1, 4):4940 case IP_VERSION(3, 1, 5):4941 case IP_VERSION(3, 1, 6):4942 case IP_VERSION(3, 2, 0):4943 case IP_VERSION(3, 2, 1):4944 case IP_VERSION(3, 5, 0):4945 case IP_VERSION(3, 5, 1):4946 case IP_VERSION(4, 0, 1):4947 psr_feature_enabled = true;4948 break;4949 default:4950 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;4951 break;4952 }4953 }4954 4955 /* Determine whether to enable Replay support by default. */4956 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {4957 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {4958 case IP_VERSION(3, 1, 4):4959 case IP_VERSION(3, 2, 0):4960 case IP_VERSION(3, 2, 1):4961 case IP_VERSION(3, 5, 0):4962 case IP_VERSION(3, 5, 1):4963 replay_feature_enabled = true;4964 break;4965 4966 default:4967 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;4968 break;4969 }4970 }4971 4972 if (link_cnt > MAX_LINKS) {4973 DRM_ERROR(4974 "KMS: Cannot support more than %d display indexes\n",4975 MAX_LINKS);4976 goto fail;4977 }4978 4979 /* loops over all connectors on the board */4980 for (i = 0; i < link_cnt; i++) {4981 struct dc_link *link = NULL;4982 4983 link = dc_get_link_at_index(dm->dc, i);4984 4985 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) {4986 struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL);4987 4988 if (!wbcon) {4989 DRM_ERROR("KMS: Failed to allocate writeback connector\n");4990 continue;4991 }4992 4993 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) {4994 DRM_ERROR("KMS: Failed to initialize writeback connector\n");4995 kfree(wbcon);4996 continue;4997 }4998 4999 link->psr_settings.psr_feature_enabled = false;5000 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;5001 5002 continue;5003 }5004 5005 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);5006 if (!aconnector)5007 goto fail;5008 5009 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);5010 if (!aencoder)5011 goto fail;5012 5013 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {5014 DRM_ERROR("KMS: Failed to initialize encoder\n");5015 goto fail;5016 }5017 5018 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {5019 DRM_ERROR("KMS: Failed to initialize connector\n");5020 goto fail;5021 }5022 5023 if (dm->hpd_rx_offload_wq)5024 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector =5025 aconnector;5026 5027 if (!dc_link_detect_connection_type(link, &new_connection_type))5028 DRM_ERROR("KMS: Failed to detect connector\n");5029 5030 if (aconnector->base.force && new_connection_type == dc_connection_none) {5031 emulated_link_detect(link);5032 amdgpu_dm_update_connector_after_detect(aconnector);5033 } else {5034 bool ret = false;5035 5036 mutex_lock(&dm->dc_lock);5037 dc_exit_ips_for_hw_access(dm->dc);5038 ret = dc_link_detect(link, DETECT_REASON_BOOT);5039 mutex_unlock(&dm->dc_lock);5040 5041 if (ret) {5042 amdgpu_dm_update_connector_after_detect(aconnector);5043 setup_backlight_device(dm, aconnector);5044 5045 /* Disable PSR if Replay can be enabled */5046 if (replay_feature_enabled)5047 if (amdgpu_dm_set_replay_caps(link, aconnector))5048 psr_feature_enabled = false;5049 5050 if (psr_feature_enabled)5051 amdgpu_dm_set_psr_caps(link);5052 }5053 }5054 amdgpu_set_panel_orientation(&aconnector->base);5055 }5056 5057 /* Software is initialized. Now we can register interrupt handlers. */5058 switch (adev->asic_type) {5059#if defined(CONFIG_DRM_AMD_DC_SI)5060 case CHIP_TAHITI:5061 case CHIP_PITCAIRN:5062 case CHIP_VERDE:5063 case CHIP_OLAND:5064 if (dce60_register_irq_handlers(dm->adev)) {5065 DRM_ERROR("DM: Failed to initialize IRQ\n");5066 goto fail;5067 }5068 break;5069#endif5070 case CHIP_BONAIRE:5071 case CHIP_HAWAII:5072 case CHIP_KAVERI:5073 case CHIP_KABINI:5074 case CHIP_MULLINS:5075 case CHIP_TONGA:5076 case CHIP_FIJI:5077 case CHIP_CARRIZO:5078 case CHIP_STONEY:5079 case CHIP_POLARIS11:5080 case CHIP_POLARIS10:5081 case CHIP_POLARIS12:5082 case CHIP_VEGAM:5083 case CHIP_VEGA10:5084 case CHIP_VEGA12:5085 case CHIP_VEGA20:5086 if (dce110_register_irq_handlers(dm->adev)) {5087 DRM_ERROR("DM: Failed to initialize IRQ\n");5088 goto fail;5089 }5090 break;5091 default:5092 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {5093 case IP_VERSION(1, 0, 0):5094 case IP_VERSION(1, 0, 1):5095 case IP_VERSION(2, 0, 2):5096 case IP_VERSION(2, 0, 3):5097 case IP_VERSION(2, 0, 0):5098 case IP_VERSION(2, 1, 0):5099 case IP_VERSION(3, 0, 0):5100 case IP_VERSION(3, 0, 2):5101 case IP_VERSION(3, 0, 3):5102 case IP_VERSION(3, 0, 1):5103 case IP_VERSION(3, 1, 2):5104 case IP_VERSION(3, 1, 3):5105 case IP_VERSION(3, 1, 4):5106 case IP_VERSION(3, 1, 5):5107 case IP_VERSION(3, 1, 6):5108 case IP_VERSION(3, 2, 0):5109 case IP_VERSION(3, 2, 1):5110 case IP_VERSION(3, 5, 0):5111 case IP_VERSION(3, 5, 1):5112 case IP_VERSION(4, 0, 1):5113 if (dcn10_register_irq_handlers(dm->adev)) {5114 DRM_ERROR("DM: Failed to initialize IRQ\n");5115 goto fail;5116 }5117 break;5118 default:5119 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",5120 amdgpu_ip_version(adev, DCE_HWIP, 0));5121 goto fail;5122 }5123 break;5124 }5125 5126 return 0;5127fail:5128 kfree(aencoder);5129 kfree(aconnector);5130 5131 return -EINVAL;5132}5133 5134static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)5135{5136 drm_atomic_private_obj_fini(&dm->atomic_obj);5137}5138 5139/******************************************************************************5140 * amdgpu_display_funcs functions5141 *****************************************************************************/5142 5143/*5144 * dm_bandwidth_update - program display watermarks5145 *5146 * @adev: amdgpu_device pointer5147 *5148 * Calculate and program the display watermarks and line buffer allocation.5149 */5150static void dm_bandwidth_update(struct amdgpu_device *adev)5151{5152 /* TODO: implement later */5153}5154 5155static const struct amdgpu_display_funcs dm_display_funcs = {5156 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */5157 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */5158 .backlight_set_level = NULL, /* never called for DC */5159 .backlight_get_level = NULL, /* never called for DC */5160 .hpd_sense = NULL,/* called unconditionally */5161 .hpd_set_polarity = NULL, /* called unconditionally */5162 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */5163 .page_flip_get_scanoutpos =5164 dm_crtc_get_scanoutpos,/* called unconditionally */5165 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */5166 .add_connector = NULL, /* VBIOS parsing. DAL does it. */5167};5168 5169#if defined(CONFIG_DEBUG_KERNEL_DC)5170 5171static ssize_t s3_debug_store(struct device *device,5172 struct device_attribute *attr,5173 const char *buf,5174 size_t count)5175{5176 int ret;5177 int s3_state;5178 struct drm_device *drm_dev = dev_get_drvdata(device);5179 struct amdgpu_device *adev = drm_to_adev(drm_dev);5180 5181 ret = kstrtoint(buf, 0, &s3_state);5182 5183 if (ret == 0) {5184 if (s3_state) {5185 dm_resume(adev);5186 drm_kms_helper_hotplug_event(adev_to_drm(adev));5187 } else5188 dm_suspend(adev);5189 }5190 5191 return ret == 0 ? count : 0;5192}5193 5194DEVICE_ATTR_WO(s3_debug);5195 5196#endif5197 5198static int dm_init_microcode(struct amdgpu_device *adev)5199{5200 char *fw_name_dmub;5201 int r;5202 5203 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {5204 case IP_VERSION(2, 1, 0):5205 fw_name_dmub = FIRMWARE_RENOIR_DMUB;5206 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))5207 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;5208 break;5209 case IP_VERSION(3, 0, 0):5210 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))5211 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;5212 else5213 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;5214 break;5215 case IP_VERSION(3, 0, 1):5216 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;5217 break;5218 case IP_VERSION(3, 0, 2):5219 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;5220 break;5221 case IP_VERSION(3, 0, 3):5222 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;5223 break;5224 case IP_VERSION(3, 1, 2):5225 case IP_VERSION(3, 1, 3):5226 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;5227 break;5228 case IP_VERSION(3, 1, 4):5229 fw_name_dmub = FIRMWARE_DCN_314_DMUB;5230 break;5231 case IP_VERSION(3, 1, 5):5232 fw_name_dmub = FIRMWARE_DCN_315_DMUB;5233 break;5234 case IP_VERSION(3, 1, 6):5235 fw_name_dmub = FIRMWARE_DCN316_DMUB;5236 break;5237 case IP_VERSION(3, 2, 0):5238 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;5239 break;5240 case IP_VERSION(3, 2, 1):5241 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;5242 break;5243 case IP_VERSION(3, 5, 0):5244 fw_name_dmub = FIRMWARE_DCN_35_DMUB;5245 break;5246 case IP_VERSION(3, 5, 1):5247 fw_name_dmub = FIRMWARE_DCN_351_DMUB;5248 break;5249 case IP_VERSION(4, 0, 1):5250 fw_name_dmub = FIRMWARE_DCN_401_DMUB;5251 break;5252 default:5253 /* ASIC doesn't support DMUB. */5254 return 0;5255 }5256 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, "%s", fw_name_dmub);5257 return r;5258}5259 5260static int dm_early_init(void *handle)5261{5262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;5263 struct amdgpu_mode_info *mode_info = &adev->mode_info;5264 struct atom_context *ctx = mode_info->atom_context;5265 int index = GetIndexIntoMasterTable(DATA, Object_Header);5266 u16 data_offset;5267 5268 /* if there is no object header, skip DM */5269 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {5270 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;5271 dev_info(adev->dev, "No object header, skipping DM\n");5272 return -ENOENT;5273 }5274 5275 switch (adev->asic_type) {5276#if defined(CONFIG_DRM_AMD_DC_SI)5277 case CHIP_TAHITI:5278 case CHIP_PITCAIRN:5279 case CHIP_VERDE:5280 adev->mode_info.num_crtc = 6;5281 adev->mode_info.num_hpd = 6;5282 adev->mode_info.num_dig = 6;5283 break;5284 case CHIP_OLAND:5285 adev->mode_info.num_crtc = 2;5286 adev->mode_info.num_hpd = 2;5287 adev->mode_info.num_dig = 2;5288 break;5289#endif5290 case CHIP_BONAIRE:5291 case CHIP_HAWAII:5292 adev->mode_info.num_crtc = 6;5293 adev->mode_info.num_hpd = 6;5294 adev->mode_info.num_dig = 6;5295 break;5296 case CHIP_KAVERI:5297 adev->mode_info.num_crtc = 4;5298 adev->mode_info.num_hpd = 6;5299 adev->mode_info.num_dig = 7;5300 break;5301 case CHIP_KABINI:5302 case CHIP_MULLINS:5303 adev->mode_info.num_crtc = 2;5304 adev->mode_info.num_hpd = 6;5305 adev->mode_info.num_dig = 6;5306 break;5307 case CHIP_FIJI:5308 case CHIP_TONGA:5309 adev->mode_info.num_crtc = 6;5310 adev->mode_info.num_hpd = 6;5311 adev->mode_info.num_dig = 7;5312 break;5313 case CHIP_CARRIZO:5314 adev->mode_info.num_crtc = 3;5315 adev->mode_info.num_hpd = 6;5316 adev->mode_info.num_dig = 9;5317 break;5318 case CHIP_STONEY:5319 adev->mode_info.num_crtc = 2;5320 adev->mode_info.num_hpd = 6;5321 adev->mode_info.num_dig = 9;5322 break;5323 case CHIP_POLARIS11:5324 case CHIP_POLARIS12:5325 adev->mode_info.num_crtc = 5;5326 adev->mode_info.num_hpd = 5;5327 adev->mode_info.num_dig = 5;5328 break;5329 case CHIP_POLARIS10:5330 case CHIP_VEGAM:5331 adev->mode_info.num_crtc = 6;5332 adev->mode_info.num_hpd = 6;5333 adev->mode_info.num_dig = 6;5334 break;5335 case CHIP_VEGA10:5336 case CHIP_VEGA12:5337 case CHIP_VEGA20:5338 adev->mode_info.num_crtc = 6;5339 adev->mode_info.num_hpd = 6;5340 adev->mode_info.num_dig = 6;5341 break;5342 default:5343 5344 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {5345 case IP_VERSION(2, 0, 2):5346 case IP_VERSION(3, 0, 0):5347 adev->mode_info.num_crtc = 6;5348 adev->mode_info.num_hpd = 6;5349 adev->mode_info.num_dig = 6;5350 break;5351 case IP_VERSION(2, 0, 0):5352 case IP_VERSION(3, 0, 2):5353 adev->mode_info.num_crtc = 5;5354 adev->mode_info.num_hpd = 5;5355 adev->mode_info.num_dig = 5;5356 break;5357 case IP_VERSION(2, 0, 3):5358 case IP_VERSION(3, 0, 3):5359 adev->mode_info.num_crtc = 2;5360 adev->mode_info.num_hpd = 2;5361 adev->mode_info.num_dig = 2;5362 break;5363 case IP_VERSION(1, 0, 0):5364 case IP_VERSION(1, 0, 1):5365 case IP_VERSION(3, 0, 1):5366 case IP_VERSION(2, 1, 0):5367 case IP_VERSION(3, 1, 2):5368 case IP_VERSION(3, 1, 3):5369 case IP_VERSION(3, 1, 4):5370 case IP_VERSION(3, 1, 5):5371 case IP_VERSION(3, 1, 6):5372 case IP_VERSION(3, 2, 0):5373 case IP_VERSION(3, 2, 1):5374 case IP_VERSION(3, 5, 0):5375 case IP_VERSION(3, 5, 1):5376 case IP_VERSION(4, 0, 1):5377 adev->mode_info.num_crtc = 4;5378 adev->mode_info.num_hpd = 4;5379 adev->mode_info.num_dig = 4;5380 break;5381 default:5382 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",5383 amdgpu_ip_version(adev, DCE_HWIP, 0));5384 return -EINVAL;5385 }5386 break;5387 }5388 5389 if (adev->mode_info.funcs == NULL)5390 adev->mode_info.funcs = &dm_display_funcs;5391 5392 /*5393 * Note: Do NOT change adev->audio_endpt_rreg and5394 * adev->audio_endpt_wreg because they are initialised in5395 * amdgpu_device_init()5396 */5397#if defined(CONFIG_DEBUG_KERNEL_DC)5398 device_create_file(5399 adev_to_drm(adev)->dev,5400 &dev_attr_s3_debug);5401#endif5402 adev->dc_enabled = true;5403 5404 return dm_init_microcode(adev);5405}5406 5407static bool modereset_required(struct drm_crtc_state *crtc_state)5408{5409 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);5410}5411 5412static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)5413{5414 drm_encoder_cleanup(encoder);5415 kfree(encoder);5416}5417 5418static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {5419 .destroy = amdgpu_dm_encoder_destroy,5420};5421 5422static int5423fill_plane_color_attributes(const struct drm_plane_state *plane_state,5424 const enum surface_pixel_format format,5425 enum dc_color_space *color_space)5426{5427 bool full_range;5428 5429 *color_space = COLOR_SPACE_SRGB;5430 5431 /* DRM color properties only affect non-RGB formats. */5432 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)5433 return 0;5434 5435 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);5436 5437 switch (plane_state->color_encoding) {5438 case DRM_COLOR_YCBCR_BT601:5439 if (full_range)5440 *color_space = COLOR_SPACE_YCBCR601;5441 else5442 *color_space = COLOR_SPACE_YCBCR601_LIMITED;5443 break;5444 5445 case DRM_COLOR_YCBCR_BT709:5446 if (full_range)5447 *color_space = COLOR_SPACE_YCBCR709;5448 else5449 *color_space = COLOR_SPACE_YCBCR709_LIMITED;5450 break;5451 5452 case DRM_COLOR_YCBCR_BT2020:5453 if (full_range)5454 *color_space = COLOR_SPACE_2020_YCBCR;5455 else5456 return -EINVAL;5457 break;5458 5459 default:5460 return -EINVAL;5461 }5462 5463 return 0;5464}5465 5466static int5467fill_dc_plane_info_and_addr(struct amdgpu_device *adev,5468 const struct drm_plane_state *plane_state,5469 const u64 tiling_flags,5470 struct dc_plane_info *plane_info,5471 struct dc_plane_address *address,5472 bool tmz_surface,5473 bool force_disable_dcc)5474{5475 const struct drm_framebuffer *fb = plane_state->fb;5476 const struct amdgpu_framebuffer *afb =5477 to_amdgpu_framebuffer(plane_state->fb);5478 int ret;5479 5480 memset(plane_info, 0, sizeof(*plane_info));5481 5482 switch (fb->format->format) {5483 case DRM_FORMAT_C8:5484 plane_info->format =5485 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;5486 break;5487 case DRM_FORMAT_RGB565:5488 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;5489 break;5490 case DRM_FORMAT_XRGB8888:5491 case DRM_FORMAT_ARGB8888:5492 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;5493 break;5494 case DRM_FORMAT_XRGB2101010:5495 case DRM_FORMAT_ARGB2101010:5496 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;5497 break;5498 case DRM_FORMAT_XBGR2101010:5499 case DRM_FORMAT_ABGR2101010:5500 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;5501 break;5502 case DRM_FORMAT_XBGR8888:5503 case DRM_FORMAT_ABGR8888:5504 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;5505 break;5506 case DRM_FORMAT_NV21:5507 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;5508 break;5509 case DRM_FORMAT_NV12:5510 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;5511 break;5512 case DRM_FORMAT_P010:5513 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;5514 break;5515 case DRM_FORMAT_XRGB16161616F:5516 case DRM_FORMAT_ARGB16161616F:5517 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;5518 break;5519 case DRM_FORMAT_XBGR16161616F:5520 case DRM_FORMAT_ABGR16161616F:5521 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;5522 break;5523 case DRM_FORMAT_XRGB16161616:5524 case DRM_FORMAT_ARGB16161616:5525 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;5526 break;5527 case DRM_FORMAT_XBGR16161616:5528 case DRM_FORMAT_ABGR16161616:5529 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;5530 break;5531 default:5532 DRM_ERROR(5533 "Unsupported screen format %p4cc\n",5534 &fb->format->format);5535 return -EINVAL;5536 }5537 5538 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {5539 case DRM_MODE_ROTATE_0:5540 plane_info->rotation = ROTATION_ANGLE_0;5541 break;5542 case DRM_MODE_ROTATE_90:5543 plane_info->rotation = ROTATION_ANGLE_90;5544 break;5545 case DRM_MODE_ROTATE_180:5546 plane_info->rotation = ROTATION_ANGLE_180;5547 break;5548 case DRM_MODE_ROTATE_270:5549 plane_info->rotation = ROTATION_ANGLE_270;5550 break;5551 default:5552 plane_info->rotation = ROTATION_ANGLE_0;5553 break;5554 }5555 5556 5557 plane_info->visible = true;5558 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;5559 5560 plane_info->layer_index = plane_state->normalized_zpos;5561 5562 ret = fill_plane_color_attributes(plane_state, plane_info->format,5563 &plane_info->color_space);5564 if (ret)5565 return ret;5566 5567 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,5568 plane_info->rotation, tiling_flags,5569 &plane_info->tiling_info,5570 &plane_info->plane_size,5571 &plane_info->dcc, address,5572 tmz_surface, force_disable_dcc);5573 if (ret)5574 return ret;5575 5576 amdgpu_dm_plane_fill_blending_from_plane_state(5577 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,5578 &plane_info->global_alpha, &plane_info->global_alpha_value);5579 5580 return 0;5581}5582 5583static int fill_dc_plane_attributes(struct amdgpu_device *adev,5584 struct dc_plane_state *dc_plane_state,5585 struct drm_plane_state *plane_state,5586 struct drm_crtc_state *crtc_state)5587{5588 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);5589 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;5590 struct dc_scaling_info scaling_info;5591 struct dc_plane_info plane_info;5592 int ret;5593 bool force_disable_dcc = false;5594 5595 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);5596 if (ret)5597 return ret;5598 5599 dc_plane_state->src_rect = scaling_info.src_rect;5600 dc_plane_state->dst_rect = scaling_info.dst_rect;5601 dc_plane_state->clip_rect = scaling_info.clip_rect;5602 dc_plane_state->scaling_quality = scaling_info.scaling_quality;5603 5604 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;5605 ret = fill_dc_plane_info_and_addr(adev, plane_state,5606 afb->tiling_flags,5607 &plane_info,5608 &dc_plane_state->address,5609 afb->tmz_surface,5610 force_disable_dcc);5611 if (ret)5612 return ret;5613 5614 dc_plane_state->format = plane_info.format;5615 dc_plane_state->color_space = plane_info.color_space;5616 dc_plane_state->format = plane_info.format;5617 dc_plane_state->plane_size = plane_info.plane_size;5618 dc_plane_state->rotation = plane_info.rotation;5619 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;5620 dc_plane_state->stereo_format = plane_info.stereo_format;5621 dc_plane_state->tiling_info = plane_info.tiling_info;5622 dc_plane_state->visible = plane_info.visible;5623 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;5624 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;5625 dc_plane_state->global_alpha = plane_info.global_alpha;5626 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;5627 dc_plane_state->dcc = plane_info.dcc;5628 dc_plane_state->layer_index = plane_info.layer_index;5629 dc_plane_state->flip_int_enabled = true;5630 5631 /*5632 * Always set input transfer function, since plane state is refreshed5633 * every time.5634 */5635 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state,5636 plane_state,5637 dc_plane_state);5638 if (ret)5639 return ret;5640 5641 return 0;5642}5643 5644static inline void fill_dc_dirty_rect(struct drm_plane *plane,5645 struct rect *dirty_rect, int32_t x,5646 s32 y, s32 width, s32 height,5647 int *i, bool ffu)5648{5649 WARN_ON(*i >= DC_MAX_DIRTY_RECTS);5650 5651 dirty_rect->x = x;5652 dirty_rect->y = y;5653 dirty_rect->width = width;5654 dirty_rect->height = height;5655 5656 if (ffu)5657 drm_dbg(plane->dev,5658 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",5659 plane->base.id, width, height);5660 else5661 drm_dbg(plane->dev,5662 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",5663 plane->base.id, x, y, width, height);5664 5665 (*i)++;5666}5667 5668/**5669 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates5670 *5671 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP5672 * remote fb5673 * @old_plane_state: Old state of @plane5674 * @new_plane_state: New state of @plane5675 * @crtc_state: New state of CRTC connected to the @plane5676 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects5677 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled.5678 * If PSR SU is enabled and damage clips are available, only the regions of the screen5679 * that have changed will be updated. If PSR SU is not enabled,5680 * or if damage clips are not available, the entire screen will be updated.5681 * @dirty_regions_changed: dirty regions changed5682 *5683 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions5684 * (referred to as "damage clips" in DRM nomenclature) that require updating on5685 * the eDP remote buffer. The responsibility of specifying the dirty regions is5686 * amdgpu_dm's.5687 *5688 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the5689 * plane with regions that require flushing to the eDP remote buffer. In5690 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -5691 * implicitly provide damage clips without any client support via the plane5692 * bounds.5693 */5694static void fill_dc_dirty_rects(struct drm_plane *plane,5695 struct drm_plane_state *old_plane_state,5696 struct drm_plane_state *new_plane_state,5697 struct drm_crtc_state *crtc_state,5698 struct dc_flip_addrs *flip_addrs,5699 bool is_psr_su,5700 bool *dirty_regions_changed)5701{5702 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);5703 struct rect *dirty_rects = flip_addrs->dirty_rects;5704 u32 num_clips;5705 struct drm_mode_rect *clips;5706 bool bb_changed;5707 bool fb_changed;5708 u32 i = 0;5709 *dirty_regions_changed = false;5710 5711 /*5712 * Cursor plane has it's own dirty rect update interface. See5713 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data5714 */5715 if (plane->type == DRM_PLANE_TYPE_CURSOR)5716 return;5717 5718 if (new_plane_state->rotation != DRM_MODE_ROTATE_0)5719 goto ffu;5720 5721 num_clips = drm_plane_get_damage_clips_count(new_plane_state);5722 clips = drm_plane_get_damage_clips(new_plane_state);5723 5724 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 &&5725 is_psr_su)))5726 goto ffu;5727 5728 if (!dm_crtc_state->mpo_requested) {5729 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)5730 goto ffu;5731 5732 for (; flip_addrs->dirty_rect_count < num_clips; clips++)5733 fill_dc_dirty_rect(new_plane_state->plane,5734 &dirty_rects[flip_addrs->dirty_rect_count],5735 clips->x1, clips->y1,5736 clips->x2 - clips->x1, clips->y2 - clips->y1,5737 &flip_addrs->dirty_rect_count,5738 false);5739 return;5740 }5741 5742 /*5743 * MPO is requested. Add entire plane bounding box to dirty rects if5744 * flipped to or damaged.5745 *5746 * If plane is moved or resized, also add old bounding box to dirty5747 * rects.5748 */5749 fb_changed = old_plane_state->fb->base.id !=5750 new_plane_state->fb->base.id;5751 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||5752 old_plane_state->crtc_y != new_plane_state->crtc_y ||5753 old_plane_state->crtc_w != new_plane_state->crtc_w ||5754 old_plane_state->crtc_h != new_plane_state->crtc_h);5755 5756 drm_dbg(plane->dev,5757 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",5758 new_plane_state->plane->base.id,5759 bb_changed, fb_changed, num_clips);5760 5761 *dirty_regions_changed = bb_changed;5762 5763 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)5764 goto ffu;5765 5766 if (bb_changed) {5767 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],5768 new_plane_state->crtc_x,5769 new_plane_state->crtc_y,5770 new_plane_state->crtc_w,5771 new_plane_state->crtc_h, &i, false);5772 5773 /* Add old plane bounding-box if plane is moved or resized */5774 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],5775 old_plane_state->crtc_x,5776 old_plane_state->crtc_y,5777 old_plane_state->crtc_w,5778 old_plane_state->crtc_h, &i, false);5779 }5780 5781 if (num_clips) {5782 for (; i < num_clips; clips++)5783 fill_dc_dirty_rect(new_plane_state->plane,5784 &dirty_rects[i], clips->x1,5785 clips->y1, clips->x2 - clips->x1,5786 clips->y2 - clips->y1, &i, false);5787 } else if (fb_changed && !bb_changed) {5788 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],5789 new_plane_state->crtc_x,5790 new_plane_state->crtc_y,5791 new_plane_state->crtc_w,5792 new_plane_state->crtc_h, &i, false);5793 }5794 5795 flip_addrs->dirty_rect_count = i;5796 return;5797 5798ffu:5799 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,5800 dm_crtc_state->base.mode.crtc_hdisplay,5801 dm_crtc_state->base.mode.crtc_vdisplay,5802 &flip_addrs->dirty_rect_count, true);5803}5804 5805static void update_stream_scaling_settings(const struct drm_display_mode *mode,5806 const struct dm_connector_state *dm_state,5807 struct dc_stream_state *stream)5808{5809 enum amdgpu_rmx_type rmx_type;5810 5811 struct rect src = { 0 }; /* viewport in composition space*/5812 struct rect dst = { 0 }; /* stream addressable area */5813 5814 /* no mode. nothing to be done */5815 if (!mode)5816 return;5817 5818 /* Full screen scaling by default */5819 src.width = mode->hdisplay;5820 src.height = mode->vdisplay;5821 dst.width = stream->timing.h_addressable;5822 dst.height = stream->timing.v_addressable;5823 5824 if (dm_state) {5825 rmx_type = dm_state->scaling;5826 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {5827 if (src.width * dst.height <5828 src.height * dst.width) {5829 /* height needs less upscaling/more downscaling */5830 dst.width = src.width *5831 dst.height / src.height;5832 } else {5833 /* width needs less upscaling/more downscaling */5834 dst.height = src.height *5835 dst.width / src.width;5836 }5837 } else if (rmx_type == RMX_CENTER) {5838 dst = src;5839 }5840 5841 dst.x = (stream->timing.h_addressable - dst.width) / 2;5842 dst.y = (stream->timing.v_addressable - dst.height) / 2;5843 5844 if (dm_state->underscan_enable) {5845 dst.x += dm_state->underscan_hborder / 2;5846 dst.y += dm_state->underscan_vborder / 2;5847 dst.width -= dm_state->underscan_hborder;5848 dst.height -= dm_state->underscan_vborder;5849 }5850 }5851 5852 stream->src = src;5853 stream->dst = dst;5854 5855 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",5856 dst.x, dst.y, dst.width, dst.height);5857 5858}5859 5860static enum dc_color_depth5861convert_color_depth_from_display_info(const struct drm_connector *connector,5862 bool is_y420, int requested_bpc)5863{5864 u8 bpc;5865 5866 if (is_y420) {5867 bpc = 8;5868 5869 /* Cap display bpc based on HDMI 2.0 HF-VSDB */5870 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)5871 bpc = 16;5872 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)5873 bpc = 12;5874 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)5875 bpc = 10;5876 } else {5877 bpc = (uint8_t)connector->display_info.bpc;5878 /* Assume 8 bpc by default if no bpc is specified. */5879 bpc = bpc ? bpc : 8;5880 }5881 5882 if (requested_bpc > 0) {5883 /*5884 * Cap display bpc based on the user requested value.5885 *5886 * The value for state->max_bpc may not correctly updated5887 * depending on when the connector gets added to the state5888 * or if this was called outside of atomic check, so it5889 * can't be used directly.5890 */5891 bpc = min_t(u8, bpc, requested_bpc);5892 5893 /* Round down to the nearest even number. */5894 bpc = bpc - (bpc & 1);5895 }5896 5897 switch (bpc) {5898 case 0:5899 /*5900 * Temporary Work around, DRM doesn't parse color depth for5901 * EDID revision before 1.45902 * TODO: Fix edid parsing5903 */5904 return COLOR_DEPTH_888;5905 case 6:5906 return COLOR_DEPTH_666;5907 case 8:5908 return COLOR_DEPTH_888;5909 case 10:5910 return COLOR_DEPTH_101010;5911 case 12:5912 return COLOR_DEPTH_121212;5913 case 14:5914 return COLOR_DEPTH_141414;5915 case 16:5916 return COLOR_DEPTH_161616;5917 default:5918 return COLOR_DEPTH_UNDEFINED;5919 }5920}5921 5922static enum dc_aspect_ratio5923get_aspect_ratio(const struct drm_display_mode *mode_in)5924{5925 /* 1-1 mapping, since both enums follow the HDMI spec. */5926 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;5927}5928 5929static enum dc_color_space5930get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,5931 const struct drm_connector_state *connector_state)5932{5933 enum dc_color_space color_space = COLOR_SPACE_SRGB;5934 5935 switch (connector_state->colorspace) {5936 case DRM_MODE_COLORIMETRY_BT601_YCC:5937 if (dc_crtc_timing->flags.Y_ONLY)5938 color_space = COLOR_SPACE_YCBCR601_LIMITED;5939 else5940 color_space = COLOR_SPACE_YCBCR601;5941 break;5942 case DRM_MODE_COLORIMETRY_BT709_YCC:5943 if (dc_crtc_timing->flags.Y_ONLY)5944 color_space = COLOR_SPACE_YCBCR709_LIMITED;5945 else5946 color_space = COLOR_SPACE_YCBCR709;5947 break;5948 case DRM_MODE_COLORIMETRY_OPRGB:5949 color_space = COLOR_SPACE_ADOBERGB;5950 break;5951 case DRM_MODE_COLORIMETRY_BT2020_RGB:5952 case DRM_MODE_COLORIMETRY_BT2020_YCC:5953 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)5954 color_space = COLOR_SPACE_2020_RGB_FULLRANGE;5955 else5956 color_space = COLOR_SPACE_2020_YCBCR;5957 break;5958 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU6015959 default:5960 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {5961 color_space = COLOR_SPACE_SRGB;5962 /*5963 * 27030khz is the separation point between HDTV and SDTV5964 * according to HDMI spec, we use YCbCr709 and YCbCr6015965 * respectively5966 */5967 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {5968 if (dc_crtc_timing->flags.Y_ONLY)5969 color_space =5970 COLOR_SPACE_YCBCR709_LIMITED;5971 else5972 color_space = COLOR_SPACE_YCBCR709;5973 } else {5974 if (dc_crtc_timing->flags.Y_ONLY)5975 color_space =5976 COLOR_SPACE_YCBCR601_LIMITED;5977 else5978 color_space = COLOR_SPACE_YCBCR601;5979 }5980 break;5981 }5982 5983 return color_space;5984}5985 5986static enum display_content_type5987get_output_content_type(const struct drm_connector_state *connector_state)5988{5989 switch (connector_state->content_type) {5990 default:5991 case DRM_MODE_CONTENT_TYPE_NO_DATA:5992 return DISPLAY_CONTENT_TYPE_NO_DATA;5993 case DRM_MODE_CONTENT_TYPE_GRAPHICS:5994 return DISPLAY_CONTENT_TYPE_GRAPHICS;5995 case DRM_MODE_CONTENT_TYPE_PHOTO:5996 return DISPLAY_CONTENT_TYPE_PHOTO;5997 case DRM_MODE_CONTENT_TYPE_CINEMA:5998 return DISPLAY_CONTENT_TYPE_CINEMA;5999 case DRM_MODE_CONTENT_TYPE_GAME:6000 return DISPLAY_CONTENT_TYPE_GAME;6001 }6002}6003 6004static bool adjust_colour_depth_from_display_info(6005 struct dc_crtc_timing *timing_out,6006 const struct drm_display_info *info)6007{6008 enum dc_color_depth depth = timing_out->display_color_depth;6009 int normalized_clk;6010 6011 do {6012 normalized_clk = timing_out->pix_clk_100hz / 10;6013 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */6014 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)6015 normalized_clk /= 2;6016 /* Adjusting pix clock following on HDMI spec based on colour depth */6017 switch (depth) {6018 case COLOR_DEPTH_888:6019 break;6020 case COLOR_DEPTH_101010:6021 normalized_clk = (normalized_clk * 30) / 24;6022 break;6023 case COLOR_DEPTH_121212:6024 normalized_clk = (normalized_clk * 36) / 24;6025 break;6026 case COLOR_DEPTH_161616:6027 normalized_clk = (normalized_clk * 48) / 24;6028 break;6029 default:6030 /* The above depths are the only ones valid for HDMI. */6031 return false;6032 }6033 if (normalized_clk <= info->max_tmds_clock) {6034 timing_out->display_color_depth = depth;6035 return true;6036 }6037 } while (--depth > COLOR_DEPTH_666);6038 return false;6039}6040 6041static void fill_stream_properties_from_drm_display_mode(6042 struct dc_stream_state *stream,6043 const struct drm_display_mode *mode_in,6044 const struct drm_connector *connector,6045 const struct drm_connector_state *connector_state,6046 const struct dc_stream_state *old_stream,6047 int requested_bpc)6048{6049 struct dc_crtc_timing *timing_out = &stream->timing;6050 const struct drm_display_info *info = &connector->display_info;6051 struct amdgpu_dm_connector *aconnector = NULL;6052 struct hdmi_vendor_infoframe hv_frame;6053 struct hdmi_avi_infoframe avi_frame;6054 6055 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)6056 aconnector = to_amdgpu_dm_connector(connector);6057 6058 memset(&hv_frame, 0, sizeof(hv_frame));6059 memset(&avi_frame, 0, sizeof(avi_frame));6060 6061 timing_out->h_border_left = 0;6062 timing_out->h_border_right = 0;6063 timing_out->v_border_top = 0;6064 timing_out->v_border_bottom = 0;6065 /* TODO: un-hardcode */6066 if (drm_mode_is_420_only(info, mode_in)6067 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)6068 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;6069 else if (drm_mode_is_420_also(info, mode_in)6070 && aconnector6071 && aconnector->force_yuv420_output)6072 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;6073 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)6074 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)6075 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;6076 else6077 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;6078 6079 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;6080 timing_out->display_color_depth = convert_color_depth_from_display_info(6081 connector,6082 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),6083 requested_bpc);6084 timing_out->scan_type = SCANNING_TYPE_NODATA;6085 timing_out->hdmi_vic = 0;6086 6087 if (old_stream) {6088 timing_out->vic = old_stream->timing.vic;6089 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;6090 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;6091 } else {6092 timing_out->vic = drm_match_cea_mode(mode_in);6093 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)6094 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;6095 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)6096 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;6097 }6098 6099 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {6100 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);6101 timing_out->vic = avi_frame.video_code;6102 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);6103 timing_out->hdmi_vic = hv_frame.vic;6104 }6105 6106 if (aconnector && is_freesync_video_mode(mode_in, aconnector)) {6107 timing_out->h_addressable = mode_in->hdisplay;6108 timing_out->h_total = mode_in->htotal;6109 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;6110 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;6111 timing_out->v_total = mode_in->vtotal;6112 timing_out->v_addressable = mode_in->vdisplay;6113 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;6114 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;6115 timing_out->pix_clk_100hz = mode_in->clock * 10;6116 } else {6117 timing_out->h_addressable = mode_in->crtc_hdisplay;6118 timing_out->h_total = mode_in->crtc_htotal;6119 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;6120 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;6121 timing_out->v_total = mode_in->crtc_vtotal;6122 timing_out->v_addressable = mode_in->crtc_vdisplay;6123 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;6124 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;6125 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;6126 }6127 6128 timing_out->aspect_ratio = get_aspect_ratio(mode_in);6129 6130 stream->out_transfer_func.type = TF_TYPE_PREDEFINED;6131 stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB;6132 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {6133 if (!adjust_colour_depth_from_display_info(timing_out, info) &&6134 drm_mode_is_420_also(info, mode_in) &&6135 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {6136 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;6137 adjust_colour_depth_from_display_info(timing_out, info);6138 }6139 }6140 6141 stream->output_color_space = get_output_color_space(timing_out, connector_state);6142 stream->content_type = get_output_content_type(connector_state);6143}6144 6145static void fill_audio_info(struct audio_info *audio_info,6146 const struct drm_connector *drm_connector,6147 const struct dc_sink *dc_sink)6148{6149 int i = 0;6150 int cea_revision = 0;6151 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;6152 6153 audio_info->manufacture_id = edid_caps->manufacturer_id;6154 audio_info->product_id = edid_caps->product_id;6155 6156 cea_revision = drm_connector->display_info.cea_rev;6157 6158 strscpy(audio_info->display_name,6159 edid_caps->display_name,6160 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);6161 6162 if (cea_revision >= 3) {6163 audio_info->mode_count = edid_caps->audio_mode_count;6164 6165 for (i = 0; i < audio_info->mode_count; ++i) {6166 audio_info->modes[i].format_code =6167 (enum audio_format_code)6168 (edid_caps->audio_modes[i].format_code);6169 audio_info->modes[i].channel_count =6170 edid_caps->audio_modes[i].channel_count;6171 audio_info->modes[i].sample_rates.all =6172 edid_caps->audio_modes[i].sample_rate;6173 audio_info->modes[i].sample_size =6174 edid_caps->audio_modes[i].sample_size;6175 }6176 }6177 6178 audio_info->flags.all = edid_caps->speaker_flags;6179 6180 /* TODO: We only check for the progressive mode, check for interlace mode too */6181 if (drm_connector->latency_present[0]) {6182 audio_info->video_latency = drm_connector->video_latency[0];6183 audio_info->audio_latency = drm_connector->audio_latency[0];6184 }6185 6186 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */6187 6188}6189 6190static void6191copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,6192 struct drm_display_mode *dst_mode)6193{6194 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;6195 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;6196 dst_mode->crtc_clock = src_mode->crtc_clock;6197 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;6198 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;6199 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;6200 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;6201 dst_mode->crtc_htotal = src_mode->crtc_htotal;6202 dst_mode->crtc_hskew = src_mode->crtc_hskew;6203 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;6204 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;6205 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;6206 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;6207 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;6208}6209 6210static void6211decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,6212 const struct drm_display_mode *native_mode,6213 bool scale_enabled)6214{6215 if (scale_enabled) {6216 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);6217 } else if (native_mode->clock == drm_mode->clock &&6218 native_mode->htotal == drm_mode->htotal &&6219 native_mode->vtotal == drm_mode->vtotal) {6220 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);6221 } else {6222 /* no scaling nor amdgpu inserted, no need to patch */6223 }6224}6225 6226static struct dc_sink *6227create_fake_sink(struct dc_link *link)6228{6229 struct dc_sink_init_data sink_init_data = { 0 };6230 struct dc_sink *sink = NULL;6231 6232 sink_init_data.link = link;6233 sink_init_data.sink_signal = link->connector_signal;6234 6235 sink = dc_sink_create(&sink_init_data);6236 if (!sink) {6237 DRM_ERROR("Failed to create sink!\n");6238 return NULL;6239 }6240 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;6241 6242 return sink;6243}6244 6245static void set_multisync_trigger_params(6246 struct dc_stream_state *stream)6247{6248 struct dc_stream_state *master = NULL;6249 6250 if (stream->triggered_crtc_reset.enabled) {6251 master = stream->triggered_crtc_reset.event_source;6252 stream->triggered_crtc_reset.event =6253 master->timing.flags.VSYNC_POSITIVE_POLARITY ?6254 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;6255 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;6256 }6257}6258 6259static void set_master_stream(struct dc_stream_state *stream_set[],6260 int stream_count)6261{6262 int j, highest_rfr = 0, master_stream = 0;6263 6264 for (j = 0; j < stream_count; j++) {6265 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {6266 int refresh_rate = 0;6267 6268 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/6269 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);6270 if (refresh_rate > highest_rfr) {6271 highest_rfr = refresh_rate;6272 master_stream = j;6273 }6274 }6275 }6276 for (j = 0; j < stream_count; j++) {6277 if (stream_set[j])6278 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];6279 }6280}6281 6282static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)6283{6284 int i = 0;6285 struct dc_stream_state *stream;6286 6287 if (context->stream_count < 2)6288 return;6289 for (i = 0; i < context->stream_count ; i++) {6290 if (!context->streams[i])6291 continue;6292 /*6293 * TODO: add a function to read AMD VSDB bits and set6294 * crtc_sync_master.multi_sync_enabled flag6295 * For now it's set to false6296 */6297 }6298 6299 set_master_stream(context->streams, context->stream_count);6300 6301 for (i = 0; i < context->stream_count ; i++) {6302 stream = context->streams[i];6303 6304 if (!stream)6305 continue;6306 6307 set_multisync_trigger_params(stream);6308 }6309}6310 6311/**6312 * DOC: FreeSync Video6313 *6314 * When a userspace application wants to play a video, the content follows a6315 * standard format definition that usually specifies the FPS for that format.6316 * The below list illustrates some video format and the expected FPS,6317 * respectively:6318 *6319 * - TV/NTSC (23.976 FPS)6320 * - Cinema (24 FPS)6321 * - TV/PAL (25 FPS)6322 * - TV/NTSC (29.97 FPS)6323 * - TV/NTSC (30 FPS)6324 * - Cinema HFR (48 FPS)6325 * - TV/PAL (50 FPS)6326 * - Commonly used (60 FPS)6327 * - Multiples of 24 (48,72,96 FPS)6328 *6329 * The list of standards video format is not huge and can be added to the6330 * connector modeset list beforehand. With that, userspace can leverage6331 * FreeSync to extends the front porch in order to attain the target refresh6332 * rate. Such a switch will happen seamlessly, without screen blanking or6333 * reprogramming of the output in any other way. If the userspace requests a6334 * modesetting change compatible with FreeSync modes that only differ in the6335 * refresh rate, DC will skip the full update and avoid blink during the6336 * transition. For example, the video player can change the modesetting from6337 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without6338 * causing any display blink. This same concept can be applied to a mode6339 * setting change.6340 */6341static struct drm_display_mode *6342get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,6343 bool use_probed_modes)6344{6345 struct drm_display_mode *m, *m_pref = NULL;6346 u16 current_refresh, highest_refresh;6347 struct list_head *list_head = use_probed_modes ?6348 &aconnector->base.probed_modes :6349 &aconnector->base.modes;6350 6351 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)6352 return NULL;6353 6354 if (aconnector->freesync_vid_base.clock != 0)6355 return &aconnector->freesync_vid_base;6356 6357 /* Find the preferred mode */6358 list_for_each_entry(m, list_head, head) {6359 if (m->type & DRM_MODE_TYPE_PREFERRED) {6360 m_pref = m;6361 break;6362 }6363 }6364 6365 if (!m_pref) {6366 /* Probably an EDID with no preferred mode. Fallback to first entry */6367 m_pref = list_first_entry_or_null(6368 &aconnector->base.modes, struct drm_display_mode, head);6369 if (!m_pref) {6370 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");6371 return NULL;6372 }6373 }6374 6375 highest_refresh = drm_mode_vrefresh(m_pref);6376 6377 /*6378 * Find the mode with highest refresh rate with same resolution.6379 * For some monitors, preferred mode is not the mode with highest6380 * supported refresh rate.6381 */6382 list_for_each_entry(m, list_head, head) {6383 current_refresh = drm_mode_vrefresh(m);6384 6385 if (m->hdisplay == m_pref->hdisplay &&6386 m->vdisplay == m_pref->vdisplay &&6387 highest_refresh < current_refresh) {6388 highest_refresh = current_refresh;6389 m_pref = m;6390 }6391 }6392 6393 drm_mode_copy(&aconnector->freesync_vid_base, m_pref);6394 return m_pref;6395}6396 6397static bool is_freesync_video_mode(const struct drm_display_mode *mode,6398 struct amdgpu_dm_connector *aconnector)6399{6400 struct drm_display_mode *high_mode;6401 int timing_diff;6402 6403 high_mode = get_highest_refresh_rate_mode(aconnector, false);6404 if (!high_mode || !mode)6405 return false;6406 6407 timing_diff = high_mode->vtotal - mode->vtotal;6408 6409 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||6410 high_mode->hdisplay != mode->hdisplay ||6411 high_mode->vdisplay != mode->vdisplay ||6412 high_mode->hsync_start != mode->hsync_start ||6413 high_mode->hsync_end != mode->hsync_end ||6414 high_mode->htotal != mode->htotal ||6415 high_mode->hskew != mode->hskew ||6416 high_mode->vscan != mode->vscan ||6417 high_mode->vsync_start - mode->vsync_start != timing_diff ||6418 high_mode->vsync_end - mode->vsync_end != timing_diff)6419 return false;6420 else6421 return true;6422}6423 6424#if defined(CONFIG_DRM_AMD_DC_FP)6425static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,6426 struct dc_sink *sink, struct dc_stream_state *stream,6427 struct dsc_dec_dpcd_caps *dsc_caps)6428{6429 stream->timing.flags.DSC = 0;6430 dsc_caps->is_dsc_supported = false;6431 6432 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||6433 sink->sink_signal == SIGNAL_TYPE_EDP)) {6434 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||6435 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)6436 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,6437 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,6438 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,6439 dsc_caps);6440 }6441}6442 6443static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,6444 struct dc_sink *sink, struct dc_stream_state *stream,6445 struct dsc_dec_dpcd_caps *dsc_caps,6446 uint32_t max_dsc_target_bpp_limit_override)6447{6448 const struct dc_link_settings *verified_link_cap = NULL;6449 u32 link_bw_in_kbps;6450 u32 edp_min_bpp_x16, edp_max_bpp_x16;6451 struct dc *dc = sink->ctx->dc;6452 struct dc_dsc_bw_range bw_range = {0};6453 struct dc_dsc_config dsc_cfg = {0};6454 struct dc_dsc_config_options dsc_options = {0};6455 6456 dc_dsc_get_default_config_option(dc, &dsc_options);6457 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;6458 6459 verified_link_cap = dc_link_get_link_cap(stream->link);6460 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);6461 edp_min_bpp_x16 = 8 * 16;6462 edp_max_bpp_x16 = 8 * 16;6463 6464 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)6465 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;6466 6467 if (edp_max_bpp_x16 < edp_min_bpp_x16)6468 edp_min_bpp_x16 = edp_max_bpp_x16;6469 6470 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],6471 dc->debug.dsc_min_slice_height_override,6472 edp_min_bpp_x16, edp_max_bpp_x16,6473 dsc_caps,6474 &stream->timing,6475 dc_link_get_highest_encoding_format(aconnector->dc_link),6476 &bw_range)) {6477 6478 if (bw_range.max_kbps < link_bw_in_kbps) {6479 if (dc_dsc_compute_config(dc->res_pool->dscs[0],6480 dsc_caps,6481 &dsc_options,6482 0,6483 &stream->timing,6484 dc_link_get_highest_encoding_format(aconnector->dc_link),6485 &dsc_cfg)) {6486 stream->timing.dsc_cfg = dsc_cfg;6487 stream->timing.flags.DSC = 1;6488 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;6489 }6490 return;6491 }6492 }6493 6494 if (dc_dsc_compute_config(dc->res_pool->dscs[0],6495 dsc_caps,6496 &dsc_options,6497 link_bw_in_kbps,6498 &stream->timing,6499 dc_link_get_highest_encoding_format(aconnector->dc_link),6500 &dsc_cfg)) {6501 stream->timing.dsc_cfg = dsc_cfg;6502 stream->timing.flags.DSC = 1;6503 }6504}6505 6506static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,6507 struct dc_sink *sink, struct dc_stream_state *stream,6508 struct dsc_dec_dpcd_caps *dsc_caps)6509{6510 struct drm_connector *drm_connector = &aconnector->base;6511 u32 link_bandwidth_kbps;6512 struct dc *dc = sink->ctx->dc;6513 u32 max_supported_bw_in_kbps, timing_bw_in_kbps;6514 u32 dsc_max_supported_bw_in_kbps;6515 u32 max_dsc_target_bpp_limit_override =6516 drm_connector->display_info.max_dsc_bpp;6517 struct dc_dsc_config_options dsc_options = {0};6518 6519 dc_dsc_get_default_config_option(dc, &dsc_options);6520 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;6521 6522 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,6523 dc_link_get_link_cap(aconnector->dc_link));6524 6525 /* Set DSC policy according to dsc_clock_en */6526 dc_dsc_policy_set_enable_dsc_when_not_needed(6527 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);6528 6529 if (sink->sink_signal == SIGNAL_TYPE_EDP &&6530 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&6531 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {6532 6533 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);6534 6535 } else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {6536 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {6537 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],6538 dsc_caps,6539 &dsc_options,6540 link_bandwidth_kbps,6541 &stream->timing,6542 dc_link_get_highest_encoding_format(aconnector->dc_link),6543 &stream->timing.dsc_cfg)) {6544 stream->timing.flags.DSC = 1;6545 DRM_DEBUG_DRIVER("%s: SST_DSC [%s] DSC is selected from SST RX\n",6546 __func__, drm_connector->name);6547 }6548 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {6549 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,6550 dc_link_get_highest_encoding_format(aconnector->dc_link));6551 max_supported_bw_in_kbps = link_bandwidth_kbps;6552 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;6553 6554 if (timing_bw_in_kbps > max_supported_bw_in_kbps &&6555 max_supported_bw_in_kbps > 0 &&6556 dsc_max_supported_bw_in_kbps > 0)6557 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],6558 dsc_caps,6559 &dsc_options,6560 dsc_max_supported_bw_in_kbps,6561 &stream->timing,6562 dc_link_get_highest_encoding_format(aconnector->dc_link),6563 &stream->timing.dsc_cfg)) {6564 stream->timing.flags.DSC = 1;6565 DRM_DEBUG_DRIVER("%s: SST_DSC [%s] DSC is selected from DP-HDMI PCON\n",6566 __func__, drm_connector->name);6567 }6568 }6569 }6570 6571 /* Overwrite the stream flag if DSC is enabled through debugfs */6572 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)6573 stream->timing.flags.DSC = 1;6574 6575 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)6576 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;6577 6578 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)6579 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;6580 6581 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)6582 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;6583}6584#endif6585 6586static struct dc_stream_state *6587create_stream_for_sink(struct drm_connector *connector,6588 const struct drm_display_mode *drm_mode,6589 const struct dm_connector_state *dm_state,6590 const struct dc_stream_state *old_stream,6591 int requested_bpc)6592{6593 struct amdgpu_dm_connector *aconnector = NULL;6594 struct drm_display_mode *preferred_mode = NULL;6595 const struct drm_connector_state *con_state = &dm_state->base;6596 struct dc_stream_state *stream = NULL;6597 struct drm_display_mode mode;6598 struct drm_display_mode saved_mode;6599 struct drm_display_mode *freesync_mode = NULL;6600 bool native_mode_found = false;6601 bool recalculate_timing = false;6602 bool scale = dm_state->scaling != RMX_OFF;6603 int mode_refresh;6604 int preferred_refresh = 0;6605 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;6606#if defined(CONFIG_DRM_AMD_DC_FP)6607 struct dsc_dec_dpcd_caps dsc_caps;6608#endif6609 struct dc_link *link = NULL;6610 struct dc_sink *sink = NULL;6611 6612 drm_mode_init(&mode, drm_mode);6613 memset(&saved_mode, 0, sizeof(saved_mode));6614 6615 if (connector == NULL) {6616 DRM_ERROR("connector is NULL!\n");6617 return stream;6618 }6619 6620 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) {6621 aconnector = NULL;6622 aconnector = to_amdgpu_dm_connector(connector);6623 link = aconnector->dc_link;6624 } else {6625 struct drm_writeback_connector *wbcon = NULL;6626 struct amdgpu_dm_wb_connector *dm_wbcon = NULL;6627 6628 wbcon = drm_connector_to_writeback(connector);6629 dm_wbcon = to_amdgpu_dm_wb_connector(wbcon);6630 link = dm_wbcon->link;6631 }6632 6633 if (!aconnector || !aconnector->dc_sink) {6634 sink = create_fake_sink(link);6635 if (!sink)6636 return stream;6637 6638 } else {6639 sink = aconnector->dc_sink;6640 dc_sink_retain(sink);6641 }6642 6643 stream = dc_create_stream_for_sink(sink);6644 6645 if (stream == NULL) {6646 DRM_ERROR("Failed to create stream for sink!\n");6647 goto finish;6648 }6649 6650 /* We leave this NULL for writeback connectors */6651 stream->dm_stream_context = aconnector;6652 6653 stream->timing.flags.LTE_340MCSC_SCRAMBLE =6654 connector->display_info.hdmi.scdc.scrambling.low_rates;6655 6656 list_for_each_entry(preferred_mode, &connector->modes, head) {6657 /* Search for preferred mode */6658 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {6659 native_mode_found = true;6660 break;6661 }6662 }6663 if (!native_mode_found)6664 preferred_mode = list_first_entry_or_null(6665 &connector->modes,6666 struct drm_display_mode,6667 head);6668 6669 mode_refresh = drm_mode_vrefresh(&mode);6670 6671 if (preferred_mode == NULL) {6672 /*6673 * This may not be an error, the use case is when we have no6674 * usermode calls to reset and set mode upon hotplug. In this6675 * case, we call set mode ourselves to restore the previous mode6676 * and the modelist may not be filled in time.6677 */6678 DRM_DEBUG_DRIVER("No preferred mode found\n");6679 } else if (aconnector) {6680 recalculate_timing = amdgpu_freesync_vid_mode &&6681 is_freesync_video_mode(&mode, aconnector);6682 if (recalculate_timing) {6683 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);6684 drm_mode_copy(&saved_mode, &mode);6685 saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio;6686 drm_mode_copy(&mode, freesync_mode);6687 mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio;6688 } else {6689 decide_crtc_timing_for_drm_display_mode(6690 &mode, preferred_mode, scale);6691 6692 preferred_refresh = drm_mode_vrefresh(preferred_mode);6693 }6694 }6695 6696 if (recalculate_timing)6697 drm_mode_set_crtcinfo(&saved_mode, 0);6698 6699 /*6700 * If scaling is enabled and refresh rate didn't change6701 * we copy the vic and polarities of the old timings6702 */6703 if (!scale || mode_refresh != preferred_refresh)6704 fill_stream_properties_from_drm_display_mode(6705 stream, &mode, connector, con_state, NULL,6706 requested_bpc);6707 else6708 fill_stream_properties_from_drm_display_mode(6709 stream, &mode, connector, con_state, old_stream,6710 requested_bpc);6711 6712 /* The rest isn't needed for writeback connectors */6713 if (!aconnector)6714 goto finish;6715 6716 if (aconnector->timing_changed) {6717 drm_dbg(aconnector->base.dev,6718 "overriding timing for automated test, bpc %d, changing to %d\n",6719 stream->timing.display_color_depth,6720 aconnector->timing_requested->display_color_depth);6721 stream->timing = *aconnector->timing_requested;6722 }6723 6724#if defined(CONFIG_DRM_AMD_DC_FP)6725 /* SST DSC determination policy */6726 update_dsc_caps(aconnector, sink, stream, &dsc_caps);6727 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)6728 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);6729#endif6730 6731 update_stream_scaling_settings(&mode, dm_state, stream);6732 6733 fill_audio_info(6734 &stream->audio_info,6735 connector,6736 sink);6737 6738 update_stream_signal(stream, sink);6739 6740 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)6741 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);6742 6743 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||6744 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||6745 stream->signal == SIGNAL_TYPE_EDP) {6746 const struct dc_edid_caps *edid_caps;6747 unsigned int disable_colorimetry = 0;6748 6749 if (aconnector->dc_sink) {6750 edid_caps = &aconnector->dc_sink->edid_caps;6751 disable_colorimetry = edid_caps->panel_patch.disable_colorimetry;6752 }6753 6754 //6755 // should decide stream support vsc sdp colorimetry capability6756 // before building vsc info packet6757 //6758 stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 &&6759 stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&6760 !disable_colorimetry;6761 6762 if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22)6763 tf = TRANSFER_FUNC_GAMMA_22;6764 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);6765 aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;6766 6767 }6768finish:6769 dc_sink_release(sink);6770 6771 return stream;6772}6773 6774static enum drm_connector_status6775amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)6776{6777 bool connected;6778 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);6779 6780 /*6781 * Notes:6782 * 1. This interface is NOT called in context of HPD irq.6783 * 2. This interface *is called* in context of user-mode ioctl. Which6784 * makes it a bad place for *any* MST-related activity.6785 */6786 6787 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&6788 !aconnector->fake_enable)6789 connected = (aconnector->dc_sink != NULL);6790 else6791 connected = (aconnector->base.force == DRM_FORCE_ON ||6792 aconnector->base.force == DRM_FORCE_ON_DIGITAL);6793 6794 update_subconnector_property(aconnector);6795 6796 return (connected ? connector_status_connected :6797 connector_status_disconnected);6798}6799 6800int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,6801 struct drm_connector_state *connector_state,6802 struct drm_property *property,6803 uint64_t val)6804{6805 struct drm_device *dev = connector->dev;6806 struct amdgpu_device *adev = drm_to_adev(dev);6807 struct dm_connector_state *dm_old_state =6808 to_dm_connector_state(connector->state);6809 struct dm_connector_state *dm_new_state =6810 to_dm_connector_state(connector_state);6811 6812 int ret = -EINVAL;6813 6814 if (property == dev->mode_config.scaling_mode_property) {6815 enum amdgpu_rmx_type rmx_type;6816 6817 switch (val) {6818 case DRM_MODE_SCALE_CENTER:6819 rmx_type = RMX_CENTER;6820 break;6821 case DRM_MODE_SCALE_ASPECT:6822 rmx_type = RMX_ASPECT;6823 break;6824 case DRM_MODE_SCALE_FULLSCREEN:6825 rmx_type = RMX_FULL;6826 break;6827 case DRM_MODE_SCALE_NONE:6828 default:6829 rmx_type = RMX_OFF;6830 break;6831 }6832 6833 if (dm_old_state->scaling == rmx_type)6834 return 0;6835 6836 dm_new_state->scaling = rmx_type;6837 ret = 0;6838 } else if (property == adev->mode_info.underscan_hborder_property) {6839 dm_new_state->underscan_hborder = val;6840 ret = 0;6841 } else if (property == adev->mode_info.underscan_vborder_property) {6842 dm_new_state->underscan_vborder = val;6843 ret = 0;6844 } else if (property == adev->mode_info.underscan_property) {6845 dm_new_state->underscan_enable = val;6846 ret = 0;6847 }6848 6849 return ret;6850}6851 6852int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,6853 const struct drm_connector_state *state,6854 struct drm_property *property,6855 uint64_t *val)6856{6857 struct drm_device *dev = connector->dev;6858 struct amdgpu_device *adev = drm_to_adev(dev);6859 struct dm_connector_state *dm_state =6860 to_dm_connector_state(state);6861 int ret = -EINVAL;6862 6863 if (property == dev->mode_config.scaling_mode_property) {6864 switch (dm_state->scaling) {6865 case RMX_CENTER:6866 *val = DRM_MODE_SCALE_CENTER;6867 break;6868 case RMX_ASPECT:6869 *val = DRM_MODE_SCALE_ASPECT;6870 break;6871 case RMX_FULL:6872 *val = DRM_MODE_SCALE_FULLSCREEN;6873 break;6874 case RMX_OFF:6875 default:6876 *val = DRM_MODE_SCALE_NONE;6877 break;6878 }6879 ret = 0;6880 } else if (property == adev->mode_info.underscan_hborder_property) {6881 *val = dm_state->underscan_hborder;6882 ret = 0;6883 } else if (property == adev->mode_info.underscan_vborder_property) {6884 *val = dm_state->underscan_vborder;6885 ret = 0;6886 } else if (property == adev->mode_info.underscan_property) {6887 *val = dm_state->underscan_enable;6888 ret = 0;6889 }6890 6891 return ret;6892}6893 6894/**6895 * DOC: panel power savings6896 *6897 * The display manager allows you to set your desired **panel power savings**6898 * level (between 0-4, with 0 representing off), e.g. using the following::6899 *6900 * # echo 3 > /sys/class/drm/card0-eDP-1/amdgpu/panel_power_savings6901 *6902 * Modifying this value can have implications on color accuracy, so tread6903 * carefully.6904 */6905 6906static ssize_t panel_power_savings_show(struct device *device,6907 struct device_attribute *attr,6908 char *buf)6909{6910 struct drm_connector *connector = dev_get_drvdata(device);6911 struct drm_device *dev = connector->dev;6912 u8 val;6913 6914 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);6915 val = to_dm_connector_state(connector->state)->abm_level ==6916 ABM_LEVEL_IMMEDIATE_DISABLE ? 0 :6917 to_dm_connector_state(connector->state)->abm_level;6918 drm_modeset_unlock(&dev->mode_config.connection_mutex);6919 6920 return sysfs_emit(buf, "%u\n", val);6921}6922 6923static ssize_t panel_power_savings_store(struct device *device,6924 struct device_attribute *attr,6925 const char *buf, size_t count)6926{6927 struct drm_connector *connector = dev_get_drvdata(device);6928 struct drm_device *dev = connector->dev;6929 long val;6930 int ret;6931 6932 ret = kstrtol(buf, 0, &val);6933 6934 if (ret)6935 return ret;6936 6937 if (val < 0 || val > 4)6938 return -EINVAL;6939 6940 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);6941 to_dm_connector_state(connector->state)->abm_level = val ?:6942 ABM_LEVEL_IMMEDIATE_DISABLE;6943 drm_modeset_unlock(&dev->mode_config.connection_mutex);6944 6945 drm_kms_helper_hotplug_event(dev);6946 6947 return count;6948}6949 6950static DEVICE_ATTR_RW(panel_power_savings);6951 6952static struct attribute *amdgpu_attrs[] = {6953 &dev_attr_panel_power_savings.attr,6954 NULL6955};6956 6957static const struct attribute_group amdgpu_group = {6958 .name = "amdgpu",6959 .attrs = amdgpu_attrs6960};6961 6962static bool6963amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector)6964{6965 if (amdgpu_dm_abm_level >= 0)6966 return false;6967 6968 if (amdgpu_dm_connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)6969 return false;6970 6971 /* check for OLED panels */6972 if (amdgpu_dm_connector->bl_idx >= 0) {6973 struct drm_device *drm = amdgpu_dm_connector->base.dev;6974 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;6975 struct amdgpu_dm_backlight_caps *caps;6976 6977 caps = &dm->backlight_caps[amdgpu_dm_connector->bl_idx];6978 if (caps->aux_support)6979 return false;6980 }6981 6982 return true;6983}6984 6985static void amdgpu_dm_connector_unregister(struct drm_connector *connector)6986{6987 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);6988 6989 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector))6990 sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group);6991 6992 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);6993}6994 6995static void amdgpu_dm_connector_destroy(struct drm_connector *connector)6996{6997 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);6998 struct amdgpu_device *adev = drm_to_adev(connector->dev);6999 struct amdgpu_display_manager *dm = &adev->dm;7000 7001 /*7002 * Call only if mst_mgr was initialized before since it's not done7003 * for all connector types.7004 */7005 if (aconnector->mst_mgr.dev)7006 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);7007 7008 if (aconnector->bl_idx != -1) {7009 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);7010 dm->backlight_dev[aconnector->bl_idx] = NULL;7011 }7012 7013 if (aconnector->dc_em_sink)7014 dc_sink_release(aconnector->dc_em_sink);7015 aconnector->dc_em_sink = NULL;7016 if (aconnector->dc_sink)7017 dc_sink_release(aconnector->dc_sink);7018 aconnector->dc_sink = NULL;7019 7020 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);7021 drm_connector_unregister(connector);7022 drm_connector_cleanup(connector);7023 if (aconnector->i2c) {7024 i2c_del_adapter(&aconnector->i2c->base);7025 kfree(aconnector->i2c);7026 }7027 kfree(aconnector->dm_dp_aux.aux.name);7028 7029 kfree(connector);7030}7031 7032void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)7033{7034 struct dm_connector_state *state =7035 to_dm_connector_state(connector->state);7036 7037 if (connector->state)7038 __drm_atomic_helper_connector_destroy_state(connector->state);7039 7040 kfree(state);7041 7042 state = kzalloc(sizeof(*state), GFP_KERNEL);7043 7044 if (state) {7045 state->scaling = RMX_OFF;7046 state->underscan_enable = false;7047 state->underscan_hborder = 0;7048 state->underscan_vborder = 0;7049 state->base.max_requested_bpc = 8;7050 state->vcpi_slots = 0;7051 state->pbn = 0;7052 7053 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {7054 if (amdgpu_dm_abm_level <= 0)7055 state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE;7056 else7057 state->abm_level = amdgpu_dm_abm_level;7058 }7059 7060 __drm_atomic_helper_connector_reset(connector, &state->base);7061 }7062}7063 7064struct drm_connector_state *7065amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)7066{7067 struct dm_connector_state *state =7068 to_dm_connector_state(connector->state);7069 7070 struct dm_connector_state *new_state =7071 kmemdup(state, sizeof(*state), GFP_KERNEL);7072 7073 if (!new_state)7074 return NULL;7075 7076 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);7077 7078 new_state->freesync_capable = state->freesync_capable;7079 new_state->abm_level = state->abm_level;7080 new_state->scaling = state->scaling;7081 new_state->underscan_enable = state->underscan_enable;7082 new_state->underscan_hborder = state->underscan_hborder;7083 new_state->underscan_vborder = state->underscan_vborder;7084 new_state->vcpi_slots = state->vcpi_slots;7085 new_state->pbn = state->pbn;7086 return &new_state->base;7087}7088 7089static int7090amdgpu_dm_connector_late_register(struct drm_connector *connector)7091{7092 struct amdgpu_dm_connector *amdgpu_dm_connector =7093 to_amdgpu_dm_connector(connector);7094 int r;7095 7096 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) {7097 r = sysfs_create_group(&connector->kdev->kobj,7098 &amdgpu_group);7099 if (r)7100 return r;7101 }7102 7103 amdgpu_dm_register_backlight_device(amdgpu_dm_connector);7104 7105 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||7106 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {7107 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;7108 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);7109 if (r)7110 return r;7111 }7112 7113#if defined(CONFIG_DEBUG_FS)7114 connector_debugfs_init(amdgpu_dm_connector);7115#endif7116 7117 return 0;7118}7119 7120static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)7121{7122 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);7123 struct dc_link *dc_link = aconnector->dc_link;7124 struct dc_sink *dc_em_sink = aconnector->dc_em_sink;7125 struct edid *edid;7126 struct i2c_adapter *ddc;7127 7128 if (dc_link && dc_link->aux_mode)7129 ddc = &aconnector->dm_dp_aux.aux.ddc;7130 else7131 ddc = &aconnector->i2c->base;7132 7133 /*7134 * Note: drm_get_edid gets edid in the following order:7135 * 1) override EDID if set via edid_override debugfs,7136 * 2) firmware EDID if set via edid_firmware module parameter7137 * 3) regular DDC read.7138 */7139 edid = drm_get_edid(connector, ddc);7140 if (!edid) {7141 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);7142 return;7143 }7144 7145 aconnector->edid = edid;7146 7147 /* Update emulated (virtual) sink's EDID */7148 if (dc_em_sink && dc_link) {7149 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));7150 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);7151 dm_helpers_parse_edid_caps(7152 dc_link,7153 &dc_em_sink->dc_edid,7154 &dc_em_sink->edid_caps);7155 }7156}7157 7158static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {7159 .reset = amdgpu_dm_connector_funcs_reset,7160 .detect = amdgpu_dm_connector_detect,7161 .fill_modes = drm_helper_probe_single_connector_modes,7162 .destroy = amdgpu_dm_connector_destroy,7163 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,7164 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,7165 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,7166 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,7167 .late_register = amdgpu_dm_connector_late_register,7168 .early_unregister = amdgpu_dm_connector_unregister,7169 .force = amdgpu_dm_connector_funcs_force7170};7171 7172static int get_modes(struct drm_connector *connector)7173{7174 return amdgpu_dm_connector_get_modes(connector);7175}7176 7177static void create_eml_sink(struct amdgpu_dm_connector *aconnector)7178{7179 struct drm_connector *connector = &aconnector->base;7180 struct dc_link *dc_link = aconnector->dc_link;7181 struct dc_sink_init_data init_params = {7182 .link = aconnector->dc_link,7183 .sink_signal = SIGNAL_TYPE_VIRTUAL7184 };7185 struct edid *edid;7186 struct i2c_adapter *ddc;7187 7188 if (dc_link->aux_mode)7189 ddc = &aconnector->dm_dp_aux.aux.ddc;7190 else7191 ddc = &aconnector->i2c->base;7192 7193 /*7194 * Note: drm_get_edid gets edid in the following order:7195 * 1) override EDID if set via edid_override debugfs,7196 * 2) firmware EDID if set via edid_firmware module parameter7197 * 3) regular DDC read.7198 */7199 edid = drm_get_edid(connector, ddc);7200 if (!edid) {7201 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);7202 return;7203 }7204 7205 if (drm_detect_hdmi_monitor(edid))7206 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;7207 7208 aconnector->edid = edid;7209 7210 aconnector->dc_em_sink = dc_link_add_remote_sink(7211 aconnector->dc_link,7212 (uint8_t *)edid,7213 (edid->extensions + 1) * EDID_LENGTH,7214 &init_params);7215 7216 if (aconnector->base.force == DRM_FORCE_ON) {7217 aconnector->dc_sink = aconnector->dc_link->local_sink ?7218 aconnector->dc_link->local_sink :7219 aconnector->dc_em_sink;7220 if (aconnector->dc_sink)7221 dc_sink_retain(aconnector->dc_sink);7222 }7223}7224 7225static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)7226{7227 struct dc_link *link = (struct dc_link *)aconnector->dc_link;7228 7229 /*7230 * In case of headless boot with force on for DP managed connector7231 * Those settings have to be != 0 to get initial modeset7232 */7233 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {7234 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;7235 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;7236 }7237 7238 create_eml_sink(aconnector);7239}7240 7241static enum dc_status dm_validate_stream_and_context(struct dc *dc,7242 struct dc_stream_state *stream)7243{7244 enum dc_status dc_result = DC_ERROR_UNEXPECTED;7245 struct dc_plane_state *dc_plane_state = NULL;7246 struct dc_state *dc_state = NULL;7247 7248 if (!stream)7249 goto cleanup;7250 7251 dc_plane_state = dc_create_plane_state(dc);7252 if (!dc_plane_state)7253 goto cleanup;7254 7255 dc_state = dc_state_create(dc, NULL);7256 if (!dc_state)7257 goto cleanup;7258 7259 /* populate stream to plane */7260 dc_plane_state->src_rect.height = stream->src.height;7261 dc_plane_state->src_rect.width = stream->src.width;7262 dc_plane_state->dst_rect.height = stream->src.height;7263 dc_plane_state->dst_rect.width = stream->src.width;7264 dc_plane_state->clip_rect.height = stream->src.height;7265 dc_plane_state->clip_rect.width = stream->src.width;7266 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;7267 dc_plane_state->plane_size.surface_size.height = stream->src.height;7268 dc_plane_state->plane_size.surface_size.width = stream->src.width;7269 dc_plane_state->plane_size.chroma_size.height = stream->src.height;7270 dc_plane_state->plane_size.chroma_size.width = stream->src.width;7271 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;7272 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;7273 dc_plane_state->rotation = ROTATION_ANGLE_0;7274 dc_plane_state->is_tiling_rotated = false;7275 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;7276 7277 dc_result = dc_validate_stream(dc, stream);7278 if (dc_result == DC_OK)7279 dc_result = dc_validate_plane(dc, dc_plane_state);7280 7281 if (dc_result == DC_OK)7282 dc_result = dc_state_add_stream(dc, dc_state, stream);7283 7284 if (dc_result == DC_OK && !dc_state_add_plane(7285 dc,7286 stream,7287 dc_plane_state,7288 dc_state))7289 dc_result = DC_FAIL_ATTACH_SURFACES;7290 7291 if (dc_result == DC_OK)7292 dc_result = dc_validate_global_state(dc, dc_state, true);7293 7294cleanup:7295 if (dc_state)7296 dc_state_release(dc_state);7297 7298 if (dc_plane_state)7299 dc_plane_state_release(dc_plane_state);7300 7301 return dc_result;7302}7303 7304struct dc_stream_state *7305create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,7306 const struct drm_display_mode *drm_mode,7307 const struct dm_connector_state *dm_state,7308 const struct dc_stream_state *old_stream)7309{7310 struct drm_connector *connector = &aconnector->base;7311 struct amdgpu_device *adev = drm_to_adev(connector->dev);7312 struct dc_stream_state *stream;7313 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;7314 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;7315 enum dc_status dc_result = DC_OK;7316 7317 if (!dm_state)7318 return NULL;7319 7320 do {7321 stream = create_stream_for_sink(connector, drm_mode,7322 dm_state, old_stream,7323 requested_bpc);7324 if (stream == NULL) {7325 DRM_ERROR("Failed to create stream for sink!\n");7326 break;7327 }7328 7329 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)7330 return stream;7331 7332 dc_result = dc_validate_stream(adev->dm.dc, stream);7333 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)7334 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);7335 7336 if (dc_result == DC_OK)7337 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);7338 7339 if (dc_result != DC_OK) {7340 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",7341 drm_mode->hdisplay,7342 drm_mode->vdisplay,7343 drm_mode->clock,7344 dc_result,7345 dc_status_to_str(dc_result));7346 7347 dc_stream_release(stream);7348 stream = NULL;7349 requested_bpc -= 2; /* lower bpc to retry validation */7350 }7351 7352 } while (stream == NULL && requested_bpc >= 6);7353 7354 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {7355 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");7356 7357 aconnector->force_yuv420_output = true;7358 stream = create_validate_stream_for_sink(aconnector, drm_mode,7359 dm_state, old_stream);7360 aconnector->force_yuv420_output = false;7361 }7362 7363 return stream;7364}7365 7366enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,7367 struct drm_display_mode *mode)7368{7369 int result = MODE_ERROR;7370 struct dc_sink *dc_sink;7371 /* TODO: Unhardcode stream count */7372 struct dc_stream_state *stream;7373 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);7374 7375 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||7376 (mode->flags & DRM_MODE_FLAG_DBLSCAN))7377 return result;7378 7379 /*7380 * Only run this the first time mode_valid is called to initilialize7381 * EDID mgmt7382 */7383 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&7384 !aconnector->dc_em_sink)7385 handle_edid_mgmt(aconnector);7386 7387 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;7388 7389 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&7390 aconnector->base.force != DRM_FORCE_ON) {7391 DRM_ERROR("dc_sink is NULL!\n");7392 goto fail;7393 }7394 7395 drm_mode_set_crtcinfo(mode, 0);7396 7397 stream = create_validate_stream_for_sink(aconnector, mode,7398 to_dm_connector_state(connector->state),7399 NULL);7400 if (stream) {7401 dc_stream_release(stream);7402 result = MODE_OK;7403 }7404 7405fail:7406 /* TODO: error handling*/7407 return result;7408}7409 7410static int fill_hdr_info_packet(const struct drm_connector_state *state,7411 struct dc_info_packet *out)7412{7413 struct hdmi_drm_infoframe frame;7414 unsigned char buf[30]; /* 26 + 4 */7415 ssize_t len;7416 int ret, i;7417 7418 memset(out, 0, sizeof(*out));7419 7420 if (!state->hdr_output_metadata)7421 return 0;7422 7423 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);7424 if (ret)7425 return ret;7426 7427 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));7428 if (len < 0)7429 return (int)len;7430 7431 /* Static metadata is a fixed 26 bytes + 4 byte header. */7432 if (len != 30)7433 return -EINVAL;7434 7435 /* Prepare the infopacket for DC. */7436 switch (state->connector->connector_type) {7437 case DRM_MODE_CONNECTOR_HDMIA:7438 out->hb0 = 0x87; /* type */7439 out->hb1 = 0x01; /* version */7440 out->hb2 = 0x1A; /* length */7441 out->sb[0] = buf[3]; /* checksum */7442 i = 1;7443 break;7444 7445 case DRM_MODE_CONNECTOR_DisplayPort:7446 case DRM_MODE_CONNECTOR_eDP:7447 out->hb0 = 0x00; /* sdp id, zero */7448 out->hb1 = 0x87; /* type */7449 out->hb2 = 0x1D; /* payload len - 1 */7450 out->hb3 = (0x13 << 2); /* sdp version */7451 out->sb[0] = 0x01; /* version */7452 out->sb[1] = 0x1A; /* length */7453 i = 2;7454 break;7455 7456 default:7457 return -EINVAL;7458 }7459 7460 memcpy(&out->sb[i], &buf[4], 26);7461 out->valid = true;7462 7463 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,7464 sizeof(out->sb), false);7465 7466 return 0;7467}7468 7469static int7470amdgpu_dm_connector_atomic_check(struct drm_connector *conn,7471 struct drm_atomic_state *state)7472{7473 struct drm_connector_state *new_con_state =7474 drm_atomic_get_new_connector_state(state, conn);7475 struct drm_connector_state *old_con_state =7476 drm_atomic_get_old_connector_state(state, conn);7477 struct drm_crtc *crtc = new_con_state->crtc;7478 struct drm_crtc_state *new_crtc_state;7479 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);7480 int ret;7481 7482 trace_amdgpu_dm_connector_atomic_check(new_con_state);7483 7484 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {7485 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);7486 if (ret < 0)7487 return ret;7488 }7489 7490 if (!crtc)7491 return 0;7492 7493 if (new_con_state->colorspace != old_con_state->colorspace) {7494 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);7495 if (IS_ERR(new_crtc_state))7496 return PTR_ERR(new_crtc_state);7497 7498 new_crtc_state->mode_changed = true;7499 }7500 7501 if (new_con_state->content_type != old_con_state->content_type) {7502 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);7503 if (IS_ERR(new_crtc_state))7504 return PTR_ERR(new_crtc_state);7505 7506 new_crtc_state->mode_changed = true;7507 }7508 7509 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {7510 struct dc_info_packet hdr_infopacket;7511 7512 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);7513 if (ret)7514 return ret;7515 7516 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);7517 if (IS_ERR(new_crtc_state))7518 return PTR_ERR(new_crtc_state);7519 7520 /*7521 * DC considers the stream backends changed if the7522 * static metadata changes. Forcing the modeset also7523 * gives a simple way for userspace to switch from7524 * 8bpc to 10bpc when setting the metadata to enter7525 * or exit HDR.7526 *7527 * Changing the static metadata after it's been7528 * set is permissible, however. So only force a7529 * modeset if we're entering or exiting HDR.7530 */7531 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||7532 !old_con_state->hdr_output_metadata ||7533 !new_con_state->hdr_output_metadata;7534 }7535 7536 return 0;7537}7538 7539static const struct drm_connector_helper_funcs7540amdgpu_dm_connector_helper_funcs = {7541 /*7542 * If hotplugging a second bigger display in FB Con mode, bigger resolution7543 * modes will be filtered by drm_mode_validate_size(), and those modes7544 * are missing after user start lightdm. So we need to renew modes list.7545 * in get_modes call back, not just return the modes count7546 */7547 .get_modes = get_modes,7548 .mode_valid = amdgpu_dm_connector_mode_valid,7549 .atomic_check = amdgpu_dm_connector_atomic_check,7550};7551 7552static void dm_encoder_helper_disable(struct drm_encoder *encoder)7553{7554 7555}7556 7557int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)7558{7559 switch (display_color_depth) {7560 case COLOR_DEPTH_666:7561 return 6;7562 case COLOR_DEPTH_888:7563 return 8;7564 case COLOR_DEPTH_101010:7565 return 10;7566 case COLOR_DEPTH_121212:7567 return 12;7568 case COLOR_DEPTH_141414:7569 return 14;7570 case COLOR_DEPTH_161616:7571 return 16;7572 default:7573 break;7574 }7575 return 0;7576}7577 7578static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,7579 struct drm_crtc_state *crtc_state,7580 struct drm_connector_state *conn_state)7581{7582 struct drm_atomic_state *state = crtc_state->state;7583 struct drm_connector *connector = conn_state->connector;7584 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);7585 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);7586 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;7587 struct drm_dp_mst_topology_mgr *mst_mgr;7588 struct drm_dp_mst_port *mst_port;7589 struct drm_dp_mst_topology_state *mst_state;7590 enum dc_color_depth color_depth;7591 int clock, bpp = 0;7592 bool is_y420 = false;7593 7594 if (!aconnector->mst_output_port)7595 return 0;7596 7597 mst_port = aconnector->mst_output_port;7598 mst_mgr = &aconnector->mst_root->mst_mgr;7599 7600 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)7601 return 0;7602 7603 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);7604 if (IS_ERR(mst_state))7605 return PTR_ERR(mst_state);7606 7607 mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link));7608 7609 if (!state->duplicated) {7610 int max_bpc = conn_state->max_requested_bpc;7611 7612 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&7613 aconnector->force_yuv420_output;7614 color_depth = convert_color_depth_from_display_info(connector,7615 is_y420,7616 max_bpc);7617 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;7618 clock = adjusted_mode->clock;7619 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);7620 }7621 7622 dm_new_connector_state->vcpi_slots =7623 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,7624 dm_new_connector_state->pbn);7625 if (dm_new_connector_state->vcpi_slots < 0) {7626 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);7627 return dm_new_connector_state->vcpi_slots;7628 }7629 return 0;7630}7631 7632const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {7633 .disable = dm_encoder_helper_disable,7634 .atomic_check = dm_encoder_helper_atomic_check7635};7636 7637static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,7638 struct dc_state *dc_state,7639 struct dsc_mst_fairness_vars *vars)7640{7641 struct dc_stream_state *stream = NULL;7642 struct drm_connector *connector;7643 struct drm_connector_state *new_con_state;7644 struct amdgpu_dm_connector *aconnector;7645 struct dm_connector_state *dm_conn_state;7646 int i, j, ret;7647 int vcpi, pbn_div, pbn = 0, slot_num = 0;7648 7649 for_each_new_connector_in_state(state, connector, new_con_state, i) {7650 7651 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)7652 continue;7653 7654 aconnector = to_amdgpu_dm_connector(connector);7655 7656 if (!aconnector->mst_output_port)7657 continue;7658 7659 if (!new_con_state || !new_con_state->crtc)7660 continue;7661 7662 dm_conn_state = to_dm_connector_state(new_con_state);7663 7664 for (j = 0; j < dc_state->stream_count; j++) {7665 stream = dc_state->streams[j];7666 if (!stream)7667 continue;7668 7669 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)7670 break;7671 7672 stream = NULL;7673 }7674 7675 if (!stream)7676 continue;7677 7678 pbn_div = dm_mst_get_pbn_divider(stream->link);7679 /* pbn is calculated by compute_mst_dsc_configs_for_state*/7680 for (j = 0; j < dc_state->stream_count; j++) {7681 if (vars[j].aconnector == aconnector) {7682 pbn = vars[j].pbn;7683 break;7684 }7685 }7686 7687 if (j == dc_state->stream_count || pbn_div == 0)7688 continue;7689 7690 slot_num = DIV_ROUND_UP(pbn, pbn_div);7691 7692 if (stream->timing.flags.DSC != 1) {7693 dm_conn_state->pbn = pbn;7694 dm_conn_state->vcpi_slots = slot_num;7695 7696 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,7697 dm_conn_state->pbn, false);7698 if (ret < 0)7699 return ret;7700 7701 continue;7702 }7703 7704 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);7705 if (vcpi < 0)7706 return vcpi;7707 7708 dm_conn_state->pbn = pbn;7709 dm_conn_state->vcpi_slots = vcpi;7710 }7711 return 0;7712}7713 7714static int to_drm_connector_type(enum signal_type st)7715{7716 switch (st) {7717 case SIGNAL_TYPE_HDMI_TYPE_A:7718 return DRM_MODE_CONNECTOR_HDMIA;7719 case SIGNAL_TYPE_EDP:7720 return DRM_MODE_CONNECTOR_eDP;7721 case SIGNAL_TYPE_LVDS:7722 return DRM_MODE_CONNECTOR_LVDS;7723 case SIGNAL_TYPE_RGB:7724 return DRM_MODE_CONNECTOR_VGA;7725 case SIGNAL_TYPE_DISPLAY_PORT:7726 case SIGNAL_TYPE_DISPLAY_PORT_MST:7727 return DRM_MODE_CONNECTOR_DisplayPort;7728 case SIGNAL_TYPE_DVI_DUAL_LINK:7729 case SIGNAL_TYPE_DVI_SINGLE_LINK:7730 return DRM_MODE_CONNECTOR_DVID;7731 case SIGNAL_TYPE_VIRTUAL:7732 return DRM_MODE_CONNECTOR_VIRTUAL;7733 7734 default:7735 return DRM_MODE_CONNECTOR_Unknown;7736 }7737}7738 7739static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)7740{7741 struct drm_encoder *encoder;7742 7743 /* There is only one encoder per connector */7744 drm_connector_for_each_possible_encoder(connector, encoder)7745 return encoder;7746 7747 return NULL;7748}7749 7750static void amdgpu_dm_get_native_mode(struct drm_connector *connector)7751{7752 struct drm_encoder *encoder;7753 struct amdgpu_encoder *amdgpu_encoder;7754 7755 encoder = amdgpu_dm_connector_to_encoder(connector);7756 7757 if (encoder == NULL)7758 return;7759 7760 amdgpu_encoder = to_amdgpu_encoder(encoder);7761 7762 amdgpu_encoder->native_mode.clock = 0;7763 7764 if (!list_empty(&connector->probed_modes)) {7765 struct drm_display_mode *preferred_mode = NULL;7766 7767 list_for_each_entry(preferred_mode,7768 &connector->probed_modes,7769 head) {7770 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)7771 amdgpu_encoder->native_mode = *preferred_mode;7772 7773 break;7774 }7775 7776 }7777}7778 7779static struct drm_display_mode *7780amdgpu_dm_create_common_mode(struct drm_encoder *encoder,7781 char *name,7782 int hdisplay, int vdisplay)7783{7784 struct drm_device *dev = encoder->dev;7785 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);7786 struct drm_display_mode *mode = NULL;7787 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;7788 7789 mode = drm_mode_duplicate(dev, native_mode);7790 7791 if (mode == NULL)7792 return NULL;7793 7794 mode->hdisplay = hdisplay;7795 mode->vdisplay = vdisplay;7796 mode->type &= ~DRM_MODE_TYPE_PREFERRED;7797 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);7798 7799 return mode;7800 7801}7802 7803static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,7804 struct drm_connector *connector)7805{7806 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);7807 struct drm_display_mode *mode = NULL;7808 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;7809 struct amdgpu_dm_connector *amdgpu_dm_connector =7810 to_amdgpu_dm_connector(connector);7811 int i;7812 int n;7813 struct mode_size {7814 char name[DRM_DISPLAY_MODE_LEN];7815 int w;7816 int h;7817 } common_modes[] = {7818 { "640x480", 640, 480},7819 { "800x600", 800, 600},7820 { "1024x768", 1024, 768},7821 { "1280x720", 1280, 720},7822 { "1280x800", 1280, 800},7823 {"1280x1024", 1280, 1024},7824 { "1440x900", 1440, 900},7825 {"1680x1050", 1680, 1050},7826 {"1600x1200", 1600, 1200},7827 {"1920x1080", 1920, 1080},7828 {"1920x1200", 1920, 1200}7829 };7830 7831 n = ARRAY_SIZE(common_modes);7832 7833 for (i = 0; i < n; i++) {7834 struct drm_display_mode *curmode = NULL;7835 bool mode_existed = false;7836 7837 if (common_modes[i].w > native_mode->hdisplay ||7838 common_modes[i].h > native_mode->vdisplay ||7839 (common_modes[i].w == native_mode->hdisplay &&7840 common_modes[i].h == native_mode->vdisplay))7841 continue;7842 7843 list_for_each_entry(curmode, &connector->probed_modes, head) {7844 if (common_modes[i].w == curmode->hdisplay &&7845 common_modes[i].h == curmode->vdisplay) {7846 mode_existed = true;7847 break;7848 }7849 }7850 7851 if (mode_existed)7852 continue;7853 7854 mode = amdgpu_dm_create_common_mode(encoder,7855 common_modes[i].name, common_modes[i].w,7856 common_modes[i].h);7857 if (!mode)7858 continue;7859 7860 drm_mode_probed_add(connector, mode);7861 amdgpu_dm_connector->num_modes++;7862 }7863}7864 7865static void amdgpu_set_panel_orientation(struct drm_connector *connector)7866{7867 struct drm_encoder *encoder;7868 struct amdgpu_encoder *amdgpu_encoder;7869 const struct drm_display_mode *native_mode;7870 7871 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&7872 connector->connector_type != DRM_MODE_CONNECTOR_LVDS)7873 return;7874 7875 mutex_lock(&connector->dev->mode_config.mutex);7876 amdgpu_dm_connector_get_modes(connector);7877 mutex_unlock(&connector->dev->mode_config.mutex);7878 7879 encoder = amdgpu_dm_connector_to_encoder(connector);7880 if (!encoder)7881 return;7882 7883 amdgpu_encoder = to_amdgpu_encoder(encoder);7884 7885 native_mode = &amdgpu_encoder->native_mode;7886 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)7887 return;7888 7889 drm_connector_set_panel_orientation_with_quirk(connector,7890 DRM_MODE_PANEL_ORIENTATION_UNKNOWN,7891 native_mode->hdisplay,7892 native_mode->vdisplay);7893}7894 7895static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,7896 struct edid *edid)7897{7898 struct amdgpu_dm_connector *amdgpu_dm_connector =7899 to_amdgpu_dm_connector(connector);7900 7901 if (edid) {7902 /* empty probed_modes */7903 INIT_LIST_HEAD(&connector->probed_modes);7904 amdgpu_dm_connector->num_modes =7905 drm_add_edid_modes(connector, edid);7906 7907 /* sorting the probed modes before calling function7908 * amdgpu_dm_get_native_mode() since EDID can have7909 * more than one preferred mode. The modes that are7910 * later in the probed mode list could be of higher7911 * and preferred resolution. For example, 3840x21607912 * resolution in base EDID preferred timing and 4096x21607913 * preferred resolution in DID extension block later.7914 */7915 drm_mode_sort(&connector->probed_modes);7916 amdgpu_dm_get_native_mode(connector);7917 7918 /* Freesync capabilities are reset by calling7919 * drm_add_edid_modes() and need to be7920 * restored here.7921 */7922 amdgpu_dm_update_freesync_caps(connector, edid);7923 } else {7924 amdgpu_dm_connector->num_modes = 0;7925 }7926}7927 7928static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,7929 struct drm_display_mode *mode)7930{7931 struct drm_display_mode *m;7932 7933 list_for_each_entry(m, &aconnector->base.probed_modes, head) {7934 if (drm_mode_equal(m, mode))7935 return true;7936 }7937 7938 return false;7939}7940 7941static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)7942{7943 const struct drm_display_mode *m;7944 struct drm_display_mode *new_mode;7945 uint i;7946 u32 new_modes_count = 0;7947 7948 /* Standard FPS values7949 *7950 * 23.976 - TV/NTSC7951 * 24 - Cinema7952 * 25 - TV/PAL7953 * 29.97 - TV/NTSC7954 * 30 - TV/NTSC7955 * 48 - Cinema HFR7956 * 50 - TV/PAL7957 * 60 - Commonly used7958 * 48,72,96,120 - Multiples of 247959 */7960 static const u32 common_rates[] = {7961 23976, 24000, 25000, 29970, 30000,7962 48000, 50000, 60000, 72000, 96000, 1200007963 };7964 7965 /*7966 * Find mode with highest refresh rate with the same resolution7967 * as the preferred mode. Some monitors report a preferred mode7968 * with lower resolution than the highest refresh rate supported.7969 */7970 7971 m = get_highest_refresh_rate_mode(aconnector, true);7972 if (!m)7973 return 0;7974 7975 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {7976 u64 target_vtotal, target_vtotal_diff;7977 u64 num, den;7978 7979 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])7980 continue;7981 7982 if (common_rates[i] < aconnector->min_vfreq * 1000 ||7983 common_rates[i] > aconnector->max_vfreq * 1000)7984 continue;7985 7986 num = (unsigned long long)m->clock * 1000 * 1000;7987 den = common_rates[i] * (unsigned long long)m->htotal;7988 target_vtotal = div_u64(num, den);7989 target_vtotal_diff = target_vtotal - m->vtotal;7990 7991 /* Check for illegal modes */7992 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||7993 m->vsync_end + target_vtotal_diff < m->vsync_start ||7994 m->vtotal + target_vtotal_diff < m->vsync_end)7995 continue;7996 7997 new_mode = drm_mode_duplicate(aconnector->base.dev, m);7998 if (!new_mode)7999 goto out;8000 8001 new_mode->vtotal += (u16)target_vtotal_diff;8002 new_mode->vsync_start += (u16)target_vtotal_diff;8003 new_mode->vsync_end += (u16)target_vtotal_diff;8004 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;8005 new_mode->type |= DRM_MODE_TYPE_DRIVER;8006 8007 if (!is_duplicate_mode(aconnector, new_mode)) {8008 drm_mode_probed_add(&aconnector->base, new_mode);8009 new_modes_count += 1;8010 } else8011 drm_mode_destroy(aconnector->base.dev, new_mode);8012 }8013 out:8014 return new_modes_count;8015}8016 8017static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,8018 struct edid *edid)8019{8020 struct amdgpu_dm_connector *amdgpu_dm_connector =8021 to_amdgpu_dm_connector(connector);8022 8023 if (!(amdgpu_freesync_vid_mode && edid))8024 return;8025 8026 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)8027 amdgpu_dm_connector->num_modes +=8028 add_fs_modes(amdgpu_dm_connector);8029}8030 8031static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)8032{8033 struct amdgpu_dm_connector *amdgpu_dm_connector =8034 to_amdgpu_dm_connector(connector);8035 struct drm_encoder *encoder;8036 struct edid *edid = amdgpu_dm_connector->edid;8037 struct dc_link_settings *verified_link_cap =8038 &amdgpu_dm_connector->dc_link->verified_link_cap;8039 const struct dc *dc = amdgpu_dm_connector->dc_link->dc;8040 8041 encoder = amdgpu_dm_connector_to_encoder(connector);8042 8043 if (!drm_edid_is_valid(edid)) {8044 amdgpu_dm_connector->num_modes =8045 drm_add_modes_noedid(connector, 640, 480);8046 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)8047 amdgpu_dm_connector->num_modes +=8048 drm_add_modes_noedid(connector, 1920, 1080);8049 } else {8050 amdgpu_dm_connector_ddc_get_modes(connector, edid);8051 if (encoder)8052 amdgpu_dm_connector_add_common_modes(encoder, connector);8053 amdgpu_dm_connector_add_freesync_modes(connector, edid);8054 }8055 amdgpu_dm_fbc_init(connector);8056 8057 return amdgpu_dm_connector->num_modes;8058}8059 8060static const u32 supported_colorspaces =8061 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |8062 BIT(DRM_MODE_COLORIMETRY_OPRGB) |8063 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |8064 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);8065 8066void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,8067 struct amdgpu_dm_connector *aconnector,8068 int connector_type,8069 struct dc_link *link,8070 int link_index)8071{8072 struct amdgpu_device *adev = drm_to_adev(dm->ddev);8073 8074 /*8075 * Some of the properties below require access to state, like bpc.8076 * Allocate some default initial connector state with our reset helper.8077 */8078 if (aconnector->base.funcs->reset)8079 aconnector->base.funcs->reset(&aconnector->base);8080 8081 aconnector->connector_id = link_index;8082 aconnector->bl_idx = -1;8083 aconnector->dc_link = link;8084 aconnector->base.interlace_allowed = false;8085 aconnector->base.doublescan_allowed = false;8086 aconnector->base.stereo_allowed = false;8087 aconnector->base.dpms = DRM_MODE_DPMS_OFF;8088 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */8089 aconnector->audio_inst = -1;8090 aconnector->pack_sdp_v1_3 = false;8091 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;8092 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));8093 mutex_init(&aconnector->hpd_lock);8094 mutex_init(&aconnector->handle_mst_msg_ready);8095 8096 /*8097 * configure support HPD hot plug connector_>polled default value is 08098 * which means HPD hot plug not supported8099 */8100 switch (connector_type) {8101 case DRM_MODE_CONNECTOR_HDMIA:8102 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;8103 aconnector->base.ycbcr_420_allowed =8104 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;8105 break;8106 case DRM_MODE_CONNECTOR_DisplayPort:8107 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;8108 link->link_enc = link_enc_cfg_get_link_enc(link);8109 ASSERT(link->link_enc);8110 if (link->link_enc)8111 aconnector->base.ycbcr_420_allowed =8112 link->link_enc->features.dp_ycbcr420_supported ? true : false;8113 break;8114 case DRM_MODE_CONNECTOR_DVID:8115 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;8116 break;8117 default:8118 break;8119 }8120 8121 drm_object_attach_property(&aconnector->base.base,8122 dm->ddev->mode_config.scaling_mode_property,8123 DRM_MODE_SCALE_NONE);8124 8125 drm_object_attach_property(&aconnector->base.base,8126 adev->mode_info.underscan_property,8127 UNDERSCAN_OFF);8128 drm_object_attach_property(&aconnector->base.base,8129 adev->mode_info.underscan_hborder_property,8130 0);8131 drm_object_attach_property(&aconnector->base.base,8132 adev->mode_info.underscan_vborder_property,8133 0);8134 8135 if (!aconnector->mst_root)8136 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);8137 8138 aconnector->base.state->max_bpc = 16;8139 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;8140 8141 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {8142 /* Content Type is currently only implemented for HDMI. */8143 drm_connector_attach_content_type_property(&aconnector->base);8144 }8145 8146 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {8147 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))8148 drm_connector_attach_colorspace_property(&aconnector->base);8149 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||8150 connector_type == DRM_MODE_CONNECTOR_eDP) {8151 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))8152 drm_connector_attach_colorspace_property(&aconnector->base);8153 }8154 8155 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||8156 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||8157 connector_type == DRM_MODE_CONNECTOR_eDP) {8158 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);8159 8160 if (!aconnector->mst_root)8161 drm_connector_attach_vrr_capable_property(&aconnector->base);8162 8163 if (adev->dm.hdcp_workqueue)8164 drm_connector_attach_content_protection_property(&aconnector->base, true);8165 }8166}8167 8168static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,8169 struct i2c_msg *msgs, int num)8170{8171 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);8172 struct ddc_service *ddc_service = i2c->ddc_service;8173 struct i2c_command cmd;8174 int i;8175 int result = -EIO;8176 8177 if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported)8178 return result;8179 8180 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);8181 8182 if (!cmd.payloads)8183 return result;8184 8185 cmd.number_of_payloads = num;8186 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;8187 cmd.speed = 100;8188 8189 for (i = 0; i < num; i++) {8190 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);8191 cmd.payloads[i].address = msgs[i].addr;8192 cmd.payloads[i].length = msgs[i].len;8193 cmd.payloads[i].data = msgs[i].buf;8194 }8195 8196 if (dc_submit_i2c(8197 ddc_service->ctx->dc,8198 ddc_service->link->link_index,8199 &cmd))8200 result = num;8201 8202 kfree(cmd.payloads);8203 return result;8204}8205 8206static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)8207{8208 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;8209}8210 8211static const struct i2c_algorithm amdgpu_dm_i2c_algo = {8212 .master_xfer = amdgpu_dm_i2c_xfer,8213 .functionality = amdgpu_dm_i2c_func,8214};8215 8216static struct amdgpu_i2c_adapter *8217create_i2c(struct ddc_service *ddc_service,8218 int link_index,8219 int *res)8220{8221 struct amdgpu_device *adev = ddc_service->ctx->driver_context;8222 struct amdgpu_i2c_adapter *i2c;8223 8224 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);8225 if (!i2c)8226 return NULL;8227 i2c->base.owner = THIS_MODULE;8228 i2c->base.dev.parent = &adev->pdev->dev;8229 i2c->base.algo = &amdgpu_dm_i2c_algo;8230 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);8231 i2c_set_adapdata(&i2c->base, i2c);8232 i2c->ddc_service = ddc_service;8233 8234 return i2c;8235}8236 8237 8238/*8239 * Note: this function assumes that dc_link_detect() was called for the8240 * dc_link which will be represented by this aconnector.8241 */8242static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,8243 struct amdgpu_dm_connector *aconnector,8244 u32 link_index,8245 struct amdgpu_encoder *aencoder)8246{8247 int res = 0;8248 int connector_type;8249 struct dc *dc = dm->dc;8250 struct dc_link *link = dc_get_link_at_index(dc, link_index);8251 struct amdgpu_i2c_adapter *i2c;8252 8253 /* Not needed for writeback connector */8254 link->priv = aconnector;8255 8256 8257 i2c = create_i2c(link->ddc, link->link_index, &res);8258 if (!i2c) {8259 DRM_ERROR("Failed to create i2c adapter data\n");8260 return -ENOMEM;8261 }8262 8263 aconnector->i2c = i2c;8264 res = i2c_add_adapter(&i2c->base);8265 8266 if (res) {8267 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);8268 goto out_free;8269 }8270 8271 connector_type = to_drm_connector_type(link->connector_signal);8272 8273 res = drm_connector_init_with_ddc(8274 dm->ddev,8275 &aconnector->base,8276 &amdgpu_dm_connector_funcs,8277 connector_type,8278 &i2c->base);8279 8280 if (res) {8281 DRM_ERROR("connector_init failed\n");8282 aconnector->connector_id = -1;8283 goto out_free;8284 }8285 8286 drm_connector_helper_add(8287 &aconnector->base,8288 &amdgpu_dm_connector_helper_funcs);8289 8290 amdgpu_dm_connector_init_helper(8291 dm,8292 aconnector,8293 connector_type,8294 link,8295 link_index);8296 8297 drm_connector_attach_encoder(8298 &aconnector->base, &aencoder->base);8299 8300 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort8301 || connector_type == DRM_MODE_CONNECTOR_eDP)8302 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);8303 8304out_free:8305 if (res) {8306 kfree(i2c);8307 aconnector->i2c = NULL;8308 }8309 return res;8310}8311 8312int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)8313{8314 switch (adev->mode_info.num_crtc) {8315 case 1:8316 return 0x1;8317 case 2:8318 return 0x3;8319 case 3:8320 return 0x7;8321 case 4:8322 return 0xf;8323 case 5:8324 return 0x1f;8325 case 6:8326 default:8327 return 0x3f;8328 }8329}8330 8331static int amdgpu_dm_encoder_init(struct drm_device *dev,8332 struct amdgpu_encoder *aencoder,8333 uint32_t link_index)8334{8335 struct amdgpu_device *adev = drm_to_adev(dev);8336 8337 int res = drm_encoder_init(dev,8338 &aencoder->base,8339 &amdgpu_dm_encoder_funcs,8340 DRM_MODE_ENCODER_TMDS,8341 NULL);8342 8343 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);8344 8345 if (!res)8346 aencoder->encoder_id = link_index;8347 else8348 aencoder->encoder_id = -1;8349 8350 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);8351 8352 return res;8353}8354 8355static void manage_dm_interrupts(struct amdgpu_device *adev,8356 struct amdgpu_crtc *acrtc,8357 struct dm_crtc_state *acrtc_state)8358{8359 /*8360 * We have no guarantee that the frontend index maps to the same8361 * backend index - some even map to more than one.8362 *8363 * TODO: Use a different interrupt or check DC itself for the mapping.8364 */8365 int irq_type =8366 amdgpu_display_crtc_idx_to_irq_type(8367 adev,8368 acrtc->crtc_id);8369 struct drm_vblank_crtc_config config = {0};8370 struct dc_crtc_timing *timing;8371 int offdelay;8372 8373 if (acrtc_state) {8374 if (amdgpu_ip_version(adev, DCE_HWIP, 0) <8375 IP_VERSION(3, 5, 0) ||8376 acrtc_state->stream->link->psr_settings.psr_version <8377 DC_PSR_VERSION_UNSUPPORTED ||8378 !(adev->flags & AMD_IS_APU)) {8379 timing = &acrtc_state->stream->timing;8380 8381 /* at least 2 frames */8382 offdelay = DIV64_U64_ROUND_UP((u64)20 *8383 timing->v_total *8384 timing->h_total,8385 timing->pix_clk_100hz);8386 8387 config.offdelay_ms = offdelay ?: 30;8388 } else {8389 config.disable_immediate = true;8390 }8391 8392 drm_crtc_vblank_on_config(&acrtc->base,8393 &config);8394 8395 amdgpu_irq_get(8396 adev,8397 &adev->pageflip_irq,8398 irq_type);8399#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)8400 amdgpu_irq_get(8401 adev,8402 &adev->vline0_irq,8403 irq_type);8404#endif8405 } else {8406#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)8407 amdgpu_irq_put(8408 adev,8409 &adev->vline0_irq,8410 irq_type);8411#endif8412 amdgpu_irq_put(8413 adev,8414 &adev->pageflip_irq,8415 irq_type);8416 drm_crtc_vblank_off(&acrtc->base);8417 }8418}8419 8420static void dm_update_pflip_irq_state(struct amdgpu_device *adev,8421 struct amdgpu_crtc *acrtc)8422{8423 int irq_type =8424 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);8425 8426 /**8427 * This reads the current state for the IRQ and force reapplies8428 * the setting to hardware.8429 */8430 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);8431}8432 8433static bool8434is_scaling_state_different(const struct dm_connector_state *dm_state,8435 const struct dm_connector_state *old_dm_state)8436{8437 if (dm_state->scaling != old_dm_state->scaling)8438 return true;8439 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {8440 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)8441 return true;8442 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {8443 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)8444 return true;8445 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||8446 dm_state->underscan_vborder != old_dm_state->underscan_vborder)8447 return true;8448 return false;8449}8450 8451static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,8452 struct drm_crtc_state *old_crtc_state,8453 struct drm_connector_state *new_conn_state,8454 struct drm_connector_state *old_conn_state,8455 const struct drm_connector *connector,8456 struct hdcp_workqueue *hdcp_w)8457{8458 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);8459 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);8460 8461 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",8462 connector->index, connector->status, connector->dpms);8463 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",8464 old_conn_state->content_protection, new_conn_state->content_protection);8465 8466 if (old_crtc_state)8467 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",8468 old_crtc_state->enable,8469 old_crtc_state->active,8470 old_crtc_state->mode_changed,8471 old_crtc_state->active_changed,8472 old_crtc_state->connectors_changed);8473 8474 if (new_crtc_state)8475 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",8476 new_crtc_state->enable,8477 new_crtc_state->active,8478 new_crtc_state->mode_changed,8479 new_crtc_state->active_changed,8480 new_crtc_state->connectors_changed);8481 8482 /* hdcp content type change */8483 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&8484 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {8485 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;8486 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);8487 return true;8488 }8489 8490 /* CP is being re enabled, ignore this */8491 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&8492 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {8493 if (new_crtc_state && new_crtc_state->mode_changed) {8494 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;8495 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);8496 return true;8497 }8498 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;8499 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);8500 return false;8501 }8502 8503 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED8504 *8505 * Handles: UNDESIRED -> ENABLED8506 */8507 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&8508 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)8509 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;8510 8511 /* Stream removed and re-enabled8512 *8513 * Can sometimes overlap with the HPD case,8514 * thus set update_hdcp to false to avoid8515 * setting HDCP multiple times.8516 *8517 * Handles: DESIRED -> DESIRED (Special case)8518 */8519 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&8520 new_conn_state->crtc && new_conn_state->crtc->enabled &&8521 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {8522 dm_con_state->update_hdcp = false;8523 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",8524 __func__);8525 return true;8526 }8527 8528 /* Hot-plug, headless s3, dpms8529 *8530 * Only start HDCP if the display is connected/enabled.8531 * update_hdcp flag will be set to false until the next8532 * HPD comes in.8533 *8534 * Handles: DESIRED -> DESIRED (Special case)8535 */8536 if (dm_con_state->update_hdcp &&8537 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&8538 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {8539 dm_con_state->update_hdcp = false;8540 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",8541 __func__);8542 return true;8543 }8544 8545 if (old_conn_state->content_protection == new_conn_state->content_protection) {8546 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {8547 if (new_crtc_state && new_crtc_state->mode_changed) {8548 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",8549 __func__);8550 return true;8551 }8552 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",8553 __func__);8554 return false;8555 }8556 8557 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);8558 return false;8559 }8560 8561 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {8562 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",8563 __func__);8564 return true;8565 }8566 8567 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);8568 return false;8569}8570 8571static void remove_stream(struct amdgpu_device *adev,8572 struct amdgpu_crtc *acrtc,8573 struct dc_stream_state *stream)8574{8575 /* this is the update mode case */8576 8577 acrtc->otg_inst = -1;8578 acrtc->enabled = false;8579}8580 8581static void prepare_flip_isr(struct amdgpu_crtc *acrtc)8582{8583 8584 assert_spin_locked(&acrtc->base.dev->event_lock);8585 WARN_ON(acrtc->event);8586 8587 acrtc->event = acrtc->base.state->event;8588 8589 /* Set the flip status */8590 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;8591 8592 /* Mark this event as consumed */8593 acrtc->base.state->event = NULL;8594 8595 drm_dbg_state(acrtc->base.dev,8596 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",8597 acrtc->crtc_id);8598}8599 8600static void update_freesync_state_on_stream(8601 struct amdgpu_display_manager *dm,8602 struct dm_crtc_state *new_crtc_state,8603 struct dc_stream_state *new_stream,8604 struct dc_plane_state *surface,8605 u32 flip_timestamp_in_us)8606{8607 struct mod_vrr_params vrr_params;8608 struct dc_info_packet vrr_infopacket = {0};8609 struct amdgpu_device *adev = dm->adev;8610 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);8611 unsigned long flags;8612 bool pack_sdp_v1_3 = false;8613 struct amdgpu_dm_connector *aconn;8614 enum vrr_packet_type packet_type = PACKET_TYPE_VRR;8615 8616 if (!new_stream)8617 return;8618 8619 /*8620 * TODO: Determine why min/max totals and vrefresh can be 0 here.8621 * For now it's sufficient to just guard against these conditions.8622 */8623 8624 if (!new_stream->timing.h_total || !new_stream->timing.v_total)8625 return;8626 8627 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);8628 vrr_params = acrtc->dm_irq_params.vrr_params;8629 8630 if (surface) {8631 mod_freesync_handle_preflip(8632 dm->freesync_module,8633 surface,8634 new_stream,8635 flip_timestamp_in_us,8636 &vrr_params);8637 8638 if (adev->family < AMDGPU_FAMILY_AI &&8639 amdgpu_dm_crtc_vrr_active(new_crtc_state)) {8640 mod_freesync_handle_v_update(dm->freesync_module,8641 new_stream, &vrr_params);8642 8643 /* Need to call this before the frame ends. */8644 dc_stream_adjust_vmin_vmax(dm->dc,8645 new_crtc_state->stream,8646 &vrr_params.adjust);8647 }8648 }8649 8650 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;8651 8652 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {8653 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;8654 8655 if (aconn->vsdb_info.amd_vsdb_version == 1)8656 packet_type = PACKET_TYPE_FS_V1;8657 else if (aconn->vsdb_info.amd_vsdb_version == 2)8658 packet_type = PACKET_TYPE_FS_V2;8659 else if (aconn->vsdb_info.amd_vsdb_version == 3)8660 packet_type = PACKET_TYPE_FS_V3;8661 8662 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,8663 &new_stream->adaptive_sync_infopacket);8664 }8665 8666 mod_freesync_build_vrr_infopacket(8667 dm->freesync_module,8668 new_stream,8669 &vrr_params,8670 packet_type,8671 TRANSFER_FUNC_UNKNOWN,8672 &vrr_infopacket,8673 pack_sdp_v1_3);8674 8675 new_crtc_state->freesync_vrr_info_changed |=8676 (memcmp(&new_crtc_state->vrr_infopacket,8677 &vrr_infopacket,8678 sizeof(vrr_infopacket)) != 0);8679 8680 acrtc->dm_irq_params.vrr_params = vrr_params;8681 new_crtc_state->vrr_infopacket = vrr_infopacket;8682 8683 new_stream->vrr_infopacket = vrr_infopacket;8684 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);8685 8686 if (new_crtc_state->freesync_vrr_info_changed)8687 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",8688 new_crtc_state->base.crtc->base.id,8689 (int)new_crtc_state->base.vrr_enabled,8690 (int)vrr_params.state);8691 8692 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);8693}8694 8695static void update_stream_irq_parameters(8696 struct amdgpu_display_manager *dm,8697 struct dm_crtc_state *new_crtc_state)8698{8699 struct dc_stream_state *new_stream = new_crtc_state->stream;8700 struct mod_vrr_params vrr_params;8701 struct mod_freesync_config config = new_crtc_state->freesync_config;8702 struct amdgpu_device *adev = dm->adev;8703 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);8704 unsigned long flags;8705 8706 if (!new_stream)8707 return;8708 8709 /*8710 * TODO: Determine why min/max totals and vrefresh can be 0 here.8711 * For now it's sufficient to just guard against these conditions.8712 */8713 if (!new_stream->timing.h_total || !new_stream->timing.v_total)8714 return;8715 8716 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);8717 vrr_params = acrtc->dm_irq_params.vrr_params;8718 8719 if (new_crtc_state->vrr_supported &&8720 config.min_refresh_in_uhz &&8721 config.max_refresh_in_uhz) {8722 /*8723 * if freesync compatible mode was set, config.state will be set8724 * in atomic check8725 */8726 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&8727 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||8728 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {8729 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;8730 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;8731 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;8732 vrr_params.state = VRR_STATE_ACTIVE_FIXED;8733 } else {8734 config.state = new_crtc_state->base.vrr_enabled ?8735 VRR_STATE_ACTIVE_VARIABLE :8736 VRR_STATE_INACTIVE;8737 }8738 } else {8739 config.state = VRR_STATE_UNSUPPORTED;8740 }8741 8742 mod_freesync_build_vrr_params(dm->freesync_module,8743 new_stream,8744 &config, &vrr_params);8745 8746 new_crtc_state->freesync_config = config;8747 /* Copy state for access from DM IRQ handler */8748 acrtc->dm_irq_params.freesync_config = config;8749 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;8750 acrtc->dm_irq_params.vrr_params = vrr_params;8751 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);8752}8753 8754static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,8755 struct dm_crtc_state *new_state)8756{8757 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);8758 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);8759 8760 if (!old_vrr_active && new_vrr_active) {8761 /* Transition VRR inactive -> active:8762 * While VRR is active, we must not disable vblank irq, as a8763 * reenable after disable would compute bogus vblank/pflip8764 * timestamps if it likely happened inside display front-porch.8765 *8766 * We also need vupdate irq for the actual core vblank handling8767 * at end of vblank.8768 */8769 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);8770 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);8771 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",8772 __func__, new_state->base.crtc->base.id);8773 } else if (old_vrr_active && !new_vrr_active) {8774 /* Transition VRR active -> inactive:8775 * Allow vblank irq disable again for fixed refresh rate.8776 */8777 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);8778 drm_crtc_vblank_put(new_state->base.crtc);8779 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",8780 __func__, new_state->base.crtc->base.id);8781 }8782}8783 8784static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)8785{8786 struct drm_plane *plane;8787 struct drm_plane_state *old_plane_state;8788 int i;8789 8790 /*8791 * TODO: Make this per-stream so we don't issue redundant updates for8792 * commits with multiple streams.8793 */8794 for_each_old_plane_in_state(state, plane, old_plane_state, i)8795 if (plane->type == DRM_PLANE_TYPE_CURSOR)8796 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);8797}8798 8799static inline uint32_t get_mem_type(struct drm_framebuffer *fb)8800{8801 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);8802 8803 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;8804}8805 8806static void amdgpu_dm_update_cursor(struct drm_plane *plane,8807 struct drm_plane_state *old_plane_state,8808 struct dc_stream_update *update)8809{8810 struct amdgpu_device *adev = drm_to_adev(plane->dev);8811 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);8812 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;8813 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;8814 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);8815 uint64_t address = afb ? afb->address : 0;8816 struct dc_cursor_position position = {0};8817 struct dc_cursor_attributes attributes;8818 int ret;8819 8820 if (!plane->state->fb && !old_plane_state->fb)8821 return;8822 8823 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n",8824 amdgpu_crtc->crtc_id, plane->state->crtc_w,8825 plane->state->crtc_h);8826 8827 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position);8828 if (ret)8829 return;8830 8831 if (!position.enable) {8832 /* turn off cursor */8833 if (crtc_state && crtc_state->stream) {8834 dc_stream_set_cursor_position(crtc_state->stream,8835 &position);8836 update->cursor_position = &crtc_state->stream->cursor_position;8837 }8838 return;8839 }8840 8841 amdgpu_crtc->cursor_width = plane->state->crtc_w;8842 amdgpu_crtc->cursor_height = plane->state->crtc_h;8843 8844 memset(&attributes, 0, sizeof(attributes));8845 attributes.address.high_part = upper_32_bits(address);8846 attributes.address.low_part = lower_32_bits(address);8847 attributes.width = plane->state->crtc_w;8848 attributes.height = plane->state->crtc_h;8849 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;8850 attributes.rotation_angle = 0;8851 attributes.attribute_flags.value = 0;8852 8853 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM8854 * legacy gamma setup.8855 */8856 if (crtc_state->cm_is_degamma_srgb &&8857 adev->dm.dc->caps.color.dpp.gamma_corr)8858 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;8859 8860 if (afb)8861 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0];8862 8863 if (crtc_state->stream) {8864 if (!dc_stream_set_cursor_attributes(crtc_state->stream,8865 &attributes))8866 DRM_ERROR("DC failed to set cursor attributes\n");8867 8868 update->cursor_attributes = &crtc_state->stream->cursor_attributes;8869 8870 if (!dc_stream_set_cursor_position(crtc_state->stream,8871 &position))8872 DRM_ERROR("DC failed to set cursor position\n");8873 8874 update->cursor_position = &crtc_state->stream->cursor_position;8875 }8876}8877 8878static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,8879 const struct dm_crtc_state *acrtc_state,8880 const u64 current_ts)8881{8882 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;8883 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;8884 struct amdgpu_dm_connector *aconn =8885 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;8886 8887 if (acrtc_state->update_type > UPDATE_TYPE_FAST) {8888 if (pr->config.replay_supported && !pr->replay_feature_enabled)8889 amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);8890 else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&8891 !psr->psr_feature_enabled)8892 if (!aconn->disallow_edp_enter_psr)8893 amdgpu_dm_link_setup_psr(acrtc_state->stream);8894 }8895 8896 /* Decrement skip count when SR is enabled and we're doing fast updates. */8897 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&8898 (psr->psr_feature_enabled || pr->config.replay_supported)) {8899 if (aconn->sr_skip_count > 0)8900 aconn->sr_skip_count--;8901 8902 /* Allow SR when skip count is 0. */8903 acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count;8904 8905 /*8906 * If sink supports PSR SU/Panel Replay, there is no need to rely on8907 * a vblank event disable request to enable PSR/RP. PSR SU/RP8908 * can be enabled immediately once OS demonstrates an8909 * adequate number of fast atomic commits to notify KMD8910 * of update events. See `vblank_control_worker()`.8911 */8912 if (acrtc_attach->dm_irq_params.allow_sr_entry &&8913#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY8914 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&8915#endif8916 (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {8917 if (pr->replay_feature_enabled && !pr->replay_allow_active)8918 amdgpu_dm_replay_enable(acrtc_state->stream, true);8919 if (psr->psr_version >= DC_PSR_VERSION_SU_1 &&8920 !psr->psr_allow_active && !aconn->disallow_edp_enter_psr)8921 amdgpu_dm_psr_enable(acrtc_state->stream);8922 }8923 } else {8924 acrtc_attach->dm_irq_params.allow_sr_entry = false;8925 }8926}8927 8928static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,8929 struct drm_device *dev,8930 struct amdgpu_display_manager *dm,8931 struct drm_crtc *pcrtc,8932 bool wait_for_vblank)8933{8934 u32 i;8935 u64 timestamp_ns = ktime_get_ns();8936 struct drm_plane *plane;8937 struct drm_plane_state *old_plane_state, *new_plane_state;8938 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);8939 struct drm_crtc_state *new_pcrtc_state =8940 drm_atomic_get_new_crtc_state(state, pcrtc);8941 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);8942 struct dm_crtc_state *dm_old_crtc_state =8943 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));8944 int planes_count = 0, vpos, hpos;8945 unsigned long flags;8946 u32 target_vblank, last_flip_vblank;8947 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);8948 bool cursor_update = false;8949 bool pflip_present = false;8950 bool dirty_rects_changed = false;8951 bool updated_planes_and_streams = false;8952 struct {8953 struct dc_surface_update surface_updates[MAX_SURFACES];8954 struct dc_plane_info plane_infos[MAX_SURFACES];8955 struct dc_scaling_info scaling_infos[MAX_SURFACES];8956 struct dc_flip_addrs flip_addrs[MAX_SURFACES];8957 struct dc_stream_update stream_update;8958 } *bundle;8959 8960 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);8961 8962 if (!bundle) {8963 drm_err(dev, "Failed to allocate update bundle\n");8964 goto cleanup;8965 }8966 8967 /*8968 * Disable the cursor first if we're disabling all the planes.8969 * It'll remain on the screen after the planes are re-enabled8970 * if we don't.8971 *8972 * If the cursor is transitioning from native to overlay mode, the8973 * native cursor needs to be disabled first.8974 */8975 if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE &&8976 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) {8977 struct dc_cursor_position cursor_position = {0};8978 8979 if (!dc_stream_set_cursor_position(acrtc_state->stream,8980 &cursor_position))8981 drm_err(dev, "DC failed to disable native cursor\n");8982 8983 bundle->stream_update.cursor_position =8984 &acrtc_state->stream->cursor_position;8985 }8986 8987 if (acrtc_state->active_planes == 0 &&8988 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE)8989 amdgpu_dm_commit_cursors(state);8990 8991 /* update planes when needed */8992 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {8993 struct drm_crtc *crtc = new_plane_state->crtc;8994 struct drm_crtc_state *new_crtc_state;8995 struct drm_framebuffer *fb = new_plane_state->fb;8996 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;8997 bool plane_needs_flip;8998 struct dc_plane_state *dc_plane;8999 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);9000 9001 /* Cursor plane is handled after stream updates */9002 if (plane->type == DRM_PLANE_TYPE_CURSOR &&9003 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) {9004 if ((fb && crtc == pcrtc) ||9005 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) {9006 cursor_update = true;9007 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0)9008 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update);9009 }9010 9011 continue;9012 }9013 9014 if (!fb || !crtc || pcrtc != crtc)9015 continue;9016 9017 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);9018 if (!new_crtc_state->active)9019 continue;9020 9021 dc_plane = dm_new_plane_state->dc_state;9022 if (!dc_plane)9023 continue;9024 9025 bundle->surface_updates[planes_count].surface = dc_plane;9026 if (new_pcrtc_state->color_mgmt_changed) {9027 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction;9028 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func;9029 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;9030 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult;9031 bundle->surface_updates[planes_count].func_shaper = &dc_plane->in_shaper_func;9032 bundle->surface_updates[planes_count].lut3d_func = &dc_plane->lut3d_func;9033 bundle->surface_updates[planes_count].blend_tf = &dc_plane->blend_tf;9034 }9035 9036 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,9037 &bundle->scaling_infos[planes_count]);9038 9039 bundle->surface_updates[planes_count].scaling_info =9040 &bundle->scaling_infos[planes_count];9041 9042 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;9043 9044 pflip_present = pflip_present || plane_needs_flip;9045 9046 if (!plane_needs_flip) {9047 planes_count += 1;9048 continue;9049 }9050 9051 fill_dc_plane_info_and_addr(9052 dm->adev, new_plane_state,9053 afb->tiling_flags,9054 &bundle->plane_infos[planes_count],9055 &bundle->flip_addrs[planes_count].address,9056 afb->tmz_surface, false);9057 9058 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",9059 new_plane_state->plane->index,9060 bundle->plane_infos[planes_count].dcc.enable);9061 9062 bundle->surface_updates[planes_count].plane_info =9063 &bundle->plane_infos[planes_count];9064 9065 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||9066 acrtc_state->stream->link->replay_settings.replay_feature_enabled) {9067 fill_dc_dirty_rects(plane, old_plane_state,9068 new_plane_state, new_crtc_state,9069 &bundle->flip_addrs[planes_count],9070 acrtc_state->stream->link->psr_settings.psr_version ==9071 DC_PSR_VERSION_SU_1,9072 &dirty_rects_changed);9073 9074 /*9075 * If the dirty regions changed, PSR-SU need to be disabled temporarily9076 * and enabled it again after dirty regions are stable to avoid video glitch.9077 * PSR-SU will be enabled in vblank_control_worker() if user pause the video9078 * during the PSR-SU was disabled.9079 */9080 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&9081 acrtc_attach->dm_irq_params.allow_sr_entry &&9082#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY9083 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&9084#endif9085 dirty_rects_changed) {9086 mutex_lock(&dm->dc_lock);9087 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =9088 timestamp_ns;9089 if (acrtc_state->stream->link->psr_settings.psr_allow_active)9090 amdgpu_dm_psr_disable(acrtc_state->stream);9091 mutex_unlock(&dm->dc_lock);9092 }9093 }9094 9095 /*9096 * Only allow immediate flips for fast updates that don't9097 * change memory domain, FB pitch, DCC state, rotation or9098 * mirroring.9099 *9100 * dm_crtc_helper_atomic_check() only accepts async flips with9101 * fast updates.9102 */9103 if (crtc->state->async_flip &&9104 (acrtc_state->update_type != UPDATE_TYPE_FAST ||9105 get_mem_type(old_plane_state->fb) != get_mem_type(fb)))9106 drm_warn_once(state->dev,9107 "[PLANE:%d:%s] async flip with non-fast update\n",9108 plane->base.id, plane->name);9109 9110 bundle->flip_addrs[planes_count].flip_immediate =9111 crtc->state->async_flip &&9112 acrtc_state->update_type == UPDATE_TYPE_FAST &&9113 get_mem_type(old_plane_state->fb) == get_mem_type(fb);9114 9115 timestamp_ns = ktime_get_ns();9116 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);9117 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];9118 bundle->surface_updates[planes_count].surface = dc_plane;9119 9120 if (!bundle->surface_updates[planes_count].surface) {9121 DRM_ERROR("No surface for CRTC: id=%d\n",9122 acrtc_attach->crtc_id);9123 continue;9124 }9125 9126 if (plane == pcrtc->primary)9127 update_freesync_state_on_stream(9128 dm,9129 acrtc_state,9130 acrtc_state->stream,9131 dc_plane,9132 bundle->flip_addrs[planes_count].flip_timestamp_in_us);9133 9134 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",9135 __func__,9136 bundle->flip_addrs[planes_count].address.grph.addr.high_part,9137 bundle->flip_addrs[planes_count].address.grph.addr.low_part);9138 9139 planes_count += 1;9140 9141 }9142 9143 if (pflip_present) {9144 if (!vrr_active) {9145 /* Use old throttling in non-vrr fixed refresh rate mode9146 * to keep flip scheduling based on target vblank counts9147 * working in a backwards compatible way, e.g., for9148 * clients using the GLX_OML_sync_control extension or9149 * DRI3/Present extension with defined target_msc.9150 */9151 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);9152 } else {9153 /* For variable refresh rate mode only:9154 * Get vblank of last completed flip to avoid > 1 vrr9155 * flips per video frame by use of throttling, but allow9156 * flip programming anywhere in the possibly large9157 * variable vrr vblank interval for fine-grained flip9158 * timing control and more opportunity to avoid stutter9159 * on late submission of flips.9160 */9161 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);9162 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;9163 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);9164 }9165 9166 target_vblank = last_flip_vblank + wait_for_vblank;9167 9168 /*9169 * Wait until we're out of the vertical blank period before the one9170 * targeted by the flip9171 */9172 while ((acrtc_attach->enabled &&9173 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,9174 0, &vpos, &hpos, NULL,9175 NULL, &pcrtc->hwmode)9176 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==9177 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&9178 (int)(target_vblank -9179 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {9180 usleep_range(1000, 1100);9181 }9182 9183 /**9184 * Prepare the flip event for the pageflip interrupt to handle.9185 *9186 * This only works in the case where we've already turned on the9187 * appropriate hardware blocks (eg. HUBP) so in the transition case9188 * from 0 -> n planes we have to skip a hardware generated event9189 * and rely on sending it from software.9190 */9191 if (acrtc_attach->base.state->event &&9192 acrtc_state->active_planes > 0) {9193 drm_crtc_vblank_get(pcrtc);9194 9195 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);9196 9197 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);9198 prepare_flip_isr(acrtc_attach);9199 9200 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);9201 }9202 9203 if (acrtc_state->stream) {9204 if (acrtc_state->freesync_vrr_info_changed)9205 bundle->stream_update.vrr_infopacket =9206 &acrtc_state->stream->vrr_infopacket;9207 }9208 } else if (cursor_update && acrtc_state->active_planes > 0) {9209 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);9210 if (acrtc_attach->base.state->event) {9211 drm_crtc_vblank_get(pcrtc);9212 acrtc_attach->event = acrtc_attach->base.state->event;9213 acrtc_attach->base.state->event = NULL;9214 }9215 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);9216 }9217 9218 /* Update the planes if changed or disable if we don't have any. */9219 if ((planes_count || acrtc_state->active_planes == 0) &&9220 acrtc_state->stream) {9221 /*9222 * If PSR or idle optimizations are enabled then flush out9223 * any pending work before hardware programming.9224 */9225 if (dm->vblank_control_workqueue)9226 flush_workqueue(dm->vblank_control_workqueue);9227 9228 bundle->stream_update.stream = acrtc_state->stream;9229 if (new_pcrtc_state->mode_changed) {9230 bundle->stream_update.src = acrtc_state->stream->src;9231 bundle->stream_update.dst = acrtc_state->stream->dst;9232 }9233 9234 if (new_pcrtc_state->color_mgmt_changed) {9235 /*9236 * TODO: This isn't fully correct since we've actually9237 * already modified the stream in place.9238 */9239 bundle->stream_update.gamut_remap =9240 &acrtc_state->stream->gamut_remap_matrix;9241 bundle->stream_update.output_csc_transform =9242 &acrtc_state->stream->csc_color_matrix;9243 bundle->stream_update.out_transfer_func =9244 &acrtc_state->stream->out_transfer_func;9245 bundle->stream_update.lut3d_func =9246 (struct dc_3dlut *) acrtc_state->stream->lut3d_func;9247 bundle->stream_update.func_shaper =9248 (struct dc_transfer_func *) acrtc_state->stream->func_shaper;9249 }9250 9251 acrtc_state->stream->abm_level = acrtc_state->abm_level;9252 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)9253 bundle->stream_update.abm_level = &acrtc_state->abm_level;9254 9255 mutex_lock(&dm->dc_lock);9256 if (acrtc_state->update_type > UPDATE_TYPE_FAST) {9257 if (acrtc_state->stream->link->replay_settings.replay_allow_active)9258 amdgpu_dm_replay_disable(acrtc_state->stream);9259 if (acrtc_state->stream->link->psr_settings.psr_allow_active)9260 amdgpu_dm_psr_disable(acrtc_state->stream);9261 }9262 mutex_unlock(&dm->dc_lock);9263 9264 /*9265 * If FreeSync state on the stream has changed then we need to9266 * re-adjust the min/max bounds now that DC doesn't handle this9267 * as part of commit.9268 */9269 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {9270 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);9271 dc_stream_adjust_vmin_vmax(9272 dm->dc, acrtc_state->stream,9273 &acrtc_attach->dm_irq_params.vrr_params.adjust);9274 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);9275 }9276 mutex_lock(&dm->dc_lock);9277 update_planes_and_stream_adapter(dm->dc,9278 acrtc_state->update_type,9279 planes_count,9280 acrtc_state->stream,9281 &bundle->stream_update,9282 bundle->surface_updates);9283 updated_planes_and_streams = true;9284 9285 /**9286 * Enable or disable the interrupts on the backend.9287 *9288 * Most pipes are put into power gating when unused.9289 *9290 * When power gating is enabled on a pipe we lose the9291 * interrupt enablement state when power gating is disabled.9292 *9293 * So we need to update the IRQ control state in hardware9294 * whenever the pipe turns on (since it could be previously9295 * power gated) or off (since some pipes can't be power gated9296 * on some ASICs).9297 */9298 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)9299 dm_update_pflip_irq_state(drm_to_adev(dev),9300 acrtc_attach);9301 9302 amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns);9303 mutex_unlock(&dm->dc_lock);9304 }9305 9306 /*9307 * Update cursor state *after* programming all the planes.9308 * This avoids redundant programming in the case where we're going9309 * to be disabling a single plane - those pipes are being disabled.9310 */9311 if (acrtc_state->active_planes &&9312 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) &&9313 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE)9314 amdgpu_dm_commit_cursors(state);9315 9316cleanup:9317 kfree(bundle);9318}9319 9320static void amdgpu_dm_commit_audio(struct drm_device *dev,9321 struct drm_atomic_state *state)9322{9323 struct amdgpu_device *adev = drm_to_adev(dev);9324 struct amdgpu_dm_connector *aconnector;9325 struct drm_connector *connector;9326 struct drm_connector_state *old_con_state, *new_con_state;9327 struct drm_crtc_state *new_crtc_state;9328 struct dm_crtc_state *new_dm_crtc_state;9329 const struct dc_stream_status *status;9330 int i, inst;9331 9332 /* Notify device removals. */9333 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {9334 if (old_con_state->crtc != new_con_state->crtc) {9335 /* CRTC changes require notification. */9336 goto notify;9337 }9338 9339 if (!new_con_state->crtc)9340 continue;9341 9342 new_crtc_state = drm_atomic_get_new_crtc_state(9343 state, new_con_state->crtc);9344 9345 if (!new_crtc_state)9346 continue;9347 9348 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))9349 continue;9350 9351notify:9352 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)9353 continue;9354 9355 aconnector = to_amdgpu_dm_connector(connector);9356 9357 mutex_lock(&adev->dm.audio_lock);9358 inst = aconnector->audio_inst;9359 aconnector->audio_inst = -1;9360 mutex_unlock(&adev->dm.audio_lock);9361 9362 amdgpu_dm_audio_eld_notify(adev, inst);9363 }9364 9365 /* Notify audio device additions. */9366 for_each_new_connector_in_state(state, connector, new_con_state, i) {9367 if (!new_con_state->crtc)9368 continue;9369 9370 new_crtc_state = drm_atomic_get_new_crtc_state(9371 state, new_con_state->crtc);9372 9373 if (!new_crtc_state)9374 continue;9375 9376 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))9377 continue;9378 9379 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);9380 if (!new_dm_crtc_state->stream)9381 continue;9382 9383 status = dc_stream_get_status(new_dm_crtc_state->stream);9384 if (!status)9385 continue;9386 9387 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)9388 continue;9389 9390 aconnector = to_amdgpu_dm_connector(connector);9391 9392 mutex_lock(&adev->dm.audio_lock);9393 inst = status->audio_inst;9394 aconnector->audio_inst = inst;9395 mutex_unlock(&adev->dm.audio_lock);9396 9397 amdgpu_dm_audio_eld_notify(adev, inst);9398 }9399}9400 9401/*9402 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC9403 * @crtc_state: the DRM CRTC state9404 * @stream_state: the DC stream state.9405 *9406 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring9407 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.9408 */9409static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,9410 struct dc_stream_state *stream_state)9411{9412 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);9413}9414 9415static void dm_clear_writeback(struct amdgpu_display_manager *dm,9416 struct dm_crtc_state *crtc_state)9417{9418 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);9419}9420 9421static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,9422 struct dc_state *dc_state)9423{9424 struct drm_device *dev = state->dev;9425 struct amdgpu_device *adev = drm_to_adev(dev);9426 struct amdgpu_display_manager *dm = &adev->dm;9427 struct drm_crtc *crtc;9428 struct drm_crtc_state *old_crtc_state, *new_crtc_state;9429 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;9430 struct drm_connector_state *old_con_state;9431 struct drm_connector *connector;9432 bool mode_set_reset_required = false;9433 u32 i;9434 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count};9435 bool set_backlight_level = false;9436 9437 /* Disable writeback */9438 for_each_old_connector_in_state(state, connector, old_con_state, i) {9439 struct dm_connector_state *dm_old_con_state;9440 struct amdgpu_crtc *acrtc;9441 9442 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)9443 continue;9444 9445 old_crtc_state = NULL;9446 9447 dm_old_con_state = to_dm_connector_state(old_con_state);9448 if (!dm_old_con_state->base.crtc)9449 continue;9450 9451 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc);9452 if (acrtc)9453 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);9454 9455 if (!acrtc || !acrtc->wb_enabled)9456 continue;9457 9458 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);9459 9460 dm_clear_writeback(dm, dm_old_crtc_state);9461 acrtc->wb_enabled = false;9462 }9463 9464 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,9465 new_crtc_state, i) {9466 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);9467 9468 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);9469 9470 if (old_crtc_state->active &&9471 (!new_crtc_state->active ||9472 drm_atomic_crtc_needs_modeset(new_crtc_state))) {9473 manage_dm_interrupts(adev, acrtc, NULL);9474 dc_stream_release(dm_old_crtc_state->stream);9475 }9476 }9477 9478 drm_atomic_helper_calc_timestamping_constants(state);9479 9480 /* update changed items */9481 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {9482 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);9483 9484 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);9485 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);9486 9487 drm_dbg_state(state->dev,9488 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",9489 acrtc->crtc_id,9490 new_crtc_state->enable,9491 new_crtc_state->active,9492 new_crtc_state->planes_changed,9493 new_crtc_state->mode_changed,9494 new_crtc_state->active_changed,9495 new_crtc_state->connectors_changed);9496 9497 /* Disable cursor if disabling crtc */9498 if (old_crtc_state->active && !new_crtc_state->active) {9499 struct dc_cursor_position position;9500 9501 memset(&position, 0, sizeof(position));9502 mutex_lock(&dm->dc_lock);9503 dc_exit_ips_for_hw_access(dm->dc);9504 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position);9505 mutex_unlock(&dm->dc_lock);9506 }9507 9508 /* Copy all transient state flags into dc state */9509 if (dm_new_crtc_state->stream) {9510 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,9511 dm_new_crtc_state->stream);9512 }9513 9514 /* handles headless hotplug case, updating new_state and9515 * aconnector as needed9516 */9517 9518 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {9519 9520 drm_dbg_atomic(dev,9521 "Atomic commit: SET crtc id %d: [%p]\n",9522 acrtc->crtc_id, acrtc);9523 9524 if (!dm_new_crtc_state->stream) {9525 /*9526 * this could happen because of issues with9527 * userspace notifications delivery.9528 * In this case userspace tries to set mode on9529 * display which is disconnected in fact.9530 * dc_sink is NULL in this case on aconnector.9531 * We expect reset mode will come soon.9532 *9533 * This can also happen when unplug is done9534 * during resume sequence ended9535 *9536 * In this case, we want to pretend we still9537 * have a sink to keep the pipe running so that9538 * hw state is consistent with the sw state9539 */9540 drm_dbg_atomic(dev,9541 "Failed to create new stream for crtc %d\n",9542 acrtc->base.base.id);9543 continue;9544 }9545 9546 if (dm_old_crtc_state->stream)9547 remove_stream(adev, acrtc, dm_old_crtc_state->stream);9548 9549 pm_runtime_get_noresume(dev->dev);9550 9551 acrtc->enabled = true;9552 acrtc->hw_mode = new_crtc_state->mode;9553 crtc->hwmode = new_crtc_state->mode;9554 mode_set_reset_required = true;9555 set_backlight_level = true;9556 } else if (modereset_required(new_crtc_state)) {9557 drm_dbg_atomic(dev,9558 "Atomic commit: RESET. crtc id %d:[%p]\n",9559 acrtc->crtc_id, acrtc);9560 /* i.e. reset mode */9561 if (dm_old_crtc_state->stream)9562 remove_stream(adev, acrtc, dm_old_crtc_state->stream);9563 9564 mode_set_reset_required = true;9565 }9566 } /* for_each_crtc_in_state() */9567 9568 /* if there mode set or reset, disable eDP PSR, Replay */9569 if (mode_set_reset_required) {9570 if (dm->vblank_control_workqueue)9571 flush_workqueue(dm->vblank_control_workqueue);9572 9573 amdgpu_dm_replay_disable_all(dm);9574 amdgpu_dm_psr_disable_all(dm);9575 }9576 9577 dm_enable_per_frame_crtc_master_sync(dc_state);9578 mutex_lock(&dm->dc_lock);9579 dc_exit_ips_for_hw_access(dm->dc);9580 WARN_ON(!dc_commit_streams(dm->dc, ¶ms));9581 9582 /* Allow idle optimization when vblank count is 0 for display off */9583 if (dm->active_vblank_irq_count == 0)9584 dc_allow_idle_optimizations(dm->dc, true);9585 mutex_unlock(&dm->dc_lock);9586 9587 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {9588 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);9589 9590 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);9591 9592 if (dm_new_crtc_state->stream != NULL) {9593 const struct dc_stream_status *status =9594 dc_stream_get_status(dm_new_crtc_state->stream);9595 9596 if (!status)9597 status = dc_state_get_stream_status(dc_state,9598 dm_new_crtc_state->stream);9599 if (!status)9600 drm_err(dev,9601 "got no status for stream %p on acrtc%p\n",9602 dm_new_crtc_state->stream, acrtc);9603 else9604 acrtc->otg_inst = status->primary_otg_inst;9605 }9606 }9607 9608 /* During boot up and resume the DC layer will reset the panel brightness9609 * to fix a flicker issue.9610 * It will cause the dm->actual_brightness is not the current panel brightness9611 * level. (the dm->brightness is the correct panel level)9612 * So we set the backlight level with dm->brightness value after set mode9613 */9614 if (set_backlight_level) {9615 for (i = 0; i < dm->num_of_edps; i++) {9616 if (dm->backlight_dev[i])9617 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);9618 }9619 }9620}9621 9622static void dm_set_writeback(struct amdgpu_display_manager *dm,9623 struct dm_crtc_state *crtc_state,9624 struct drm_connector *connector,9625 struct drm_connector_state *new_con_state)9626{9627 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector);9628 struct amdgpu_device *adev = dm->adev;9629 struct amdgpu_crtc *acrtc;9630 struct dc_writeback_info *wb_info;9631 struct pipe_ctx *pipe = NULL;9632 struct amdgpu_framebuffer *afb;9633 int i = 0;9634 9635 wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL);9636 if (!wb_info) {9637 DRM_ERROR("Failed to allocate wb_info\n");9638 return;9639 }9640 9641 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc);9642 if (!acrtc) {9643 DRM_ERROR("no amdgpu_crtc found\n");9644 kfree(wb_info);9645 return;9646 }9647 9648 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb);9649 if (!afb) {9650 DRM_ERROR("No amdgpu_framebuffer found\n");9651 kfree(wb_info);9652 return;9653 }9654 9655 for (i = 0; i < MAX_PIPES; i++) {9656 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {9657 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];9658 break;9659 }9660 }9661 9662 /* fill in wb_info */9663 wb_info->wb_enabled = true;9664 9665 wb_info->dwb_pipe_inst = 0;9666 wb_info->dwb_params.dwbscl_black_color = 0;9667 wb_info->dwb_params.hdr_mult = 0x1F000;9668 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS;9669 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;9670 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC;9671 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC;9672 9673 /* width & height from crtc */9674 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay;9675 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay;9676 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay;9677 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay;9678 9679 wb_info->dwb_params.cnv_params.crop_en = false;9680 wb_info->dwb_params.stereo_params.stereo_enabled = false;9681 9682 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits9683 wb_info->dwb_params.cnv_params.out_min_pix_val = 0;9684 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB;9685 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS;9686 9687 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444;9688 9689 wb_info->dwb_params.capture_rate = dwb_capture_rate_0;9690 9691 wb_info->dwb_params.scaler_taps.h_taps = 4;9692 wb_info->dwb_params.scaler_taps.v_taps = 4;9693 wb_info->dwb_params.scaler_taps.h_taps_c = 2;9694 wb_info->dwb_params.scaler_taps.v_taps_c = 2;9695 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING;9696 9697 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0];9698 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1];9699 9700 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) {9701 wb_info->mcif_buf_params.luma_address[i] = afb->address;9702 wb_info->mcif_buf_params.chroma_address[i] = 0;9703 }9704 9705 wb_info->mcif_buf_params.p_vmid = 1;9706 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) {9707 wb_info->mcif_warmup_params.start_address.quad_part = afb->address;9708 wb_info->mcif_warmup_params.region_size =9709 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height;9710 }9711 wb_info->mcif_warmup_params.p_vmid = 1;9712 wb_info->writeback_source_plane = pipe->plane_state;9713 9714 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info);9715 9716 acrtc->wb_pending = true;9717 acrtc->wb_conn = wb_conn;9718 drm_writeback_queue_job(wb_conn, new_con_state);9719}9720 9721/**9722 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.9723 * @state: The atomic state to commit9724 *9725 * This will tell DC to commit the constructed DC state from atomic_check,9726 * programming the hardware. Any failures here implies a hardware failure, since9727 * atomic check should have filtered anything non-kosher.9728 */9729static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)9730{9731 struct drm_device *dev = state->dev;9732 struct amdgpu_device *adev = drm_to_adev(dev);9733 struct amdgpu_display_manager *dm = &adev->dm;9734 struct dm_atomic_state *dm_state;9735 struct dc_state *dc_state = NULL;9736 u32 i, j;9737 struct drm_crtc *crtc;9738 struct drm_crtc_state *old_crtc_state, *new_crtc_state;9739 unsigned long flags;9740 bool wait_for_vblank = true;9741 struct drm_connector *connector;9742 struct drm_connector_state *old_con_state, *new_con_state;9743 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;9744 int crtc_disable_count = 0;9745 9746 trace_amdgpu_dm_atomic_commit_tail_begin(state);9747 9748 drm_atomic_helper_update_legacy_modeset_state(dev, state);9749 drm_dp_mst_atomic_wait_for_dependencies(state);9750 9751 dm_state = dm_atomic_get_new_state(state);9752 if (dm_state && dm_state->context) {9753 dc_state = dm_state->context;9754 amdgpu_dm_commit_streams(state, dc_state);9755 }9756 9757 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {9758 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);9759 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);9760 struct amdgpu_dm_connector *aconnector;9761 9762 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)9763 continue;9764 9765 aconnector = to_amdgpu_dm_connector(connector);9766 9767 if (!adev->dm.hdcp_workqueue)9768 continue;9769 9770 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);9771 9772 if (!connector)9773 continue;9774 9775 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",9776 connector->index, connector->status, connector->dpms);9777 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",9778 old_con_state->content_protection, new_con_state->content_protection);9779 9780 if (aconnector->dc_sink) {9781 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&9782 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {9783 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",9784 aconnector->dc_sink->edid_caps.display_name);9785 }9786 }9787 9788 new_crtc_state = NULL;9789 old_crtc_state = NULL;9790 9791 if (acrtc) {9792 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);9793 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);9794 }9795 9796 if (old_crtc_state)9797 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",9798 old_crtc_state->enable,9799 old_crtc_state->active,9800 old_crtc_state->mode_changed,9801 old_crtc_state->active_changed,9802 old_crtc_state->connectors_changed);9803 9804 if (new_crtc_state)9805 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",9806 new_crtc_state->enable,9807 new_crtc_state->active,9808 new_crtc_state->mode_changed,9809 new_crtc_state->active_changed,9810 new_crtc_state->connectors_changed);9811 }9812 9813 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {9814 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);9815 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);9816 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);9817 9818 if (!adev->dm.hdcp_workqueue)9819 continue;9820 9821 new_crtc_state = NULL;9822 old_crtc_state = NULL;9823 9824 if (acrtc) {9825 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);9826 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);9827 }9828 9829 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);9830 9831 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&9832 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {9833 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);9834 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;9835 dm_new_con_state->update_hdcp = true;9836 continue;9837 }9838 9839 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,9840 old_con_state, connector, adev->dm.hdcp_workqueue)) {9841 /* when display is unplugged from mst hub, connctor will9842 * be destroyed within dm_dp_mst_connector_destroy. connector9843 * hdcp perperties, like type, undesired, desired, enabled,9844 * will be lost. So, save hdcp properties into hdcp_work within9845 * amdgpu_dm_atomic_commit_tail. if the same display is9846 * plugged back with same display index, its hdcp properties9847 * will be retrieved from hdcp_work within dm_dp_mst_get_modes9848 */9849 9850 bool enable_encryption = false;9851 9852 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)9853 enable_encryption = true;9854 9855 if (aconnector->dc_link && aconnector->dc_sink &&9856 aconnector->dc_link->type == dc_connection_mst_branch) {9857 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;9858 struct hdcp_workqueue *hdcp_w =9859 &hdcp_work[aconnector->dc_link->link_index];9860 9861 hdcp_w->hdcp_content_type[connector->index] =9862 new_con_state->hdcp_content_type;9863 hdcp_w->content_protection[connector->index] =9864 new_con_state->content_protection;9865 }9866 9867 if (new_crtc_state && new_crtc_state->mode_changed &&9868 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)9869 enable_encryption = true;9870 9871 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);9872 9873 if (aconnector->dc_link)9874 hdcp_update_display(9875 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,9876 new_con_state->hdcp_content_type, enable_encryption);9877 }9878 }9879 9880 /* Handle connector state changes */9881 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {9882 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);9883 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);9884 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);9885 struct dc_surface_update *dummy_updates;9886 struct dc_stream_update stream_update;9887 struct dc_info_packet hdr_packet;9888 struct dc_stream_status *status = NULL;9889 bool abm_changed, hdr_changed, scaling_changed;9890 9891 memset(&stream_update, 0, sizeof(stream_update));9892 9893 if (acrtc) {9894 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);9895 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);9896 }9897 9898 /* Skip any modesets/resets */9899 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))9900 continue;9901 9902 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);9903 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);9904 9905 scaling_changed = is_scaling_state_different(dm_new_con_state,9906 dm_old_con_state);9907 9908 abm_changed = dm_new_crtc_state->abm_level !=9909 dm_old_crtc_state->abm_level;9910 9911 hdr_changed =9912 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);9913 9914 if (!scaling_changed && !abm_changed && !hdr_changed)9915 continue;9916 9917 stream_update.stream = dm_new_crtc_state->stream;9918 if (scaling_changed) {9919 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,9920 dm_new_con_state, dm_new_crtc_state->stream);9921 9922 stream_update.src = dm_new_crtc_state->stream->src;9923 stream_update.dst = dm_new_crtc_state->stream->dst;9924 }9925 9926 if (abm_changed) {9927 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;9928 9929 stream_update.abm_level = &dm_new_crtc_state->abm_level;9930 }9931 9932 if (hdr_changed) {9933 fill_hdr_info_packet(new_con_state, &hdr_packet);9934 stream_update.hdr_static_metadata = &hdr_packet;9935 }9936 9937 status = dc_stream_get_status(dm_new_crtc_state->stream);9938 9939 if (WARN_ON(!status))9940 continue;9941 9942 WARN_ON(!status->plane_count);9943 9944 /*9945 * TODO: DC refuses to perform stream updates without a dc_surface_update.9946 * Here we create an empty update on each plane.9947 * To fix this, DC should permit updating only stream properties.9948 */9949 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);9950 if (!dummy_updates) {9951 DRM_ERROR("Failed to allocate memory for dummy_updates.\n");9952 continue;9953 }9954 for (j = 0; j < status->plane_count; j++)9955 dummy_updates[j].surface = status->plane_states[0];9956 9957 sort(dummy_updates, status->plane_count,9958 sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL);9959 9960 mutex_lock(&dm->dc_lock);9961 dc_exit_ips_for_hw_access(dm->dc);9962 dc_update_planes_and_stream(dm->dc,9963 dummy_updates,9964 status->plane_count,9965 dm_new_crtc_state->stream,9966 &stream_update);9967 mutex_unlock(&dm->dc_lock);9968 kfree(dummy_updates);9969 }9970 9971 /**9972 * Enable interrupts for CRTCs that are newly enabled or went through9973 * a modeset. It was intentionally deferred until after the front end9974 * state was modified to wait until the OTG was on and so the IRQ9975 * handlers didn't access stale or invalid state.9976 */9977 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {9978 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);9979#ifdef CONFIG_DEBUG_FS9980 enum amdgpu_dm_pipe_crc_source cur_crc_src;9981#endif9982 /* Count number of newly disabled CRTCs for dropping PM refs later. */9983 if (old_crtc_state->active && !new_crtc_state->active)9984 crtc_disable_count++;9985 9986 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);9987 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);9988 9989 /* For freesync config update on crtc state and params for irq */9990 update_stream_irq_parameters(dm, dm_new_crtc_state);9991 9992#ifdef CONFIG_DEBUG_FS9993 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);9994 cur_crc_src = acrtc->dm_irq_params.crc_src;9995 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);9996#endif9997 9998 if (new_crtc_state->active &&9999 (!old_crtc_state->active ||10000 drm_atomic_crtc_needs_modeset(new_crtc_state))) {10001 dc_stream_retain(dm_new_crtc_state->stream);10002 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;10003 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state);10004 }10005 /* Handle vrr on->off / off->on transitions */10006 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);10007 10008#ifdef CONFIG_DEBUG_FS10009 if (new_crtc_state->active &&10010 (!old_crtc_state->active ||10011 drm_atomic_crtc_needs_modeset(new_crtc_state))) {10012 /**10013 * Frontend may have changed so reapply the CRC capture10014 * settings for the stream.10015 */10016 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {10017#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)10018 if (amdgpu_dm_crc_window_is_activated(crtc)) {10019 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);10020 acrtc->dm_irq_params.window_param.update_win = true;10021 10022 /**10023 * It takes 2 frames for HW to stably generate CRC when10024 * resuming from suspend, so we set skip_frame_cnt 2.10025 */10026 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;10027 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);10028 }10029#endif10030 if (amdgpu_dm_crtc_configure_crc_source(10031 crtc, dm_new_crtc_state, cur_crc_src))10032 drm_dbg_atomic(dev, "Failed to configure crc source");10033 }10034 }10035#endif10036 }10037 10038 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)10039 if (new_crtc_state->async_flip)10040 wait_for_vblank = false;10041 10042 /* update planes when needed per crtc*/10043 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {10044 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);10045 10046 if (dm_new_crtc_state->stream)10047 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);10048 }10049 10050 /* Enable writeback */10051 for_each_new_connector_in_state(state, connector, new_con_state, i) {10052 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);10053 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);10054 10055 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)10056 continue;10057 10058 if (!new_con_state->writeback_job)10059 continue;10060 10061 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);10062 10063 if (!new_crtc_state)10064 continue;10065 10066 if (acrtc->wb_enabled)10067 continue;10068 10069 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);10070 10071 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state);10072 acrtc->wb_enabled = true;10073 }10074 10075 /* Update audio instances for each connector. */10076 amdgpu_dm_commit_audio(dev, state);10077 10078 /* restore the backlight level */10079 for (i = 0; i < dm->num_of_edps; i++) {10080 if (dm->backlight_dev[i] &&10081 (dm->actual_brightness[i] != dm->brightness[i]))10082 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);10083 }10084 10085 /*10086 * send vblank event on all events not handled in flip and10087 * mark consumed event for drm_atomic_helper_commit_hw_done10088 */10089 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);10090 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {10091 10092 if (new_crtc_state->event)10093 drm_send_event_locked(dev, &new_crtc_state->event->base);10094 10095 new_crtc_state->event = NULL;10096 }10097 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);10098 10099 /* Signal HW programming completion */10100 drm_atomic_helper_commit_hw_done(state);10101 10102 if (wait_for_vblank)10103 drm_atomic_helper_wait_for_flip_done(dev, state);10104 10105 drm_atomic_helper_cleanup_planes(dev, state);10106 10107 /* Don't free the memory if we are hitting this as part of suspend.10108 * This way we don't free any memory during suspend; see10109 * amdgpu_bo_free_kernel(). The memory will be freed in the first10110 * non-suspend modeset or when the driver is torn down.10111 */10112 if (!adev->in_suspend) {10113 /* return the stolen vga memory back to VRAM */10114 if (!adev->mman.keep_stolen_vga_memory)10115 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);10116 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);10117 }10118 10119 /*10120 * Finally, drop a runtime PM reference for each newly disabled CRTC,10121 * so we can put the GPU into runtime suspend if we're not driving any10122 * displays anymore10123 */10124 for (i = 0; i < crtc_disable_count; i++)10125 pm_runtime_put_autosuspend(dev->dev);10126 pm_runtime_mark_last_busy(dev->dev);10127}10128 10129static int dm_force_atomic_commit(struct drm_connector *connector)10130{10131 int ret = 0;10132 struct drm_device *ddev = connector->dev;10133 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);10134 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);10135 struct drm_plane *plane = disconnected_acrtc->base.primary;10136 struct drm_connector_state *conn_state;10137 struct drm_crtc_state *crtc_state;10138 struct drm_plane_state *plane_state;10139 10140 if (!state)10141 return -ENOMEM;10142 10143 state->acquire_ctx = ddev->mode_config.acquire_ctx;10144 10145 /* Construct an atomic state to restore previous display setting */10146 10147 /*10148 * Attach connectors to drm_atomic_state10149 */10150 conn_state = drm_atomic_get_connector_state(state, connector);10151 10152 ret = PTR_ERR_OR_ZERO(conn_state);10153 if (ret)10154 goto out;10155 10156 /* Attach crtc to drm_atomic_state*/10157 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);10158 10159 ret = PTR_ERR_OR_ZERO(crtc_state);10160 if (ret)10161 goto out;10162 10163 /* force a restore */10164 crtc_state->mode_changed = true;10165 10166 /* Attach plane to drm_atomic_state */10167 plane_state = drm_atomic_get_plane_state(state, plane);10168 10169 ret = PTR_ERR_OR_ZERO(plane_state);10170 if (ret)10171 goto out;10172 10173 /* Call commit internally with the state we just constructed */10174 ret = drm_atomic_commit(state);10175 10176out:10177 drm_atomic_state_put(state);10178 if (ret)10179 DRM_ERROR("Restoring old state failed with %i\n", ret);10180 10181 return ret;10182}10183 10184/*10185 * This function handles all cases when set mode does not come upon hotplug.10186 * This includes when a display is unplugged then plugged back into the10187 * same port and when running without usermode desktop manager supprot10188 */10189void dm_restore_drm_connector_state(struct drm_device *dev,10190 struct drm_connector *connector)10191{10192 struct amdgpu_dm_connector *aconnector;10193 struct amdgpu_crtc *disconnected_acrtc;10194 struct dm_crtc_state *acrtc_state;10195 10196 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)10197 return;10198 10199 aconnector = to_amdgpu_dm_connector(connector);10200 10201 if (!aconnector->dc_sink || !connector->state || !connector->encoder)10202 return;10203 10204 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);10205 if (!disconnected_acrtc)10206 return;10207 10208 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);10209 if (!acrtc_state->stream)10210 return;10211 10212 /*10213 * If the previous sink is not released and different from the current,10214 * we deduce we are in a state where we can not rely on usermode call10215 * to turn on the display, so we do it here10216 */10217 if (acrtc_state->stream->sink != aconnector->dc_sink)10218 dm_force_atomic_commit(&aconnector->base);10219}10220 10221/*10222 * Grabs all modesetting locks to serialize against any blocking commits,10223 * Waits for completion of all non blocking commits.10224 */10225static int do_aquire_global_lock(struct drm_device *dev,10226 struct drm_atomic_state *state)10227{10228 struct drm_crtc *crtc;10229 struct drm_crtc_commit *commit;10230 long ret;10231 10232 /*10233 * Adding all modeset locks to aquire_ctx will10234 * ensure that when the framework release it the10235 * extra locks we are locking here will get released to10236 */10237 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);10238 if (ret)10239 return ret;10240 10241 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {10242 spin_lock(&crtc->commit_lock);10243 commit = list_first_entry_or_null(&crtc->commit_list,10244 struct drm_crtc_commit, commit_entry);10245 if (commit)10246 drm_crtc_commit_get(commit);10247 spin_unlock(&crtc->commit_lock);10248 10249 if (!commit)10250 continue;10251 10252 /*10253 * Make sure all pending HW programming completed and10254 * page flips done10255 */10256 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);10257 10258 if (ret > 0)10259 ret = wait_for_completion_interruptible_timeout(10260 &commit->flip_done, 10*HZ);10261 10262 if (ret == 0)10263 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",10264 crtc->base.id, crtc->name);10265 10266 drm_crtc_commit_put(commit);10267 }10268 10269 return ret < 0 ? ret : 0;10270}10271 10272static void get_freesync_config_for_crtc(10273 struct dm_crtc_state *new_crtc_state,10274 struct dm_connector_state *new_con_state)10275{10276 struct mod_freesync_config config = {0};10277 struct amdgpu_dm_connector *aconnector;10278 struct drm_display_mode *mode = &new_crtc_state->base.mode;10279 int vrefresh = drm_mode_vrefresh(mode);10280 bool fs_vid_mode = false;10281 10282 if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)10283 return;10284 10285 aconnector = to_amdgpu_dm_connector(new_con_state->base.connector);10286 10287 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&10288 vrefresh >= aconnector->min_vfreq &&10289 vrefresh <= aconnector->max_vfreq;10290 10291 if (new_crtc_state->vrr_supported) {10292 new_crtc_state->stream->ignore_msa_timing_param = true;10293 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;10294 10295 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;10296 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;10297 config.vsif_supported = true;10298 config.btr = true;10299 10300 if (fs_vid_mode) {10301 config.state = VRR_STATE_ACTIVE_FIXED;10302 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;10303 goto out;10304 } else if (new_crtc_state->base.vrr_enabled) {10305 config.state = VRR_STATE_ACTIVE_VARIABLE;10306 } else {10307 config.state = VRR_STATE_INACTIVE;10308 }10309 }10310out:10311 new_crtc_state->freesync_config = config;10312}10313 10314static void reset_freesync_config_for_crtc(10315 struct dm_crtc_state *new_crtc_state)10316{10317 new_crtc_state->vrr_supported = false;10318 10319 memset(&new_crtc_state->vrr_infopacket, 0,10320 sizeof(new_crtc_state->vrr_infopacket));10321}10322 10323static bool10324is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,10325 struct drm_crtc_state *new_crtc_state)10326{10327 const struct drm_display_mode *old_mode, *new_mode;10328 10329 if (!old_crtc_state || !new_crtc_state)10330 return false;10331 10332 old_mode = &old_crtc_state->mode;10333 new_mode = &new_crtc_state->mode;10334 10335 if (old_mode->clock == new_mode->clock &&10336 old_mode->hdisplay == new_mode->hdisplay &&10337 old_mode->vdisplay == new_mode->vdisplay &&10338 old_mode->htotal == new_mode->htotal &&10339 old_mode->vtotal != new_mode->vtotal &&10340 old_mode->hsync_start == new_mode->hsync_start &&10341 old_mode->vsync_start != new_mode->vsync_start &&10342 old_mode->hsync_end == new_mode->hsync_end &&10343 old_mode->vsync_end != new_mode->vsync_end &&10344 old_mode->hskew == new_mode->hskew &&10345 old_mode->vscan == new_mode->vscan &&10346 (old_mode->vsync_end - old_mode->vsync_start) ==10347 (new_mode->vsync_end - new_mode->vsync_start))10348 return true;10349 10350 return false;10351}10352 10353static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)10354{10355 u64 num, den, res;10356 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;10357 10358 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;10359 10360 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;10361 den = (unsigned long long)new_crtc_state->mode.htotal *10362 (unsigned long long)new_crtc_state->mode.vtotal;10363 10364 res = div_u64(num, den);10365 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;10366}10367 10368static int dm_update_crtc_state(struct amdgpu_display_manager *dm,10369 struct drm_atomic_state *state,10370 struct drm_crtc *crtc,10371 struct drm_crtc_state *old_crtc_state,10372 struct drm_crtc_state *new_crtc_state,10373 bool enable,10374 bool *lock_and_validation_needed)10375{10376 struct dm_atomic_state *dm_state = NULL;10377 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;10378 struct dc_stream_state *new_stream;10379 int ret = 0;10380 10381 /*10382 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set10383 * update changed items10384 */10385 struct amdgpu_crtc *acrtc = NULL;10386 struct drm_connector *connector = NULL;10387 struct amdgpu_dm_connector *aconnector = NULL;10388 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;10389 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;10390 10391 new_stream = NULL;10392 10393 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);10394 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);10395 acrtc = to_amdgpu_crtc(crtc);10396 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);10397 if (connector)10398 aconnector = to_amdgpu_dm_connector(connector);10399 10400 /* TODO This hack should go away */10401 if (connector && enable) {10402 /* Make sure fake sink is created in plug-in scenario */10403 drm_new_conn_state = drm_atomic_get_new_connector_state(state,10404 connector);10405 drm_old_conn_state = drm_atomic_get_old_connector_state(state,10406 connector);10407 10408 if (IS_ERR(drm_new_conn_state)) {10409 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);10410 goto fail;10411 }10412 10413 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);10414 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);10415 10416 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))10417 goto skip_modeset;10418 10419 new_stream = create_validate_stream_for_sink(aconnector,10420 &new_crtc_state->mode,10421 dm_new_conn_state,10422 dm_old_crtc_state->stream);10423 10424 /*10425 * we can have no stream on ACTION_SET if a display10426 * was disconnected during S3, in this case it is not an10427 * error, the OS will be updated after detection, and10428 * will do the right thing on next atomic commit10429 */10430 10431 if (!new_stream) {10432 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",10433 __func__, acrtc->base.base.id);10434 ret = -ENOMEM;10435 goto fail;10436 }10437 10438 /*10439 * TODO: Check VSDB bits to decide whether this should10440 * be enabled or not.10441 */10442 new_stream->triggered_crtc_reset.enabled =10443 dm->force_timing_sync;10444 10445 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;10446 10447 ret = fill_hdr_info_packet(drm_new_conn_state,10448 &new_stream->hdr_static_metadata);10449 if (ret)10450 goto fail;10451 10452 /*10453 * If we already removed the old stream from the context10454 * (and set the new stream to NULL) then we can't reuse10455 * the old stream even if the stream and scaling are unchanged.10456 * We'll hit the BUG_ON and black screen.10457 *10458 * TODO: Refactor this function to allow this check to work10459 * in all conditions.10460 */10461 if (amdgpu_freesync_vid_mode &&10462 dm_new_crtc_state->stream &&10463 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))10464 goto skip_modeset;10465 10466 if (dm_new_crtc_state->stream &&10467 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&10468 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {10469 new_crtc_state->mode_changed = false;10470 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",10471 new_crtc_state->mode_changed);10472 }10473 }10474 10475 /* mode_changed flag may get updated above, need to check again */10476 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))10477 goto skip_modeset;10478 10479 drm_dbg_state(state->dev,10480 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",10481 acrtc->crtc_id,10482 new_crtc_state->enable,10483 new_crtc_state->active,10484 new_crtc_state->planes_changed,10485 new_crtc_state->mode_changed,10486 new_crtc_state->active_changed,10487 new_crtc_state->connectors_changed);10488 10489 /* Remove stream for any changed/disabled CRTC */10490 if (!enable) {10491 10492 if (!dm_old_crtc_state->stream)10493 goto skip_modeset;10494 10495 /* Unset freesync video if it was active before */10496 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {10497 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;10498 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;10499 }10500 10501 /* Now check if we should set freesync video mode */10502 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&10503 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&10504 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&10505 is_timing_unchanged_for_freesync(new_crtc_state,10506 old_crtc_state)) {10507 new_crtc_state->mode_changed = false;10508 DRM_DEBUG_DRIVER(10509 "Mode change not required for front porch change, setting mode_changed to %d",10510 new_crtc_state->mode_changed);10511 10512 set_freesync_fixed_config(dm_new_crtc_state);10513 10514 goto skip_modeset;10515 } else if (amdgpu_freesync_vid_mode && aconnector &&10516 is_freesync_video_mode(&new_crtc_state->mode,10517 aconnector)) {10518 struct drm_display_mode *high_mode;10519 10520 high_mode = get_highest_refresh_rate_mode(aconnector, false);10521 if (!drm_mode_equal(&new_crtc_state->mode, high_mode))10522 set_freesync_fixed_config(dm_new_crtc_state);10523 }10524 10525 ret = dm_atomic_get_state(state, &dm_state);10526 if (ret)10527 goto fail;10528 10529 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",10530 crtc->base.id);10531 10532 /* i.e. reset mode */10533 if (dc_state_remove_stream(10534 dm->dc,10535 dm_state->context,10536 dm_old_crtc_state->stream) != DC_OK) {10537 ret = -EINVAL;10538 goto fail;10539 }10540 10541 dc_stream_release(dm_old_crtc_state->stream);10542 dm_new_crtc_state->stream = NULL;10543 10544 reset_freesync_config_for_crtc(dm_new_crtc_state);10545 10546 *lock_and_validation_needed = true;10547 10548 } else {/* Add stream for any updated/enabled CRTC */10549 /*10550 * Quick fix to prevent NULL pointer on new_stream when10551 * added MST connectors not found in existing crtc_state in the chained mode10552 * TODO: need to dig out the root cause of that10553 */10554 if (!connector)10555 goto skip_modeset;10556 10557 if (modereset_required(new_crtc_state))10558 goto skip_modeset;10559 10560 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,10561 dm_old_crtc_state->stream)) {10562 10563 WARN_ON(dm_new_crtc_state->stream);10564 10565 ret = dm_atomic_get_state(state, &dm_state);10566 if (ret)10567 goto fail;10568 10569 dm_new_crtc_state->stream = new_stream;10570 10571 dc_stream_retain(new_stream);10572 10573 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",10574 crtc->base.id);10575 10576 if (dc_state_add_stream(10577 dm->dc,10578 dm_state->context,10579 dm_new_crtc_state->stream) != DC_OK) {10580 ret = -EINVAL;10581 goto fail;10582 }10583 10584 *lock_and_validation_needed = true;10585 }10586 }10587 10588skip_modeset:10589 /* Release extra reference */10590 if (new_stream)10591 dc_stream_release(new_stream);10592 10593 /*10594 * We want to do dc stream updates that do not require a10595 * full modeset below.10596 */10597 if (!(enable && connector && new_crtc_state->active))10598 return 0;10599 /*10600 * Given above conditions, the dc state cannot be NULL because:10601 * 1. We're in the process of enabling CRTCs (just been added10602 * to the dc context, or already is on the context)10603 * 2. Has a valid connector attached, and10604 * 3. Is currently active and enabled.10605 * => The dc stream state currently exists.10606 */10607 BUG_ON(dm_new_crtc_state->stream == NULL);10608 10609 /* Scaling or underscan settings */10610 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||10611 drm_atomic_crtc_needs_modeset(new_crtc_state))10612 update_stream_scaling_settings(10613 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);10614 10615 /* ABM settings */10616 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;10617 10618 /*10619 * Color management settings. We also update color properties10620 * when a modeset is needed, to ensure it gets reprogrammed.10621 */10622 if (dm_new_crtc_state->base.color_mgmt_changed ||10623 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf ||10624 drm_atomic_crtc_needs_modeset(new_crtc_state)) {10625 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);10626 if (ret)10627 goto fail;10628 }10629 10630 /* Update Freesync settings. */10631 get_freesync_config_for_crtc(dm_new_crtc_state,10632 dm_new_conn_state);10633 10634 return ret;10635 10636fail:10637 if (new_stream)10638 dc_stream_release(new_stream);10639 return ret;10640}10641 10642static bool should_reset_plane(struct drm_atomic_state *state,10643 struct drm_plane *plane,10644 struct drm_plane_state *old_plane_state,10645 struct drm_plane_state *new_plane_state)10646{10647 struct drm_plane *other;10648 struct drm_plane_state *old_other_state, *new_other_state;10649 struct drm_crtc_state *old_crtc_state, *new_crtc_state;10650 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state;10651 struct amdgpu_device *adev = drm_to_adev(plane->dev);10652 int i;10653 10654 /*10655 * TODO: Remove this hack for all asics once it proves that the10656 * fast updates works fine on DCN3.2+.10657 */10658 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) &&10659 state->allow_modeset)10660 return true;10661 10662 /* Exit early if we know that we're adding or removing the plane. */10663 if (old_plane_state->crtc != new_plane_state->crtc)10664 return true;10665 10666 /* old crtc == new_crtc == NULL, plane not in context. */10667 if (!new_plane_state->crtc)10668 return false;10669 10670 new_crtc_state =10671 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);10672 old_crtc_state =10673 drm_atomic_get_old_crtc_state(state, old_plane_state->crtc);10674 10675 if (!new_crtc_state)10676 return true;10677 10678 /*10679 * A change in cursor mode means a new dc pipe needs to be acquired or10680 * released from the state10681 */10682 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);10683 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);10684 if (plane->type == DRM_PLANE_TYPE_CURSOR &&10685 old_dm_crtc_state != NULL &&10686 old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) {10687 return true;10688 }10689 10690 /* CRTC Degamma changes currently require us to recreate planes. */10691 if (new_crtc_state->color_mgmt_changed)10692 return true;10693 10694 /*10695 * On zpos change, planes need to be reordered by removing and re-adding10696 * them one by one to the dc state, in order of descending zpos.10697 *10698 * TODO: We can likely skip bandwidth validation if the only thing that10699 * changed about the plane was it'z z-ordering.10700 */10701 if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos)10702 return true;10703 10704 if (drm_atomic_crtc_needs_modeset(new_crtc_state))10705 return true;10706 10707 /*10708 * If there are any new primary or overlay planes being added or10709 * removed then the z-order can potentially change. To ensure10710 * correct z-order and pipe acquisition the current DC architecture10711 * requires us to remove and recreate all existing planes.10712 *10713 * TODO: Come up with a more elegant solution for this.10714 */10715 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {10716 struct amdgpu_framebuffer *old_afb, *new_afb;10717 struct dm_plane_state *dm_new_other_state, *dm_old_other_state;10718 10719 dm_new_other_state = to_dm_plane_state(new_other_state);10720 dm_old_other_state = to_dm_plane_state(old_other_state);10721 10722 if (other->type == DRM_PLANE_TYPE_CURSOR)10723 continue;10724 10725 if (old_other_state->crtc != new_plane_state->crtc &&10726 new_other_state->crtc != new_plane_state->crtc)10727 continue;10728 10729 if (old_other_state->crtc != new_other_state->crtc)10730 return true;10731 10732 /* Src/dst size and scaling updates. */10733 if (old_other_state->src_w != new_other_state->src_w ||10734 old_other_state->src_h != new_other_state->src_h ||10735 old_other_state->crtc_w != new_other_state->crtc_w ||10736 old_other_state->crtc_h != new_other_state->crtc_h)10737 return true;10738 10739 /* Rotation / mirroring updates. */10740 if (old_other_state->rotation != new_other_state->rotation)10741 return true;10742 10743 /* Blending updates. */10744 if (old_other_state->pixel_blend_mode !=10745 new_other_state->pixel_blend_mode)10746 return true;10747 10748 /* Alpha updates. */10749 if (old_other_state->alpha != new_other_state->alpha)10750 return true;10751 10752 /* Colorspace changes. */10753 if (old_other_state->color_range != new_other_state->color_range ||10754 old_other_state->color_encoding != new_other_state->color_encoding)10755 return true;10756 10757 /* HDR/Transfer Function changes. */10758 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf ||10759 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut ||10760 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult ||10761 dm_old_other_state->ctm != dm_new_other_state->ctm ||10762 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut ||10763 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf ||10764 dm_old_other_state->lut3d != dm_new_other_state->lut3d ||10765 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut ||10766 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf)10767 return true;10768 10769 /* Framebuffer checks fall at the end. */10770 if (!old_other_state->fb || !new_other_state->fb)10771 continue;10772 10773 /* Pixel format changes can require bandwidth updates. */10774 if (old_other_state->fb->format != new_other_state->fb->format)10775 return true;10776 10777 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;10778 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;10779 10780 /* Tiling and DCC changes also require bandwidth updates. */10781 if (old_afb->tiling_flags != new_afb->tiling_flags ||10782 old_afb->base.modifier != new_afb->base.modifier)10783 return true;10784 }10785 10786 return false;10787}10788 10789static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,10790 struct drm_plane_state *new_plane_state,10791 struct drm_framebuffer *fb)10792{10793 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);10794 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);10795 unsigned int pitch;10796 bool linear;10797 10798 if (fb->width > new_acrtc->max_cursor_width ||10799 fb->height > new_acrtc->max_cursor_height) {10800 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",10801 new_plane_state->fb->width,10802 new_plane_state->fb->height);10803 return -EINVAL;10804 }10805 if (new_plane_state->src_w != fb->width << 16 ||10806 new_plane_state->src_h != fb->height << 16) {10807 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");10808 return -EINVAL;10809 }10810 10811 /* Pitch in pixels */10812 pitch = fb->pitches[0] / fb->format->cpp[0];10813 10814 if (fb->width != pitch) {10815 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",10816 fb->width, pitch);10817 return -EINVAL;10818 }10819 10820 switch (pitch) {10821 case 64:10822 case 128:10823 case 256:10824 /* FB pitch is supported by cursor plane */10825 break;10826 default:10827 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);10828 return -EINVAL;10829 }10830 10831 /* Core DRM takes care of checking FB modifiers, so we only need to10832 * check tiling flags when the FB doesn't have a modifier.10833 */10834 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {10835 if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) {10836 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0;10837 } else if (adev->family >= AMDGPU_FAMILY_AI) {10838 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;10839 } else {10840 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&10841 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&10842 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;10843 }10844 if (!linear) {10845 DRM_DEBUG_ATOMIC("Cursor FB not linear");10846 return -EINVAL;10847 }10848 }10849 10850 return 0;10851}10852 10853/*10854 * Helper function for checking the cursor in native mode10855 */10856static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc,10857 struct drm_plane *plane,10858 struct drm_plane_state *new_plane_state,10859 bool enable)10860{10861 10862 struct amdgpu_crtc *new_acrtc;10863 int ret;10864 10865 if (!enable || !new_plane_crtc ||10866 drm_atomic_plane_disabling(plane->state, new_plane_state))10867 return 0;10868 10869 new_acrtc = to_amdgpu_crtc(new_plane_crtc);10870 10871 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {10872 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");10873 return -EINVAL;10874 }10875 10876 if (new_plane_state->fb) {10877 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,10878 new_plane_state->fb);10879 if (ret)10880 return ret;10881 }10882 10883 return 0;10884}10885 10886static bool dm_should_update_native_cursor(struct drm_atomic_state *state,10887 struct drm_crtc *old_plane_crtc,10888 struct drm_crtc *new_plane_crtc,10889 bool enable)10890{10891 struct drm_crtc_state *old_crtc_state, *new_crtc_state;10892 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;10893 10894 if (!enable) {10895 if (old_plane_crtc == NULL)10896 return true;10897 10898 old_crtc_state = drm_atomic_get_old_crtc_state(10899 state, old_plane_crtc);10900 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);10901 10902 return dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE;10903 } else {10904 if (new_plane_crtc == NULL)10905 return true;10906 10907 new_crtc_state = drm_atomic_get_new_crtc_state(10908 state, new_plane_crtc);10909 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);10910 10911 return dm_new_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE;10912 }10913}10914 10915static int dm_update_plane_state(struct dc *dc,10916 struct drm_atomic_state *state,10917 struct drm_plane *plane,10918 struct drm_plane_state *old_plane_state,10919 struct drm_plane_state *new_plane_state,10920 bool enable,10921 bool *lock_and_validation_needed,10922 bool *is_top_most_overlay)10923{10924 10925 struct dm_atomic_state *dm_state = NULL;10926 struct drm_crtc *new_plane_crtc, *old_plane_crtc;10927 struct drm_crtc_state *old_crtc_state, *new_crtc_state;10928 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;10929 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;10930 bool needs_reset, update_native_cursor;10931 int ret = 0;10932 10933 10934 new_plane_crtc = new_plane_state->crtc;10935 old_plane_crtc = old_plane_state->crtc;10936 dm_new_plane_state = to_dm_plane_state(new_plane_state);10937 dm_old_plane_state = to_dm_plane_state(old_plane_state);10938 10939 update_native_cursor = dm_should_update_native_cursor(state,10940 old_plane_crtc,10941 new_plane_crtc,10942 enable);10943 10944 if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) {10945 ret = dm_check_native_cursor_state(new_plane_crtc, plane,10946 new_plane_state, enable);10947 if (ret)10948 return ret;10949 10950 return 0;10951 }10952 10953 needs_reset = should_reset_plane(state, plane, old_plane_state,10954 new_plane_state);10955 10956 /* Remove any changed/removed planes */10957 if (!enable) {10958 if (!needs_reset)10959 return 0;10960 10961 if (!old_plane_crtc)10962 return 0;10963 10964 old_crtc_state = drm_atomic_get_old_crtc_state(10965 state, old_plane_crtc);10966 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);10967 10968 if (!dm_old_crtc_state->stream)10969 return 0;10970 10971 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",10972 plane->base.id, old_plane_crtc->base.id);10973 10974 ret = dm_atomic_get_state(state, &dm_state);10975 if (ret)10976 return ret;10977 10978 if (!dc_state_remove_plane(10979 dc,10980 dm_old_crtc_state->stream,10981 dm_old_plane_state->dc_state,10982 dm_state->context)) {10983 10984 return -EINVAL;10985 }10986 10987 if (dm_old_plane_state->dc_state)10988 dc_plane_state_release(dm_old_plane_state->dc_state);10989 10990 dm_new_plane_state->dc_state = NULL;10991 10992 *lock_and_validation_needed = true;10993 10994 } else { /* Add new planes */10995 struct dc_plane_state *dc_new_plane_state;10996 10997 if (drm_atomic_plane_disabling(plane->state, new_plane_state))10998 return 0;10999 11000 if (!new_plane_crtc)11001 return 0;11002 11003 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);11004 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);11005 11006 if (!dm_new_crtc_state->stream)11007 return 0;11008 11009 if (!needs_reset)11010 return 0;11011 11012 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);11013 if (ret)11014 goto out;11015 11016 WARN_ON(dm_new_plane_state->dc_state);11017 11018 dc_new_plane_state = dc_create_plane_state(dc);11019 if (!dc_new_plane_state) {11020 ret = -ENOMEM;11021 goto out;11022 }11023 11024 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",11025 plane->base.id, new_plane_crtc->base.id);11026 11027 ret = fill_dc_plane_attributes(11028 drm_to_adev(new_plane_crtc->dev),11029 dc_new_plane_state,11030 new_plane_state,11031 new_crtc_state);11032 if (ret) {11033 dc_plane_state_release(dc_new_plane_state);11034 goto out;11035 }11036 11037 ret = dm_atomic_get_state(state, &dm_state);11038 if (ret) {11039 dc_plane_state_release(dc_new_plane_state);11040 goto out;11041 }11042 11043 /*11044 * Any atomic check errors that occur after this will11045 * not need a release. The plane state will be attached11046 * to the stream, and therefore part of the atomic11047 * state. It'll be released when the atomic state is11048 * cleaned.11049 */11050 if (!dc_state_add_plane(11051 dc,11052 dm_new_crtc_state->stream,11053 dc_new_plane_state,11054 dm_state->context)) {11055 11056 dc_plane_state_release(dc_new_plane_state);11057 ret = -EINVAL;11058 goto out;11059 }11060 11061 dm_new_plane_state->dc_state = dc_new_plane_state;11062 11063 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);11064 11065 /* Tell DC to do a full surface update every time there11066 * is a plane change. Inefficient, but works for now.11067 */11068 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;11069 11070 *lock_and_validation_needed = true;11071 }11072 11073out:11074 /* If enabling cursor overlay failed, attempt fallback to native mode */11075 if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) {11076 ret = dm_check_native_cursor_state(new_plane_crtc, plane,11077 new_plane_state, enable);11078 if (ret)11079 return ret;11080 11081 dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE;11082 }11083 11084 return ret;11085}11086 11087static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,11088 int *src_w, int *src_h)11089{11090 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {11091 case DRM_MODE_ROTATE_90:11092 case DRM_MODE_ROTATE_270:11093 *src_w = plane_state->src_h >> 16;11094 *src_h = plane_state->src_w >> 16;11095 break;11096 case DRM_MODE_ROTATE_0:11097 case DRM_MODE_ROTATE_180:11098 default:11099 *src_w = plane_state->src_w >> 16;11100 *src_h = plane_state->src_h >> 16;11101 break;11102 }11103}11104 11105static void11106dm_get_plane_scale(struct drm_plane_state *plane_state,11107 int *out_plane_scale_w, int *out_plane_scale_h)11108{11109 int plane_src_w, plane_src_h;11110 11111 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);11112 *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;11113 *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;11114}11115 11116/*11117 * The normalized_zpos value cannot be used by this iterator directly. It's only11118 * calculated for enabled planes, potentially causing normalized_zpos collisions11119 * between enabled/disabled planes in the atomic state. We need a unique value11120 * so that the iterator will not generate the same object twice, or loop11121 * indefinitely.11122 */11123static inline struct __drm_planes_state *__get_next_zpos(11124 struct drm_atomic_state *state,11125 struct __drm_planes_state *prev)11126{11127 unsigned int highest_zpos = 0, prev_zpos = 256;11128 uint32_t highest_id = 0, prev_id = UINT_MAX;11129 struct drm_plane_state *new_plane_state;11130 struct drm_plane *plane;11131 int i, highest_i = -1;11132 11133 if (prev != NULL) {11134 prev_zpos = prev->new_state->zpos;11135 prev_id = prev->ptr->base.id;11136 }11137 11138 for_each_new_plane_in_state(state, plane, new_plane_state, i) {11139 /* Skip planes with higher zpos than the previously returned */11140 if (new_plane_state->zpos > prev_zpos ||11141 (new_plane_state->zpos == prev_zpos &&11142 plane->base.id >= prev_id))11143 continue;11144 11145 /* Save the index of the plane with highest zpos */11146 if (new_plane_state->zpos > highest_zpos ||11147 (new_plane_state->zpos == highest_zpos &&11148 plane->base.id > highest_id)) {11149 highest_zpos = new_plane_state->zpos;11150 highest_id = plane->base.id;11151 highest_i = i;11152 }11153 }11154 11155 if (highest_i < 0)11156 return NULL;11157 11158 return &state->planes[highest_i];11159}11160 11161/*11162 * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate11163 * by descending zpos, as read from the new plane state. This is the same11164 * ordering as defined by drm_atomic_normalize_zpos().11165 */11166#define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \11167 for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \11168 __i != NULL; __i = __get_next_zpos((__state), __i)) \11169 for_each_if(((plane) = __i->ptr, \11170 (void)(plane) /* Only to avoid unused-but-set-variable warning */, \11171 (old_plane_state) = __i->old_state, \11172 (new_plane_state) = __i->new_state, 1))11173 11174static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)11175{11176 struct drm_connector *connector;11177 struct drm_connector_state *conn_state, *old_conn_state;11178 struct amdgpu_dm_connector *aconnector = NULL;11179 int i;11180 11181 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {11182 if (!conn_state->crtc)11183 conn_state = old_conn_state;11184 11185 if (conn_state->crtc != crtc)11186 continue;11187 11188 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)11189 continue;11190 11191 aconnector = to_amdgpu_dm_connector(connector);11192 if (!aconnector->mst_output_port || !aconnector->mst_root)11193 aconnector = NULL;11194 else11195 break;11196 }11197 11198 if (!aconnector)11199 return 0;11200 11201 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);11202}11203 11204/**11205 * DOC: Cursor Modes - Native vs Overlay11206 *11207 * In native mode, the cursor uses a integrated cursor pipe within each DCN hw11208 * plane. It does not require a dedicated hw plane to enable, but it is11209 * subjected to the same z-order and scaling as the hw plane. It also has format11210 * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB11211 * hw plane.11212 *11213 * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its11214 * own scaling and z-pos. It also has no blending restrictions. It lends to a11215 * cursor behavior more akin to a DRM client's expectations. However, it does11216 * occupy an extra DCN plane, and therefore will only be used if a DCN plane is11217 * available.11218 */11219 11220/**11221 * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc11222 * @adev: amdgpu device11223 * @state: DRM atomic state11224 * @dm_crtc_state: amdgpu state for the CRTC containing the cursor11225 * @cursor_mode: Returns the required cursor mode on dm_crtc_state11226 *11227 * Get whether the cursor should be enabled in native mode, or overlay mode, on11228 * the dm_crtc_state.11229 *11230 * The cursor should be enabled in overlay mode if there exists an underlying11231 * plane - on which the cursor may be blended - that is either YUV formatted, or11232 * scaled differently from the cursor.11233 *11234 * Since zpos info is required, drm_atomic_normalize_zpos must be called before11235 * calling this function.11236 *11237 * Return: 0 on success, or an error code if getting the cursor plane state11238 * failed.11239 */11240static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev,11241 struct drm_atomic_state *state,11242 struct dm_crtc_state *dm_crtc_state,11243 enum amdgpu_dm_cursor_mode *cursor_mode)11244{11245 struct drm_plane_state *old_plane_state, *plane_state, *cursor_state;11246 struct drm_crtc_state *crtc_state = &dm_crtc_state->base;11247 struct drm_plane *plane;11248 bool consider_mode_change = false;11249 bool entire_crtc_covered = false;11250 bool cursor_changed = false;11251 int underlying_scale_w, underlying_scale_h;11252 int cursor_scale_w, cursor_scale_h;11253 int i;11254 11255 /* Overlay cursor not supported on HW before DCN11256 * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions11257 * as previous DCN generations, so enable native mode on DCN401 in addition to DCE11258 */11259 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0 ||11260 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {11261 *cursor_mode = DM_CURSOR_NATIVE_MODE;11262 return 0;11263 }11264 11265 /* Init cursor_mode to be the same as current */11266 *cursor_mode = dm_crtc_state->cursor_mode;11267 11268 /*11269 * Cursor mode can change if a plane's format changes, scale changes, is11270 * enabled/disabled, or z-order changes.11271 */11272 for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) {11273 int new_scale_w, new_scale_h, old_scale_w, old_scale_h;11274 11275 /* Only care about planes on this CRTC */11276 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0)11277 continue;11278 11279 if (plane->type == DRM_PLANE_TYPE_CURSOR)11280 cursor_changed = true;11281 11282 if (drm_atomic_plane_enabling(old_plane_state, plane_state) ||11283 drm_atomic_plane_disabling(old_plane_state, plane_state) ||11284 old_plane_state->fb->format != plane_state->fb->format) {11285 consider_mode_change = true;11286 break;11287 }11288 11289 dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h);11290 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);11291 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {11292 consider_mode_change = true;11293 break;11294 }11295 }11296 11297 if (!consider_mode_change && !crtc_state->zpos_changed)11298 return 0;11299 11300 /*11301 * If no cursor change on this CRTC, and not enabled on this CRTC, then11302 * no need to set cursor mode. This avoids needlessly locking the cursor11303 * state.11304 */11305 if (!cursor_changed &&11306 !(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) {11307 return 0;11308 }11309 11310 cursor_state = drm_atomic_get_plane_state(state,11311 crtc_state->crtc->cursor);11312 if (IS_ERR(cursor_state))11313 return PTR_ERR(cursor_state);11314 11315 /* Cursor is disabled */11316 if (!cursor_state->fb)11317 return 0;11318 11319 /* For all planes in descending z-order (all of which are below cursor11320 * as per zpos definitions), check their scaling and format11321 */11322 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) {11323 11324 /* Only care about non-cursor planes on this CRTC */11325 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 ||11326 plane->type == DRM_PLANE_TYPE_CURSOR)11327 continue;11328 11329 /* Underlying plane is YUV format - use overlay cursor */11330 if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) {11331 *cursor_mode = DM_CURSOR_OVERLAY_MODE;11332 return 0;11333 }11334 11335 dm_get_plane_scale(plane_state,11336 &underlying_scale_w, &underlying_scale_h);11337 dm_get_plane_scale(cursor_state,11338 &cursor_scale_w, &cursor_scale_h);11339 11340 /* Underlying plane has different scale - use overlay cursor */11341 if (cursor_scale_w != underlying_scale_w &&11342 cursor_scale_h != underlying_scale_h) {11343 *cursor_mode = DM_CURSOR_OVERLAY_MODE;11344 return 0;11345 }11346 11347 /* If this plane covers the whole CRTC, no need to check planes underneath */11348 if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 &&11349 plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay &&11350 plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) {11351 entire_crtc_covered = true;11352 break;11353 }11354 }11355 11356 /* If planes do not cover the entire CRTC, use overlay mode to enable11357 * cursor over holes11358 */11359 if (entire_crtc_covered)11360 *cursor_mode = DM_CURSOR_NATIVE_MODE;11361 else11362 *cursor_mode = DM_CURSOR_OVERLAY_MODE;11363 11364 return 0;11365}11366 11367/**11368 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.11369 *11370 * @dev: The DRM device11371 * @state: The atomic state to commit11372 *11373 * Validate that the given atomic state is programmable by DC into hardware.11374 * This involves constructing a &struct dc_state reflecting the new hardware11375 * state we wish to commit, then querying DC to see if it is programmable. It's11376 * important not to modify the existing DC state. Otherwise, atomic_check11377 * may unexpectedly commit hardware changes.11378 *11379 * When validating the DC state, it's important that the right locks are11380 * acquired. For full updates case which removes/adds/updates streams on one11381 * CRTC while flipping on another CRTC, acquiring global lock will guarantee11382 * that any such full update commit will wait for completion of any outstanding11383 * flip using DRMs synchronization events.11384 *11385 * Note that DM adds the affected connectors for all CRTCs in state, when that11386 * might not seem necessary. This is because DC stream creation requires the11387 * DC sink, which is tied to the DRM connector state. Cleaning this up should11388 * be possible but non-trivial - a possible TODO item.11389 *11390 * Return: -Error code if validation failed.11391 */11392static int amdgpu_dm_atomic_check(struct drm_device *dev,11393 struct drm_atomic_state *state)11394{11395 struct amdgpu_device *adev = drm_to_adev(dev);11396 struct dm_atomic_state *dm_state = NULL;11397 struct dc *dc = adev->dm.dc;11398 struct drm_connector *connector;11399 struct drm_connector_state *old_con_state, *new_con_state;11400 struct drm_crtc *crtc;11401 struct drm_crtc_state *old_crtc_state, *new_crtc_state;11402 struct drm_plane *plane;11403 struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state;11404 enum dc_status status;11405 int ret, i;11406 bool lock_and_validation_needed = false;11407 bool is_top_most_overlay = true;11408 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;11409 struct drm_dp_mst_topology_mgr *mgr;11410 struct drm_dp_mst_topology_state *mst_state;11411 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0};11412 11413 trace_amdgpu_dm_atomic_check_begin(state);11414 11415 ret = drm_atomic_helper_check_modeset(dev, state);11416 if (ret) {11417 drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed\n");11418 goto fail;11419 }11420 11421 /* Check connector changes */11422 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {11423 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);11424 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);11425 11426 /* Skip connectors that are disabled or part of modeset already. */11427 if (!new_con_state->crtc)11428 continue;11429 11430 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);11431 if (IS_ERR(new_crtc_state)) {11432 drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed\n");11433 ret = PTR_ERR(new_crtc_state);11434 goto fail;11435 }11436 11437 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||11438 dm_old_con_state->scaling != dm_new_con_state->scaling)11439 new_crtc_state->connectors_changed = true;11440 }11441 11442 if (dc_resource_is_dsc_encoding_supported(dc)) {11443 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {11444 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {11445 ret = add_affected_mst_dsc_crtcs(state, crtc);11446 if (ret) {11447 drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed\n");11448 goto fail;11449 }11450 }11451 }11452 }11453 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {11454 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);11455 11456 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&11457 !new_crtc_state->color_mgmt_changed &&11458 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&11459 dm_old_crtc_state->dsc_force_changed == false)11460 continue;11461 11462 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);11463 if (ret) {11464 drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed\n");11465 goto fail;11466 }11467 11468 if (!new_crtc_state->enable)11469 continue;11470 11471 ret = drm_atomic_add_affected_connectors(state, crtc);11472 if (ret) {11473 drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed\n");11474 goto fail;11475 }11476 11477 ret = drm_atomic_add_affected_planes(state, crtc);11478 if (ret) {11479 drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed\n");11480 goto fail;11481 }11482 11483 if (dm_old_crtc_state->dsc_force_changed)11484 new_crtc_state->mode_changed = true;11485 }11486 11487 /*11488 * Add all primary and overlay planes on the CRTC to the state11489 * whenever a plane is enabled to maintain correct z-ordering11490 * and to enable fast surface updates.11491 */11492 drm_for_each_crtc(crtc, dev) {11493 bool modified = false;11494 11495 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {11496 if (plane->type == DRM_PLANE_TYPE_CURSOR)11497 continue;11498 11499 if (new_plane_state->crtc == crtc ||11500 old_plane_state->crtc == crtc) {11501 modified = true;11502 break;11503 }11504 }11505 11506 if (!modified)11507 continue;11508 11509 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {11510 if (plane->type == DRM_PLANE_TYPE_CURSOR)11511 continue;11512 11513 new_plane_state =11514 drm_atomic_get_plane_state(state, plane);11515 11516 if (IS_ERR(new_plane_state)) {11517 ret = PTR_ERR(new_plane_state);11518 drm_dbg_atomic(dev, "new_plane_state is BAD\n");11519 goto fail;11520 }11521 }11522 }11523 11524 /*11525 * DC consults the zpos (layer_index in DC terminology) to determine the11526 * hw plane on which to enable the hw cursor (see11527 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in11528 * atomic state, so call drm helper to normalize zpos.11529 */11530 ret = drm_atomic_normalize_zpos(dev, state);11531 if (ret) {11532 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");11533 goto fail;11534 }11535 11536 /*11537 * Determine whether cursors on each CRTC should be enabled in native or11538 * overlay mode.11539 */11540 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {11541 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);11542 11543 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state,11544 &dm_new_crtc_state->cursor_mode);11545 if (ret) {11546 drm_dbg(dev, "Failed to determine cursor mode\n");11547 goto fail;11548 }11549 11550 /*11551 * If overlay cursor is needed, DC cannot go through the11552 * native cursor update path. All enabled planes on the CRTC11553 * need to be added for DC to not disable a plane by mistake11554 */11555 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) {11556 ret = drm_atomic_add_affected_planes(state, crtc);11557 if (ret)11558 goto fail;11559 }11560 }11561 11562 /* Remove exiting planes if they are modified */11563 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {11564 if (old_plane_state->fb && new_plane_state->fb &&11565 get_mem_type(old_plane_state->fb) !=11566 get_mem_type(new_plane_state->fb))11567 lock_and_validation_needed = true;11568 11569 ret = dm_update_plane_state(dc, state, plane,11570 old_plane_state,11571 new_plane_state,11572 false,11573 &lock_and_validation_needed,11574 &is_top_most_overlay);11575 if (ret) {11576 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n");11577 goto fail;11578 }11579 }11580 11581 /* Disable all crtcs which require disable */11582 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {11583 ret = dm_update_crtc_state(&adev->dm, state, crtc,11584 old_crtc_state,11585 new_crtc_state,11586 false,11587 &lock_and_validation_needed);11588 if (ret) {11589 drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed\n");11590 goto fail;11591 }11592 }11593 11594 /* Enable all crtcs which require enable */11595 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {11596 ret = dm_update_crtc_state(&adev->dm, state, crtc,11597 old_crtc_state,11598 new_crtc_state,11599 true,11600 &lock_and_validation_needed);11601 if (ret) {11602 drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed\n");11603 goto fail;11604 }11605 }11606 11607 /* Add new/modified planes */11608 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {11609 ret = dm_update_plane_state(dc, state, plane,11610 old_plane_state,11611 new_plane_state,11612 true,11613 &lock_and_validation_needed,11614 &is_top_most_overlay);11615 if (ret) {11616 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n");11617 goto fail;11618 }11619 }11620 11621#if defined(CONFIG_DRM_AMD_DC_FP)11622 if (dc_resource_is_dsc_encoding_supported(dc)) {11623 ret = pre_validate_dsc(state, &dm_state, vars);11624 if (ret != 0)11625 goto fail;11626 }11627#endif11628 11629 /* Run this here since we want to validate the streams we created */11630 ret = drm_atomic_helper_check_planes(dev, state);11631 if (ret) {11632 drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed\n");11633 goto fail;11634 }11635 11636 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {11637 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);11638 if (dm_new_crtc_state->mpo_requested)11639 drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc);11640 }11641 11642 /* Check cursor restrictions */11643 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {11644 enum amdgpu_dm_cursor_mode required_cursor_mode;11645 int is_rotated, is_scaled;11646 11647 /* Overlay cusor not subject to native cursor restrictions */11648 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);11649 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE)11650 continue;11651 11652 /* Check if rotation or scaling is enabled on DCN401 */11653 if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) &&11654 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {11655 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor);11656 11657 is_rotated = new_cursor_state &&11658 ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0);11659 is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) ||11660 (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h));11661 11662 if (is_rotated || is_scaled) {11663 drm_dbg_driver(11664 crtc->dev,11665 "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n",11666 crtc->base.id, crtc->name);11667 ret = -EINVAL;11668 goto fail;11669 }11670 }11671 11672 /* If HW can only do native cursor, check restrictions again */11673 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state,11674 &required_cursor_mode);11675 if (ret) {11676 drm_dbg_driver(crtc->dev,11677 "[CRTC:%d:%s] Checking cursor mode failed\n",11678 crtc->base.id, crtc->name);11679 goto fail;11680 } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) {11681 drm_dbg_driver(crtc->dev,11682 "[CRTC:%d:%s] Cannot enable native cursor due to scaling or YUV restrictions\n",11683 crtc->base.id, crtc->name);11684 ret = -EINVAL;11685 goto fail;11686 }11687 }11688 11689 if (state->legacy_cursor_update) {11690 /*11691 * This is a fast cursor update coming from the plane update11692 * helper, check if it can be done asynchronously for better11693 * performance.11694 */11695 state->async_update =11696 !drm_atomic_helper_async_check(dev, state);11697 11698 /*11699 * Skip the remaining global validation if this is an async11700 * update. Cursor updates can be done without affecting11701 * state or bandwidth calcs and this avoids the performance11702 * penalty of locking the private state object and11703 * allocating a new dc_state.11704 */11705 if (state->async_update)11706 return 0;11707 }11708 11709 /* Check scaling and underscan changes*/11710 /* TODO Removed scaling changes validation due to inability to commit11711 * new stream into context w\o causing full reset. Need to11712 * decide how to handle.11713 */11714 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {11715 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);11716 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);11717 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);11718 11719 /* Skip any modesets/resets */11720 if (!acrtc || drm_atomic_crtc_needs_modeset(11721 drm_atomic_get_new_crtc_state(state, &acrtc->base)))11722 continue;11723 11724 /* Skip any thing not scale or underscan changes */11725 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))11726 continue;11727 11728 lock_and_validation_needed = true;11729 }11730 11731 /* set the slot info for each mst_state based on the link encoding format */11732 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {11733 struct amdgpu_dm_connector *aconnector;11734 struct drm_connector *connector;11735 struct drm_connector_list_iter iter;11736 u8 link_coding_cap;11737 11738 drm_connector_list_iter_begin(dev, &iter);11739 drm_for_each_connector_iter(connector, &iter) {11740 if (connector->index == mst_state->mgr->conn_base_id) {11741 aconnector = to_amdgpu_dm_connector(connector);11742 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);11743 drm_dp_mst_update_slots(mst_state, link_coding_cap);11744 11745 break;11746 }11747 }11748 drm_connector_list_iter_end(&iter);11749 }11750 11751 /**11752 * Streams and planes are reset when there are changes that affect11753 * bandwidth. Anything that affects bandwidth needs to go through11754 * DC global validation to ensure that the configuration can be applied11755 * to hardware.11756 *11757 * We have to currently stall out here in atomic_check for outstanding11758 * commits to finish in this case because our IRQ handlers reference11759 * DRM state directly - we can end up disabling interrupts too early11760 * if we don't.11761 *11762 * TODO: Remove this stall and drop DM state private objects.11763 */11764 if (lock_and_validation_needed) {11765 ret = dm_atomic_get_state(state, &dm_state);11766 if (ret) {11767 drm_dbg_atomic(dev, "dm_atomic_get_state() failed\n");11768 goto fail;11769 }11770 11771 ret = do_aquire_global_lock(dev, state);11772 if (ret) {11773 drm_dbg_atomic(dev, "do_aquire_global_lock() failed\n");11774 goto fail;11775 }11776 11777#if defined(CONFIG_DRM_AMD_DC_FP)11778 if (dc_resource_is_dsc_encoding_supported(dc)) {11779 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);11780 if (ret) {11781 drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed\n");11782 ret = -EINVAL;11783 goto fail;11784 }11785 }11786#endif11787 11788 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);11789 if (ret) {11790 drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n");11791 goto fail;11792 }11793 11794 /*11795 * Perform validation of MST topology in the state:11796 * We need to perform MST atomic check before calling11797 * dc_validate_global_state(), or there is a chance11798 * to get stuck in an infinite loop and hang eventually.11799 */11800 ret = drm_dp_mst_atomic_check(state);11801 if (ret) {11802 drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n");11803 goto fail;11804 }11805 status = dc_validate_global_state(dc, dm_state->context, true);11806 if (status != DC_OK) {11807 drm_dbg_atomic(dev, "DC global validation failure: %s (%d)",11808 dc_status_to_str(status), status);11809 ret = -EINVAL;11810 goto fail;11811 }11812 } else {11813 /*11814 * The commit is a fast update. Fast updates shouldn't change11815 * the DC context, affect global validation, and can have their11816 * commit work done in parallel with other commits not touching11817 * the same resource. If we have a new DC context as part of11818 * the DM atomic state from validation we need to free it and11819 * retain the existing one instead.11820 *11821 * Furthermore, since the DM atomic state only contains the DC11822 * context and can safely be annulled, we can free the state11823 * and clear the associated private object now to free11824 * some memory and avoid a possible use-after-free later.11825 */11826 11827 for (i = 0; i < state->num_private_objs; i++) {11828 struct drm_private_obj *obj = state->private_objs[i].ptr;11829 11830 if (obj->funcs == adev->dm.atomic_obj.funcs) {11831 int j = state->num_private_objs-1;11832 11833 dm_atomic_destroy_state(obj,11834 state->private_objs[i].state);11835 11836 /* If i is not at the end of the array then the11837 * last element needs to be moved to where i was11838 * before the array can safely be truncated.11839 */11840 if (i != j)11841 state->private_objs[i] =11842 state->private_objs[j];11843 11844 state->private_objs[j].ptr = NULL;11845 state->private_objs[j].state = NULL;11846 state->private_objs[j].old_state = NULL;11847 state->private_objs[j].new_state = NULL;11848 11849 state->num_private_objs = j;11850 break;11851 }11852 }11853 }11854 11855 /* Store the overall update type for use later in atomic check. */11856 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {11857 struct dm_crtc_state *dm_new_crtc_state =11858 to_dm_crtc_state(new_crtc_state);11859 11860 /*11861 * Only allow async flips for fast updates that don't change11862 * the FB pitch, the DCC state, rotation, etc.11863 */11864 if (new_crtc_state->async_flip && lock_and_validation_needed) {11865 drm_dbg_atomic(crtc->dev,11866 "[CRTC:%d:%s] async flips are only supported for fast updates\n",11867 crtc->base.id, crtc->name);11868 ret = -EINVAL;11869 goto fail;11870 }11871 11872 dm_new_crtc_state->update_type = lock_and_validation_needed ?11873 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;11874 }11875 11876 /* Must be success */11877 WARN_ON(ret);11878 11879 trace_amdgpu_dm_atomic_check_finish(state, ret);11880 11881 return ret;11882 11883fail:11884 if (ret == -EDEADLK)11885 drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n");11886 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)11887 drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n");11888 else11889 drm_dbg_atomic(dev, "Atomic check failed with err: %d\n", ret);11890 11891 trace_amdgpu_dm_atomic_check_finish(state, ret);11892 11893 return ret;11894}11895 11896static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,11897 unsigned int offset,11898 unsigned int total_length,11899 u8 *data,11900 unsigned int length,11901 struct amdgpu_hdmi_vsdb_info *vsdb)11902{11903 bool res;11904 union dmub_rb_cmd cmd;11905 struct dmub_cmd_send_edid_cea *input;11906 struct dmub_cmd_edid_cea_output *output;11907 11908 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)11909 return false;11910 11911 memset(&cmd, 0, sizeof(cmd));11912 11913 input = &cmd.edid_cea.data.input;11914 11915 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;11916 cmd.edid_cea.header.sub_type = 0;11917 cmd.edid_cea.header.payload_bytes =11918 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);11919 input->offset = offset;11920 input->length = length;11921 input->cea_total_length = total_length;11922 memcpy(input->payload, data, length);11923 11924 res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);11925 if (!res) {11926 DRM_ERROR("EDID CEA parser failed\n");11927 return false;11928 }11929 11930 output = &cmd.edid_cea.data.output;11931 11932 if (output->type == DMUB_CMD__EDID_CEA_ACK) {11933 if (!output->ack.success) {11934 DRM_ERROR("EDID CEA ack failed at offset %d\n",11935 output->ack.offset);11936 }11937 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {11938 if (!output->amd_vsdb.vsdb_found)11939 return false;11940 11941 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;11942 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;11943 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;11944 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;11945 } else {11946 DRM_WARN("Unknown EDID CEA parser results\n");11947 return false;11948 }11949 11950 return true;11951}11952 11953static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,11954 u8 *edid_ext, int len,11955 struct amdgpu_hdmi_vsdb_info *vsdb_info)11956{11957 int i;11958 11959 /* send extension block to DMCU for parsing */11960 for (i = 0; i < len; i += 8) {11961 bool res;11962 int offset;11963 11964 /* send 8 bytes a time */11965 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))11966 return false;11967 11968 if (i+8 == len) {11969 /* EDID block sent completed, expect result */11970 int version, min_rate, max_rate;11971 11972 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);11973 if (res) {11974 /* amd vsdb found */11975 vsdb_info->freesync_supported = 1;11976 vsdb_info->amd_vsdb_version = version;11977 vsdb_info->min_refresh_rate_hz = min_rate;11978 vsdb_info->max_refresh_rate_hz = max_rate;11979 return true;11980 }11981 /* not amd vsdb */11982 return false;11983 }11984 11985 /* check for ack*/11986 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);11987 if (!res)11988 return false;11989 }11990 11991 return false;11992}11993 11994static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,11995 u8 *edid_ext, int len,11996 struct amdgpu_hdmi_vsdb_info *vsdb_info)11997{11998 int i;11999 12000 /* send extension block to DMCU for parsing */12001 for (i = 0; i < len; i += 8) {12002 /* send 8 bytes a time */12003 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))12004 return false;12005 }12006 12007 return vsdb_info->freesync_supported;12008}12009 12010static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,12011 u8 *edid_ext, int len,12012 struct amdgpu_hdmi_vsdb_info *vsdb_info)12013{12014 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);12015 bool ret;12016 12017 mutex_lock(&adev->dm.dc_lock);12018 if (adev->dm.dmub_srv)12019 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);12020 else12021 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);12022 mutex_unlock(&adev->dm.dc_lock);12023 return ret;12024}12025 12026static void parse_edid_displayid_vrr(struct drm_connector *connector,12027 struct edid *edid)12028{12029 u8 *edid_ext = NULL;12030 int i;12031 int j = 0;12032 u16 min_vfreq;12033 u16 max_vfreq;12034 12035 if (edid == NULL || edid->extensions == 0)12036 return;12037 12038 /* Find DisplayID extension */12039 for (i = 0; i < edid->extensions; i++) {12040 edid_ext = (void *)(edid + (i + 1));12041 if (edid_ext[0] == DISPLAYID_EXT)12042 break;12043 }12044 12045 if (edid_ext == NULL)12046 return;12047 12048 while (j < EDID_LENGTH) {12049 /* Get dynamic video timing range from DisplayID if available */12050 if (EDID_LENGTH - j > 13 && edid_ext[j] == 0x25 &&12051 (edid_ext[j+1] & 0xFE) == 0 && (edid_ext[j+2] == 9)) {12052 min_vfreq = edid_ext[j+9];12053 if (edid_ext[j+1] & 7)12054 max_vfreq = edid_ext[j+10] + ((edid_ext[j+11] & 3) << 8);12055 else12056 max_vfreq = edid_ext[j+10];12057 12058 if (max_vfreq && min_vfreq) {12059 connector->display_info.monitor_range.max_vfreq = max_vfreq;12060 connector->display_info.monitor_range.min_vfreq = min_vfreq;12061 12062 return;12063 }12064 }12065 j++;12066 }12067}12068 12069static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,12070 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)12071{12072 u8 *edid_ext = NULL;12073 int i;12074 int j = 0;12075 12076 if (edid == NULL || edid->extensions == 0)12077 return -ENODEV;12078 12079 /* Find DisplayID extension */12080 for (i = 0; i < edid->extensions; i++) {12081 edid_ext = (void *)(edid + (i + 1));12082 if (edid_ext[0] == DISPLAYID_EXT)12083 break;12084 }12085 12086 while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) {12087 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];12088 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);12089 12090 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&12091 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {12092 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;12093 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;12094 DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);12095 12096 return true;12097 }12098 j++;12099 }12100 12101 return false;12102}12103 12104static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,12105 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)12106{12107 u8 *edid_ext = NULL;12108 int i;12109 bool valid_vsdb_found = false;12110 12111 /*----- drm_find_cea_extension() -----*/12112 /* No EDID or EDID extensions */12113 if (edid == NULL || edid->extensions == 0)12114 return -ENODEV;12115 12116 /* Find CEA extension */12117 for (i = 0; i < edid->extensions; i++) {12118 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);12119 if (edid_ext[0] == CEA_EXT)12120 break;12121 }12122 12123 if (i == edid->extensions)12124 return -ENODEV;12125 12126 /*----- cea_db_offsets() -----*/12127 if (edid_ext[0] != CEA_EXT)12128 return -ENODEV;12129 12130 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);12131 12132 return valid_vsdb_found ? i : -ENODEV;12133}12134 12135/**12136 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities12137 *12138 * @connector: Connector to query.12139 * @edid: EDID from monitor12140 *12141 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep12142 * track of some of the display information in the internal data struct used by12143 * amdgpu_dm. This function checks which type of connector we need to set the12144 * FreeSync parameters.12145 */12146void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,12147 struct edid *edid)12148{12149 int i = 0;12150 struct detailed_timing *timing;12151 struct detailed_non_pixel *data;12152 struct detailed_data_monitor_range *range;12153 struct amdgpu_dm_connector *amdgpu_dm_connector =12154 to_amdgpu_dm_connector(connector);12155 struct dm_connector_state *dm_con_state = NULL;12156 struct dc_sink *sink;12157 12158 struct amdgpu_device *adev = drm_to_adev(connector->dev);12159 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};12160 bool freesync_capable = false;12161 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;12162 12163 if (!connector->state) {12164 DRM_ERROR("%s - Connector has no state", __func__);12165 goto update;12166 }12167 12168 sink = amdgpu_dm_connector->dc_sink ?12169 amdgpu_dm_connector->dc_sink :12170 amdgpu_dm_connector->dc_em_sink;12171 12172 if (!edid || !sink) {12173 dm_con_state = to_dm_connector_state(connector->state);12174 12175 amdgpu_dm_connector->min_vfreq = 0;12176 amdgpu_dm_connector->max_vfreq = 0;12177 connector->display_info.monitor_range.min_vfreq = 0;12178 connector->display_info.monitor_range.max_vfreq = 0;12179 freesync_capable = false;12180 12181 goto update;12182 }12183 12184 dm_con_state = to_dm_connector_state(connector->state);12185 12186 if (!adev->dm.freesync_module)12187 goto update;12188 12189 /* Some eDP panels only have the refresh rate range info in DisplayID */12190 if ((connector->display_info.monitor_range.min_vfreq == 0 ||12191 connector->display_info.monitor_range.max_vfreq == 0))12192 parse_edid_displayid_vrr(connector, edid);12193 12194 if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||12195 sink->sink_signal == SIGNAL_TYPE_EDP)) {12196 bool edid_check_required = false;12197 12198 if (amdgpu_dm_connector->dc_link &&12199 amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) {12200 if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) {12201 amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;12202 amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;12203 if (amdgpu_dm_connector->max_vfreq -12204 amdgpu_dm_connector->min_vfreq > 10)12205 freesync_capable = true;12206 } else {12207 edid_check_required = edid->version > 1 ||12208 (edid->version == 1 &&12209 edid->revision > 1);12210 }12211 }12212 12213 if (edid_check_required) {12214 for (i = 0; i < 4; i++) {12215 12216 timing = &edid->detailed_timings[i];12217 data = &timing->data.other_data;12218 range = &data->data.range;12219 /*12220 * Check if monitor has continuous frequency mode12221 */12222 if (data->type != EDID_DETAIL_MONITOR_RANGE)12223 continue;12224 /*12225 * Check for flag range limits only. If flag == 1 then12226 * no additional timing information provided.12227 * Default GTF, GTF Secondary curve and CVT are not12228 * supported12229 */12230 if (range->flags != 1)12231 continue;12232 12233 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;12234 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;12235 12236 if (edid->revision >= 4) {12237 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)12238 connector->display_info.monitor_range.min_vfreq += 255;12239 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)12240 connector->display_info.monitor_range.max_vfreq += 255;12241 }12242 12243 amdgpu_dm_connector->min_vfreq =12244 connector->display_info.monitor_range.min_vfreq;12245 amdgpu_dm_connector->max_vfreq =12246 connector->display_info.monitor_range.max_vfreq;12247 12248 break;12249 }12250 12251 if (amdgpu_dm_connector->max_vfreq -12252 amdgpu_dm_connector->min_vfreq > 10) {12253 12254 freesync_capable = true;12255 }12256 }12257 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);12258 12259 if (vsdb_info.replay_mode) {12260 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;12261 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;12262 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;12263 }12264 12265 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {12266 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);12267 if (i >= 0 && vsdb_info.freesync_supported) {12268 timing = &edid->detailed_timings[i];12269 data = &timing->data.other_data;12270 12271 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;12272 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;12273 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)12274 freesync_capable = true;12275 12276 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;12277 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;12278 }12279 }12280 12281 if (amdgpu_dm_connector->dc_link)12282 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);12283 12284 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {12285 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);12286 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {12287 12288 amdgpu_dm_connector->pack_sdp_v1_3 = true;12289 amdgpu_dm_connector->as_type = as_type;12290 amdgpu_dm_connector->vsdb_info = vsdb_info;12291 12292 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;12293 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;12294 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)12295 freesync_capable = true;12296 12297 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;12298 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;12299 }12300 }12301 12302update:12303 if (dm_con_state)12304 dm_con_state->freesync_capable = freesync_capable;12305 12306 if (connector->state && amdgpu_dm_connector->dc_link && !freesync_capable &&12307 amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported) {12308 amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported = false;12309 amdgpu_dm_connector->dc_link->replay_settings.replay_feature_enabled = false;12310 }12311 12312 if (connector->vrr_capable_property)12313 drm_connector_set_vrr_capable_property(connector,12314 freesync_capable);12315}12316 12317void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)12318{12319 struct amdgpu_device *adev = drm_to_adev(dev);12320 struct dc *dc = adev->dm.dc;12321 int i;12322 12323 mutex_lock(&adev->dm.dc_lock);12324 if (dc->current_state) {12325 for (i = 0; i < dc->current_state->stream_count; ++i)12326 dc->current_state->streams[i]12327 ->triggered_crtc_reset.enabled =12328 adev->dm.force_timing_sync;12329 12330 dm_enable_per_frame_crtc_master_sync(dc->current_state);12331 dc_trigger_sync(dc, dc->current_state);12332 }12333 mutex_unlock(&adev->dm.dc_lock);12334}12335 12336static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc)12337{12338 if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)12339 dc_exit_ips_for_hw_access(dc);12340}12341 12342void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,12343 u32 value, const char *func_name)12344{12345#ifdef DM_CHECK_ADDR_012346 if (address == 0) {12347 drm_err(adev_to_drm(ctx->driver_context),12348 "invalid register write. address = 0");12349 return;12350 }12351#endif12352 12353 amdgpu_dm_exit_ips_for_hw_access(ctx->dc);12354 cgs_write_register(ctx->cgs_device, address, value);12355 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);12356}12357 12358uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,12359 const char *func_name)12360{12361 u32 value;12362#ifdef DM_CHECK_ADDR_012363 if (address == 0) {12364 drm_err(adev_to_drm(ctx->driver_context),12365 "invalid register read; address = 0\n");12366 return 0;12367 }12368#endif12369 12370 if (ctx->dmub_srv &&12371 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&12372 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {12373 ASSERT(false);12374 return 0;12375 }12376 12377 amdgpu_dm_exit_ips_for_hw_access(ctx->dc);12378 12379 value = cgs_read_register(ctx->cgs_device, address);12380 12381 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);12382 12383 return value;12384}12385 12386int amdgpu_dm_process_dmub_aux_transfer_sync(12387 struct dc_context *ctx,12388 unsigned int link_index,12389 struct aux_payload *payload,12390 enum aux_return_code_type *operation_result)12391{12392 struct amdgpu_device *adev = ctx->driver_context;12393 struct dmub_notification *p_notify = adev->dm.dmub_notify;12394 int ret = -1;12395 12396 mutex_lock(&adev->dm.dpia_aux_lock);12397 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {12398 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;12399 goto out;12400 }12401 12402 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {12403 DRM_ERROR("wait_for_completion_timeout timeout!");12404 *operation_result = AUX_RET_ERROR_TIMEOUT;12405 goto out;12406 }12407 12408 if (p_notify->result != AUX_RET_SUCCESS) {12409 /*12410 * Transient states before tunneling is enabled could12411 * lead to this error. We can ignore this for now.12412 */12413 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {12414 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",12415 payload->address, payload->length,12416 p_notify->result);12417 }12418 *operation_result = AUX_RET_ERROR_INVALID_REPLY;12419 goto out;12420 }12421 12422 12423 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;12424 if (!payload->write && p_notify->aux_reply.length &&12425 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {12426 12427 if (payload->length != p_notify->aux_reply.length) {12428 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",12429 p_notify->aux_reply.length,12430 payload->address, payload->length);12431 *operation_result = AUX_RET_ERROR_INVALID_REPLY;12432 goto out;12433 }12434 12435 memcpy(payload->data, p_notify->aux_reply.data,12436 p_notify->aux_reply.length);12437 }12438 12439 /* success */12440 ret = p_notify->aux_reply.length;12441 *operation_result = p_notify->result;12442out:12443 reinit_completion(&adev->dm.dmub_aux_transfer_done);12444 mutex_unlock(&adev->dm.dpia_aux_lock);12445 return ret;12446}12447 12448int amdgpu_dm_process_dmub_set_config_sync(12449 struct dc_context *ctx,12450 unsigned int link_index,12451 struct set_config_cmd_payload *payload,12452 enum set_config_status *operation_result)12453{12454 struct amdgpu_device *adev = ctx->driver_context;12455 bool is_cmd_complete;12456 int ret;12457 12458 mutex_lock(&adev->dm.dpia_aux_lock);12459 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,12460 link_index, payload, adev->dm.dmub_notify);12461 12462 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {12463 ret = 0;12464 *operation_result = adev->dm.dmub_notify->sc_status;12465 } else {12466 DRM_ERROR("wait_for_completion_timeout timeout!");12467 ret = -1;12468 *operation_result = SET_CONFIG_UNKNOWN_ERROR;12469 }12470 12471 if (!is_cmd_complete)12472 reinit_completion(&adev->dm.dmub_aux_transfer_done);12473 mutex_unlock(&adev->dm.dpia_aux_lock);12474 return ret;12475}12476 12477bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)12478{12479 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);12480}12481 12482bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)12483{12484 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);12485}12486