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1/*2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef __AMDGPU_DM_H__27#define __AMDGPU_DM_H__28 29#include <drm/display/drm_dp_mst_helper.h>30#include <drm/drm_atomic.h>31#include <drm/drm_connector.h>32#include <drm/drm_crtc.h>33#include <drm/drm_plane.h>34#include "link_service_types.h"35#include <drm/drm_writeback.h>36 37/*38 * This file contains the definition for amdgpu_display_manager39 * and its API for amdgpu driver's use.40 * This component provides all the display related functionality41 * and this is the only component that calls DAL API.42 * The API contained here intended for amdgpu driver use.43 * The API that is called directly from KMS framework is located44 * in amdgpu_dm_kms.h file45 */46 47#define AMDGPU_DM_MAX_DISPLAY_INDEX 3148 49#define AMDGPU_DM_MAX_CRTC 650 51#define AMDGPU_DM_MAX_NUM_EDP 252 53#define AMDGPU_DMUB_NOTIFICATION_MAX 754 55#define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A56#define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x4057#define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x358 59#define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL)60 61/*62#include "include/amdgpu_dal_power_if.h"63#include "amdgpu_dm_irq.h"64*/65 66#include "irq_types.h"67#include "signal_types.h"68#include "amdgpu_dm_crc.h"69#include "mod_info_packet.h"70struct aux_payload;71struct set_config_cmd_payload;72enum aux_return_code_type;73enum set_config_status;74 75/* Forward declarations */76struct amdgpu_device;77struct amdgpu_crtc;78struct drm_device;79struct dc;80struct amdgpu_bo;81struct dmub_srv;82struct dc_plane_state;83struct dmub_notification;84 85struct amd_vsdb_block {86 unsigned char ieee_id[3];87 unsigned char version;88 unsigned char feature_caps;89};90 91struct common_irq_params {92 struct amdgpu_device *adev;93 enum dc_irq_source irq_src;94 atomic64_t previous_timestamp;95};96 97/**98 * struct dm_compressor_info - Buffer info used by frame buffer compression99 * @cpu_addr: MMIO cpu addr100 * @bo_ptr: Pointer to the buffer object101 * @gpu_addr: MMIO gpu addr102 */103struct dm_compressor_info {104 void *cpu_addr;105 struct amdgpu_bo *bo_ptr;106 uint64_t gpu_addr;107};108 109typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify);110 111/**112 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ113 *114 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq115 * @dmub_notify: notification for callback function116 * @adev: amdgpu_device pointer117 */118struct dmub_hpd_work {119 struct work_struct handle_hpd_work;120 struct dmub_notification *dmub_notify;121 struct amdgpu_device *adev;122};123 124/**125 * struct vblank_control_work - Work data for vblank control126 * @work: Kernel work data for the work event127 * @dm: amdgpu display manager device128 * @acrtc: amdgpu CRTC instance for which the event has occurred129 * @stream: DC stream for which the event has occurred130 * @enable: true if enabling vblank131 */132struct vblank_control_work {133 struct work_struct work;134 struct amdgpu_display_manager *dm;135 struct amdgpu_crtc *acrtc;136 struct dc_stream_state *stream;137 bool enable;138};139 140/**141 * struct idle_workqueue - Work data for periodic action in idle142 * @work: Kernel work data for the work event143 * @dm: amdgpu display manager device144 * @enable: true if idle worker is enabled145 * @running: true if idle worker is running146 */147struct idle_workqueue {148 struct work_struct work;149 struct amdgpu_display_manager *dm;150 bool enable;151 bool running;152};153 154/**155 * struct amdgpu_dm_backlight_caps - Information about backlight156 *157 * Describe the backlight support for ACPI or eDP AUX.158 */159struct amdgpu_dm_backlight_caps {160 /**161 * @ext_caps: Keep the data struct with all the information about the162 * display support for HDR.163 */164 union dpcd_sink_ext_caps *ext_caps;165 /**166 * @aux_min_input_signal: Min brightness value supported by the display167 */168 u32 aux_min_input_signal;169 /**170 * @aux_max_input_signal: Max brightness value supported by the display171 * in nits.172 */173 u32 aux_max_input_signal;174 /**175 * @min_input_signal: minimum possible input in range 0-255.176 */177 int min_input_signal;178 /**179 * @max_input_signal: maximum possible input in range 0-255.180 */181 int max_input_signal;182 /**183 * @caps_valid: true if these values are from the ACPI interface.184 */185 bool caps_valid;186 /**187 * @aux_support: Describes if the display supports AUX backlight.188 */189 bool aux_support;190 /**191 * @ac_level: the default brightness if booted on AC192 */193 u8 ac_level;194 /**195 * @dc_level: the default brightness if booted on DC196 */197 u8 dc_level;198};199 200/**201 * struct dal_allocation - Tracks mapped FB memory for SMU communication202 * @list: list of dal allocations203 * @bo: GPU buffer object204 * @cpu_ptr: CPU virtual address of the GPU buffer object205 * @gpu_addr: GPU virtual address of the GPU buffer object206 */207struct dal_allocation {208 struct list_head list;209 struct amdgpu_bo *bo;210 void *cpu_ptr;211 u64 gpu_addr;212};213 214/**215 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq216 * offload work217 */218struct hpd_rx_irq_offload_work_queue {219 /**220 * @wq: workqueue structure to queue offload work.221 */222 struct workqueue_struct *wq;223 /**224 * @offload_lock: To protect fields of offload work queue.225 */226 spinlock_t offload_lock;227 /**228 * @is_handling_link_loss: Used to prevent inserting link loss event when229 * we're handling link loss230 */231 bool is_handling_link_loss;232 /**233 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message234 * ready event when we're already handling mst message ready event235 */236 bool is_handling_mst_msg_rdy_event;237 /**238 * @aconnector: The aconnector that this work queue is attached to239 */240 struct amdgpu_dm_connector *aconnector;241};242 243/**244 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure245 */246struct hpd_rx_irq_offload_work {247 /**248 * @work: offload work249 */250 struct work_struct work;251 /**252 * @data: reference irq data which is used while handling offload work253 */254 union hpd_irq_data data;255 /**256 * @offload_wq: offload work queue that this work is queued to257 */258 struct hpd_rx_irq_offload_work_queue *offload_wq;259};260 261/**262 * struct amdgpu_display_manager - Central amdgpu display manager device263 *264 * @dc: Display Core control structure265 * @adev: AMDGPU base driver structure266 * @ddev: DRM base driver structure267 * @display_indexes_num: Max number of display streams supported268 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables269 * @backlight_dev: Backlight control device270 * @backlight_link: Link on which to control backlight271 * @backlight_caps: Capabilities of the backlight device272 * @freesync_module: Module handling freesync calculations273 * @hdcp_workqueue: AMDGPU content protection queue274 * @fw_dmcu: Reference to DMCU firmware275 * @dmcu_fw_version: Version of the DMCU firmware276 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW277 * @cached_state: Caches device atomic state for suspend/resume278 * @cached_dc_state: Cached state of content streams279 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info280 * @force_timing_sync: set via debugfs. When set, indicates that all connected281 * displays will be forced to synchronize.282 * @dmcub_trace_event_en: enable dmcub trace events283 * @dmub_outbox_params: DMUB Outbox parameters284 * @num_of_edps: number of backlight eDPs285 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the286 * driver when true287 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB288 * transfers are done289 * @delayed_hpd_wq: work queue used to delay DMUB HPD work290 */291struct amdgpu_display_manager {292 293 struct dc *dc;294 295 /**296 * @dmub_srv:297 *298 * DMUB service, used for controlling the DMUB on hardware299 * that supports it. The pointer to the dmub_srv will be300 * NULL on hardware that does not support it.301 */302 struct dmub_srv *dmub_srv;303 304 /**305 * @dmub_notify:306 *307 * Notification from DMUB.308 */309 310 struct dmub_notification *dmub_notify;311 312 /**313 * @dmub_callback:314 *315 * Callback functions to handle notification from DMUB.316 */317 318 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX];319 320 /**321 * @dmub_thread_offload:322 *323 * Flag to indicate if callback is offload.324 */325 326 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX];327 328 /**329 * @dmub_fb_info:330 *331 * Framebuffer regions for the DMUB.332 */333 struct dmub_srv_fb_info *dmub_fb_info;334 335 /**336 * @dmub_fw:337 *338 * DMUB firmware, required on hardware that has DMUB support.339 */340 const struct firmware *dmub_fw;341 342 /**343 * @dmub_bo:344 *345 * Buffer object for the DMUB.346 */347 struct amdgpu_bo *dmub_bo;348 349 /**350 * @dmub_bo_gpu_addr:351 *352 * GPU virtual address for the DMUB buffer object.353 */354 u64 dmub_bo_gpu_addr;355 356 /**357 * @dmub_bo_cpu_addr:358 *359 * CPU address for the DMUB buffer object.360 */361 void *dmub_bo_cpu_addr;362 363 /**364 * @dmcub_fw_version:365 *366 * DMCUB firmware version.367 */368 uint32_t dmcub_fw_version;369 370 /**371 * @cgs_device:372 *373 * The Common Graphics Services device. It provides an interface for374 * accessing registers.375 */376 struct cgs_device *cgs_device;377 378 struct amdgpu_device *adev;379 struct drm_device *ddev;380 u16 display_indexes_num;381 382 /**383 * @atomic_obj:384 *385 * In combination with &dm_atomic_state it helps manage386 * global atomic state that doesn't map cleanly into existing387 * drm resources, like &dc_context.388 */389 struct drm_private_obj atomic_obj;390 391 /**392 * @dc_lock:393 *394 * Guards access to DC functions that can issue register write395 * sequences.396 */397 struct mutex dc_lock;398 399 /**400 * @audio_lock:401 *402 * Guards access to audio instance changes.403 */404 struct mutex audio_lock;405 406 /**407 * @audio_component:408 *409 * Used to notify ELD changes to sound driver.410 */411 struct drm_audio_component *audio_component;412 413 /**414 * @audio_registered:415 *416 * True if the audio component has been registered417 * successfully, false otherwise.418 */419 bool audio_registered;420 421 /**422 * @irq_handler_list_low_tab:423 *424 * Low priority IRQ handler table.425 *426 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ427 * source. Low priority IRQ handlers are deferred to a workqueue to be428 * processed. Hence, they can sleep.429 *430 * Note that handlers are called in the same order as they were431 * registered (FIFO).432 */433 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];434 435 /**436 * @irq_handler_list_high_tab:437 *438 * High priority IRQ handler table.439 *440 * It is a n*m table, same as &irq_handler_list_low_tab. However,441 * handlers in this table are not deferred and are called immediately.442 */443 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];444 445 /**446 * @pflip_params:447 *448 * Page flip IRQ parameters, passed to registered handlers when449 * triggered.450 */451 struct common_irq_params452 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];453 454 /**455 * @vblank_params:456 *457 * Vertical blanking IRQ parameters, passed to registered handlers when458 * triggered.459 */460 struct common_irq_params461 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];462 463 /**464 * @vline0_params:465 *466 * OTG vertical interrupt0 IRQ parameters, passed to registered467 * handlers when triggered.468 */469 struct common_irq_params470 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1];471 472 /**473 * @vupdate_params:474 *475 * Vertical update IRQ parameters, passed to registered handlers when476 * triggered.477 */478 struct common_irq_params479 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];480 481 /**482 * @dmub_trace_params:483 *484 * DMUB trace event IRQ parameters, passed to registered handlers when485 * triggered.486 */487 struct common_irq_params488 dmub_trace_params[1];489 490 struct common_irq_params491 dmub_outbox_params[1];492 493 spinlock_t irq_handler_list_table_lock;494 495 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP];496 497 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP];498 499 uint8_t num_of_edps;500 501 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP];502 503 struct mod_freesync *freesync_module;504 struct hdcp_workqueue *hdcp_workqueue;505 506 /**507 * @vblank_control_workqueue:508 *509 * Deferred work for vblank control events.510 */511 struct workqueue_struct *vblank_control_workqueue;512 513 /**514 * @idle_workqueue:515 *516 * Periodic work for idle events.517 */518 struct idle_workqueue *idle_workqueue;519 520 struct drm_atomic_state *cached_state;521 struct dc_state *cached_dc_state;522 523 struct dm_compressor_info compressor;524 525 const struct firmware *fw_dmcu;526 uint32_t dmcu_fw_version;527 /**528 * @soc_bounding_box:529 *530 * gpu_info FW provided soc bounding box struct or 0 if not531 * available in FW532 */533 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;534 535 /**536 * @active_vblank_irq_count:537 *538 * number of currently active vblank irqs539 */540 uint32_t active_vblank_irq_count;541 542#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)543 /**544 * @secure_display_ctxs:545 *546 * Store the ROI information and the work_struct to command dmub and psp for547 * all crtcs.548 */549 struct secure_display_context *secure_display_ctxs;550#endif551 /**552 * @hpd_rx_offload_wq:553 *554 * Work queue to offload works of hpd_rx_irq555 */556 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq;557 /**558 * @mst_encoders:559 *560 * fake encoders used for DP MST.561 */562 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];563 bool force_timing_sync;564 bool disable_hpd_irq;565 bool dmcub_trace_event_en;566 /**567 * @da_list:568 *569 * DAL fb memory allocation list, for communication with SMU.570 */571 struct list_head da_list;572 struct completion dmub_aux_transfer_done;573 struct workqueue_struct *delayed_hpd_wq;574 575 /**576 * @brightness:577 *578 * cached backlight values.579 */580 u32 brightness[AMDGPU_DM_MAX_NUM_EDP];581 /**582 * @actual_brightness:583 *584 * last successfully applied backlight values.585 */586 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];587 588 /**589 * @aux_hpd_discon_quirk:590 *591 * quirk for hpd discon while aux is on-going.592 * occurred on certain intel platform593 */594 bool aux_hpd_discon_quirk;595 596 /**597 * @dpia_aux_lock:598 *599 * Guards access to DPIA AUX600 */601 struct mutex dpia_aux_lock;602 603 /**604 * @bb_from_dmub:605 *606 * Bounding box data read from dmub during early initialization for DCN4+607 */608 struct dml2_soc_bb *bb_from_dmub;609};610 611enum dsc_clock_force_state {612 DSC_CLK_FORCE_DEFAULT = 0,613 DSC_CLK_FORCE_ENABLE,614 DSC_CLK_FORCE_DISABLE,615};616 617struct dsc_preferred_settings {618 enum dsc_clock_force_state dsc_force_enable;619 uint32_t dsc_num_slices_v;620 uint32_t dsc_num_slices_h;621 uint32_t dsc_bits_per_pixel;622 bool dsc_force_disable_passthrough;623};624 625enum mst_progress_status {626 MST_STATUS_DEFAULT = 0,627 MST_PROBE = BIT(0),628 MST_REMOTE_EDID = BIT(1),629 MST_ALLOCATE_NEW_PAYLOAD = BIT(2),630 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3),631};632 633/**634 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info635 *636 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this637 * struct is useful to keep track of the display-specific information about638 * FreeSync.639 */640struct amdgpu_hdmi_vsdb_info {641 /**642 * @amd_vsdb_version: Vendor Specific Data Block Version, should be643 * used to determine which Vendor Specific InfoFrame (VSIF) to send.644 */645 unsigned int amd_vsdb_version;646 647 /**648 * @freesync_supported: FreeSync Supported.649 */650 bool freesync_supported;651 652 /**653 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz.654 */655 unsigned int min_refresh_rate_hz;656 657 /**658 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz659 */660 unsigned int max_refresh_rate_hz;661 662 /**663 * @replay_mode: Replay supported664 */665 bool replay_mode;666};667 668struct amdgpu_dm_connector {669 670 struct drm_connector base;671 uint32_t connector_id;672 int bl_idx;673 674 /* we need to mind the EDID between detect675 and get modes due to analog/digital/tvencoder */676 struct edid *edid;677 678 /* shared with amdgpu */679 struct amdgpu_hpd hpd;680 681 /* number of modes generated from EDID at 'dc_sink' */682 int num_modes;683 684 /* The 'old' sink - before an HPD.685 * The 'current' sink is in dc_link->sink. */686 struct dc_sink *dc_sink;687 struct dc_link *dc_link;688 689 /**690 * @dc_em_sink: Reference to the emulated (virtual) sink.691 */692 struct dc_sink *dc_em_sink;693 694 /* DM only */695 struct drm_dp_mst_topology_mgr mst_mgr;696 struct amdgpu_dm_dp_aux dm_dp_aux;697 struct drm_dp_mst_port *mst_output_port;698 struct amdgpu_dm_connector *mst_root;699 struct drm_dp_aux *dsc_aux;700 struct mutex handle_mst_msg_ready;701 702 /* TODO see if we can merge with ddc_bus or make a dm_connector */703 struct amdgpu_i2c_adapter *i2c;704 705 /* Monitor range limits */706 /**707 * @min_vfreq: Minimal frequency supported by the display in Hz. This708 * value is set to zero when there is no FreeSync support.709 */710 int min_vfreq;711 712 /**713 * @max_vfreq: Maximum frequency supported by the display in Hz. This714 * value is set to zero when there is no FreeSync support.715 */716 int max_vfreq ;717 718 /* Audio instance - protected by audio_lock. */719 int audio_inst;720 721 struct mutex hpd_lock;722 723 bool fake_enable;724 bool force_yuv420_output;725 struct dsc_preferred_settings dsc_settings;726 union dp_downstream_port_present mst_downstream_port_present;727 /* Cached display modes */728 struct drm_display_mode freesync_vid_base;729 730 int sr_skip_count;731 bool disallow_edp_enter_psr;732 733 /* Record progress status of mst*/734 uint8_t mst_status;735 736 /* Automated testing */737 bool timing_changed;738 struct dc_crtc_timing *timing_requested;739 740 /* Adaptive Sync */741 bool pack_sdp_v1_3;742 enum adaptive_sync_type as_type;743 struct amdgpu_hdmi_vsdb_info vsdb_info;744};745 746static inline void amdgpu_dm_set_mst_status(uint8_t *status,747 uint8_t flags, bool set)748{749 if (set)750 *status |= flags;751 else752 *status &= ~flags;753}754 755#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)756 757struct amdgpu_dm_wb_connector {758 struct drm_writeback_connector base;759 struct dc_link *link;760};761 762#define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base)763 764extern const struct amdgpu_ip_block_version dm_ip_block;765 766/* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD.767 *768 * It includes standardized transfer functions and pure power functions. The769 * transfer function coefficients are available at modules/color/color_gamma.c770 */771enum amdgpu_transfer_function {772 AMDGPU_TRANSFER_FUNCTION_DEFAULT,773 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF,774 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF,775 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF,776 AMDGPU_TRANSFER_FUNCTION_IDENTITY,777 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF,778 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF,779 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF,780 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF,781 AMDGPU_TRANSFER_FUNCTION_BT709_OETF,782 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF,783 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF,784 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF,785 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF,786 AMDGPU_TRANSFER_FUNCTION_COUNT787};788 789struct dm_plane_state {790 struct drm_plane_state base;791 struct dc_plane_state *dc_state;792 793 /* Plane color mgmt */794 /**795 * @degamma_lut:796 *797 * 1D LUT for mapping framebuffer/plane pixel data before sampling or798 * blending operations. It's usually applied to linearize input space.799 * The blob (if not NULL) is an array of &struct drm_color_lut.800 */801 struct drm_property_blob *degamma_lut;802 /**803 * @degamma_tf:804 *805 * Predefined transfer function to tell DC driver the input space to806 * linearize.807 */808 enum amdgpu_transfer_function degamma_tf;809 /**810 * @hdr_mult:811 *812 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed813 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on814 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously.815 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you816 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is817 * S31.32 sign-magnitude.818 *819 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ820 * TF is needed for any subsequent linear-to-non-linear transforms.821 */822 __u64 hdr_mult;823 /**824 * @ctm:825 *826 * Color transformation matrix. The blob (if not NULL) is a &struct827 * drm_color_ctm_3x4.828 */829 struct drm_property_blob *ctm;830 /**831 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an832 * array of &struct drm_color_lut.833 */834 struct drm_property_blob *shaper_lut;835 /**836 * @shaper_tf:837 *838 * Predefined transfer function to delinearize color space.839 */840 enum amdgpu_transfer_function shaper_tf;841 /**842 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of843 * &struct drm_color_lut.844 */845 struct drm_property_blob *lut3d;846 /**847 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an848 * array of &struct drm_color_lut.849 */850 struct drm_property_blob *blend_lut;851 /**852 * @blend_tf:853 *854 * Pre-defined transfer function for converting plane pixel data before855 * applying blend LUT.856 */857 enum amdgpu_transfer_function blend_tf;858};859 860enum amdgpu_dm_cursor_mode {861 DM_CURSOR_NATIVE_MODE = 0,862 DM_CURSOR_OVERLAY_MODE,863};864 865struct dm_crtc_state {866 struct drm_crtc_state base;867 struct dc_stream_state *stream;868 869 bool cm_has_degamma;870 bool cm_is_degamma_srgb;871 872 bool mpo_requested;873 874 int update_type;875 int active_planes;876 877 int crc_skip_count;878 879 bool freesync_vrr_info_changed;880 881 bool dsc_force_changed;882 bool vrr_supported;883 struct mod_freesync_config freesync_config;884 struct dc_info_packet vrr_infopacket;885 886 int abm_level;887 888 /**889 * @regamma_tf:890 *891 * Pre-defined transfer function for converting internal FB -> wire892 * encoding.893 */894 enum amdgpu_transfer_function regamma_tf;895 896 enum amdgpu_dm_cursor_mode cursor_mode;897};898 899#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)900 901struct dm_atomic_state {902 struct drm_private_state base;903 904 struct dc_state *context;905};906 907#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)908 909struct dm_connector_state {910 struct drm_connector_state base;911 912 enum amdgpu_rmx_type scaling;913 uint8_t underscan_vborder;914 uint8_t underscan_hborder;915 bool underscan_enable;916 bool freesync_capable;917 bool update_hdcp;918 uint8_t abm_level;919 int vcpi_slots;920 uint64_t pbn;921};922 923#define to_dm_connector_state(x)\924 container_of((x), struct dm_connector_state, base)925 926void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);927struct drm_connector_state *928amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);929int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,930 struct drm_connector_state *state,931 struct drm_property *property,932 uint64_t val);933 934int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,935 const struct drm_connector_state *state,936 struct drm_property *property,937 uint64_t *val);938 939int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);940 941void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,942 struct amdgpu_dm_connector *aconnector,943 int connector_type,944 struct dc_link *link,945 int link_index);946 947enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,948 struct drm_display_mode *mode);949 950void dm_restore_drm_connector_state(struct drm_device *dev,951 struct drm_connector *connector);952 953void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,954 struct edid *edid);955 956void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);957 958/* 3D LUT max size is 17x17x17 (4913 entries) */959#define MAX_COLOR_3DLUT_SIZE 17960#define MAX_COLOR_3DLUT_BITDEPTH 12961int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,962 struct drm_plane_state *plane_state);963/* 1D LUT size */964#define MAX_COLOR_LUT_ENTRIES 4096965/* Legacy gamm LUT users such as X doesn't like large LUT sizes */966#define MAX_COLOR_LEGACY_LUT_ENTRIES 256967 968void amdgpu_dm_init_color_mod(void);969int amdgpu_dm_create_color_properties(struct amdgpu_device *adev);970int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);971int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);972int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,973 struct drm_plane_state *plane_state,974 struct dc_plane_state *dc_plane_state);975 976void amdgpu_dm_update_connector_after_detect(977 struct amdgpu_dm_connector *aconnector);978 979extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;980 981int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index,982 struct aux_payload *payload, enum aux_return_code_type *operation_result);983 984int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index,985 struct set_config_cmd_payload *payload, enum set_config_status *operation_result);986 987struct dc_stream_state *988 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,989 const struct drm_display_mode *drm_mode,990 const struct dm_connector_state *dm_state,991 const struct dc_stream_state *old_stream);992 993int dm_atomic_get_state(struct drm_atomic_state *state,994 struct dm_atomic_state **dm_state);995 996struct drm_connector *997amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,998 struct drm_crtc *crtc);999 1000int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth);1001struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev);1002 1003void *dm_allocate_gpu_mem(struct amdgpu_device *adev,1004 enum dc_gpu_mem_alloc_type type,1005 size_t size,1006 long long *addr);1007 1008bool amdgpu_dm_is_headless(struct amdgpu_device *adev);1009 1010#endif /* __AMDGPU_DM_H__ */1011