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1/*2 * Copyright 2019 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_27#define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_28 29struct drm_crtc;30struct dm_crtc_state;31 32enum amdgpu_dm_pipe_crc_source {33 AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,34 AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,35 AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER,36 AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,37 AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER,38 AMDGPU_DM_PIPE_CRC_SOURCE_MAX,39 AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,40};41 42#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY43struct crc_window_param {44 uint16_t x_start;45 uint16_t y_start;46 uint16_t x_end;47 uint16_t y_end;48 /* CRC window is activated or not*/49 bool activated;50 /* Update crc window during vertical blank or not */51 bool update_win;52 /* skip reading/writing for few frames */53 int skip_frame_cnt;54};55 56struct secure_display_context {57 /* work to notify PSP TA*/58 struct work_struct notify_ta_work;59 60 /* work to forward ROI to dmcu/dmub */61 struct work_struct forward_roi_work;62 63 struct drm_crtc *crtc;64 65 /* Region of Interest (ROI) */66 struct rect rect;67};68#endif69 70static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)71{72 return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&73 (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);74}75 76/* amdgpu_dm_crc.c */77#ifdef CONFIG_DEBUG_FS78int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,79 struct dm_crtc_state *dm_crtc_state,80 enum amdgpu_dm_pipe_crc_source source);81int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);82int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,83 const char *src_name,84 size_t *values_cnt);85const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,86 size_t *count);87void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);88#else89#define amdgpu_dm_crtc_set_crc_source NULL90#define amdgpu_dm_crtc_verify_crc_source NULL91#define amdgpu_dm_crtc_get_crc_sources NULL92#define amdgpu_dm_crtc_handle_crc_irq(x)93#endif94 95#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY96bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);97void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc);98struct secure_display_context *amdgpu_dm_crtc_secure_display_create_contexts(99 struct amdgpu_device *adev);100#else101#define amdgpu_dm_crc_window_is_activated(x)102#define amdgpu_dm_crtc_handle_crc_window_irq(x)103#define amdgpu_dm_crtc_secure_display_create_contexts(x)104#endif105 106#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */107