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1/*2 * Copyright 2015 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#include <linux/string.h>27#include <linux/acpi.h>28#include <linux/i2c.h>29 30#include <drm/drm_atomic.h>31#include <drm/drm_probe_helper.h>32#include <drm/amdgpu_drm.h>33#include <drm/drm_edid.h>34#include <drm/drm_fixed.h>35 36#include "dm_services.h"37#include "amdgpu.h"38#include "dc.h"39#include "amdgpu_dm.h"40#include "amdgpu_dm_irq.h"41#include "amdgpu_dm_mst_types.h"42#include "dpcd_defs.h"43#include "dc/inc/core_types.h"44 45#include "dm_helpers.h"46#include "ddc_service_types.h"47#include "clk_mgr.h"48 49static u32 edid_extract_panel_id(struct edid *edid)50{51 return (u32)edid->mfg_id[0] << 24 |52 (u32)edid->mfg_id[1] << 16 |53 (u32)EDID_PRODUCT_ID(edid);54}55 56static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)57{58 uint32_t panel_id = edid_extract_panel_id(edid);59 60 switch (panel_id) {61 /* Workaround for some monitors which does not work well with FAMS */62 case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):63 case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):64 case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):65 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);66 edid_caps->panel_patch.disable_fams = true;67 break;68 /* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */69 case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):70 case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):71 case drm_edid_encode_panel_id('B', 'O', 'E', 0x092A):72 case drm_edid_encode_panel_id('L', 'G', 'D', 0x06D1):73 case drm_edid_encode_panel_id('M', 'S', 'F', 0x1003):74 DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);75 edid_caps->panel_patch.remove_sink_ext_caps = true;76 break;77 case drm_edid_encode_panel_id('S', 'D', 'C', 0x4154):78 DRM_DEBUG_DRIVER("Disabling VSC on monitor with panel id %X\n", panel_id);79 edid_caps->panel_patch.disable_colorimetry = true;80 break;81 default:82 return;83 }84}85 86/**87 * dm_helpers_parse_edid_caps() - Parse edid caps88 *89 * @link: current detected link90 * @edid: [in] pointer to edid91 * @edid_caps: [in] pointer to edid caps92 *93 * Return: void94 */95enum dc_edid_status dm_helpers_parse_edid_caps(96 struct dc_link *link,97 const struct dc_edid *edid,98 struct dc_edid_caps *edid_caps)99{100 struct amdgpu_dm_connector *aconnector = link->priv;101 struct drm_connector *connector = &aconnector->base;102 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;103 struct cea_sad *sads;104 int sad_count = -1;105 int sadb_count = -1;106 int i = 0;107 uint8_t *sadb = NULL;108 109 enum dc_edid_status result = EDID_OK;110 111 if (!edid_caps || !edid)112 return EDID_BAD_INPUT;113 114 if (!drm_edid_is_valid(edid_buf))115 result = EDID_BAD_CHECKSUM;116 117 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |118 ((uint16_t) edid_buf->mfg_id[1])<<8;119 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |120 ((uint16_t) edid_buf->prod_code[1])<<8;121 edid_caps->serial_number = edid_buf->serial;122 edid_caps->manufacture_week = edid_buf->mfg_week;123 edid_caps->manufacture_year = edid_buf->mfg_year;124 125 drm_edid_get_monitor_name(edid_buf,126 edid_caps->display_name,127 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);128 129 edid_caps->edid_hdmi = connector->display_info.is_hdmi;130 131 apply_edid_quirks(edid_buf, edid_caps);132 133 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);134 if (sad_count <= 0)135 return result;136 137 edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT);138 for (i = 0; i < edid_caps->audio_mode_count; ++i) {139 struct cea_sad *sad = &sads[i];140 141 edid_caps->audio_modes[i].format_code = sad->format;142 edid_caps->audio_modes[i].channel_count = sad->channels + 1;143 edid_caps->audio_modes[i].sample_rate = sad->freq;144 edid_caps->audio_modes[i].sample_size = sad->byte2;145 }146 147 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);148 149 if (sadb_count < 0) {150 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);151 sadb_count = 0;152 }153 154 if (sadb_count)155 edid_caps->speaker_flags = sadb[0];156 else157 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;158 159 kfree(sads);160 kfree(sadb);161 162 return result;163}164 165static void166fill_dc_mst_payload_table_from_drm(struct dc_link *link,167 bool enable,168 struct drm_dp_mst_atomic_payload *target_payload,169 struct dc_dp_mst_stream_allocation_table *table)170{171 struct dc_dp_mst_stream_allocation_table new_table = { 0 };172 struct dc_dp_mst_stream_allocation *sa;173 struct link_mst_stream_allocation_table copy_of_link_table =174 link->mst_stream_alloc_table;175 176 int i;177 int current_hw_table_stream_cnt = copy_of_link_table.stream_count;178 struct link_mst_stream_allocation *dc_alloc;179 180 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/181 if (enable) {182 dc_alloc =183 ©_of_link_table.stream_allocations[current_hw_table_stream_cnt];184 dc_alloc->vcp_id = target_payload->vcpi;185 dc_alloc->slot_count = target_payload->time_slots;186 } else {187 for (i = 0; i < copy_of_link_table.stream_count; i++) {188 dc_alloc =189 ©_of_link_table.stream_allocations[i];190 191 if (dc_alloc->vcp_id == target_payload->vcpi) {192 dc_alloc->vcp_id = 0;193 dc_alloc->slot_count = 0;194 break;195 }196 }197 ASSERT(i != copy_of_link_table.stream_count);198 }199 200 /* Fill payload info*/201 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {202 dc_alloc =203 ©_of_link_table.stream_allocations[i];204 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {205 sa = &new_table.stream_allocations[new_table.stream_count];206 sa->slot_count = dc_alloc->slot_count;207 sa->vcp_id = dc_alloc->vcp_id;208 new_table.stream_count++;209 }210 }211 212 /* Overwrite the old table */213 *table = new_table;214}215 216void dm_helpers_dp_update_branch_info(217 struct dc_context *ctx,218 const struct dc_link *link)219{}220 221static void dm_helpers_construct_old_payload(222 struct drm_dp_mst_topology_mgr *mgr,223 struct drm_dp_mst_topology_state *mst_state,224 struct drm_dp_mst_atomic_payload *new_payload,225 struct drm_dp_mst_atomic_payload *old_payload)226{227 struct drm_dp_mst_atomic_payload *pos;228 int pbn_per_slot = dfixed_trunc(mst_state->pbn_div);229 u8 next_payload_vc_start = mgr->next_start_slot;230 u8 payload_vc_start = new_payload->vc_start_slot;231 u8 allocated_time_slots;232 233 *old_payload = *new_payload;234 235 /* Set correct time_slots/PBN of old payload.236 * other fields (delete & dsc_enabled) in237 * struct drm_dp_mst_atomic_payload are don't care fields238 * while calling drm_dp_remove_payload_part2()239 */240 list_for_each_entry(pos, &mst_state->payloads, next) {241 if (pos != new_payload &&242 pos->vc_start_slot > payload_vc_start &&243 pos->vc_start_slot < next_payload_vc_start)244 next_payload_vc_start = pos->vc_start_slot;245 }246 247 allocated_time_slots = next_payload_vc_start - payload_vc_start;248 249 old_payload->time_slots = allocated_time_slots;250 old_payload->pbn = allocated_time_slots * pbn_per_slot;251}252 253/*254 * Writes payload allocation table in immediate downstream device.255 */256bool dm_helpers_dp_mst_write_payload_allocation_table(257 struct dc_context *ctx,258 const struct dc_stream_state *stream,259 struct dc_dp_mst_stream_allocation_table *proposed_table,260 bool enable)261{262 struct amdgpu_dm_connector *aconnector;263 struct drm_dp_mst_topology_state *mst_state;264 struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;265 struct drm_dp_mst_topology_mgr *mst_mgr;266 267 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;268 /* Accessing the connector state is required for vcpi_slots allocation269 * and directly relies on behaviour in commit check270 * that blocks before commit guaranteeing that the state271 * is not gonna be swapped while still in use in commit tail272 */273 274 if (!aconnector || !aconnector->mst_root)275 return false;276 277 mst_mgr = &aconnector->mst_root->mst_mgr;278 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);279 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);280 281 if (enable) {282 target_payload = new_payload;283 284 /* It's OK for this to fail */285 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload);286 } else {287 /* construct old payload by VCPI*/288 dm_helpers_construct_old_payload(mst_mgr, mst_state,289 new_payload, &old_payload);290 target_payload = &old_payload;291 292 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload);293 }294 295 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or296 * AUX message. The sequence is slot 1-63 allocated sequence for each297 * stream. AMD ASIC stream slot allocation should follow the same298 * sequence. copy DRM MST allocation to dc299 */300 fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);301 302 return true;303}304 305/*306 * poll pending down reply307 */308void dm_helpers_dp_mst_poll_pending_down_reply(309 struct dc_context *ctx,310 const struct dc_link *link)311{}312 313/*314 * Clear payload allocation table before enable MST DP link.315 */316void dm_helpers_dp_mst_clear_payload_allocation_table(317 struct dc_context *ctx,318 const struct dc_link *link)319{}320 321/*322 * Polls for ACT (allocation change trigger) handled and sends323 * ALLOCATE_PAYLOAD message.324 */325enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(326 struct dc_context *ctx,327 const struct dc_stream_state *stream)328{329 struct amdgpu_dm_connector *aconnector;330 struct drm_dp_mst_topology_mgr *mst_mgr;331 int ret;332 333 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;334 335 if (!aconnector || !aconnector->mst_root)336 return ACT_FAILED;337 338 mst_mgr = &aconnector->mst_root->mst_mgr;339 340 if (!mst_mgr->mst_state)341 return ACT_FAILED;342 343 ret = drm_dp_check_act_status(mst_mgr);344 345 if (ret)346 return ACT_FAILED;347 348 return ACT_SUCCESS;349}350 351void dm_helpers_dp_mst_send_payload_allocation(352 struct dc_context *ctx,353 const struct dc_stream_state *stream)354{355 struct amdgpu_dm_connector *aconnector;356 struct drm_dp_mst_topology_state *mst_state;357 struct drm_dp_mst_topology_mgr *mst_mgr;358 struct drm_dp_mst_atomic_payload *new_payload;359 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;360 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;361 int ret = 0;362 363 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;364 365 if (!aconnector || !aconnector->mst_root)366 return;367 368 mst_mgr = &aconnector->mst_root->mst_mgr;369 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);370 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);371 372 ret = drm_dp_add_payload_part2(mst_mgr, new_payload);373 374 if (ret) {375 amdgpu_dm_set_mst_status(&aconnector->mst_status,376 set_flag, false);377 } else {378 amdgpu_dm_set_mst_status(&aconnector->mst_status,379 set_flag, true);380 amdgpu_dm_set_mst_status(&aconnector->mst_status,381 clr_flag, false);382 }383}384 385void dm_helpers_dp_mst_update_mst_mgr_for_deallocation(386 struct dc_context *ctx,387 const struct dc_stream_state *stream)388{389 struct amdgpu_dm_connector *aconnector;390 struct drm_dp_mst_topology_state *mst_state;391 struct drm_dp_mst_topology_mgr *mst_mgr;392 struct drm_dp_mst_atomic_payload *new_payload, old_payload;393 enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;394 enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD;395 396 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;397 398 if (!aconnector || !aconnector->mst_root)399 return;400 401 mst_mgr = &aconnector->mst_root->mst_mgr;402 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);403 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);404 dm_helpers_construct_old_payload(mst_mgr, mst_state,405 new_payload, &old_payload);406 407 drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload);408 409 amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true);410 amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false);411 }412 413void dm_dtn_log_begin(struct dc_context *ctx,414 struct dc_log_buffer_ctx *log_ctx)415{416 static const char msg[] = "[dtn begin]\n";417 418 if (!log_ctx) {419 pr_info("%s", msg);420 return;421 }422 423 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);424}425 426__printf(3, 4)427void dm_dtn_log_append_v(struct dc_context *ctx,428 struct dc_log_buffer_ctx *log_ctx,429 const char *msg, ...)430{431 va_list args;432 size_t total;433 int n;434 435 if (!log_ctx) {436 /* No context, redirect to dmesg. */437 struct va_format vaf;438 439 vaf.fmt = msg;440 vaf.va = &args;441 442 va_start(args, msg);443 pr_info("%pV", &vaf);444 va_end(args);445 446 return;447 }448 449 /* Measure the output. */450 va_start(args, msg);451 n = vsnprintf(NULL, 0, msg, args);452 va_end(args);453 454 if (n <= 0)455 return;456 457 /* Reallocate the string buffer as needed. */458 total = log_ctx->pos + n + 1;459 460 if (total > log_ctx->size) {461 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL);462 463 if (buf) {464 memcpy(buf, log_ctx->buf, log_ctx->pos);465 kfree(log_ctx->buf);466 467 log_ctx->buf = buf;468 log_ctx->size = total;469 }470 }471 472 if (!log_ctx->buf)473 return;474 475 /* Write the formatted string to the log buffer. */476 va_start(args, msg);477 n = vscnprintf(478 log_ctx->buf + log_ctx->pos,479 log_ctx->size - log_ctx->pos,480 msg,481 args);482 va_end(args);483 484 if (n > 0)485 log_ctx->pos += n;486}487 488void dm_dtn_log_end(struct dc_context *ctx,489 struct dc_log_buffer_ctx *log_ctx)490{491 static const char msg[] = "[dtn end]\n";492 493 if (!log_ctx) {494 pr_info("%s", msg);495 return;496 }497 498 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);499}500 501bool dm_helpers_dp_mst_start_top_mgr(502 struct dc_context *ctx,503 const struct dc_link *link,504 bool boot)505{506 struct amdgpu_dm_connector *aconnector = link->priv;507 int ret;508 509 if (!aconnector) {510 DRM_ERROR("Failed to find connector for link!");511 return false;512 }513 514 if (boot) {515 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",516 aconnector, aconnector->base.base.id);517 return true;518 }519 520 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",521 aconnector, aconnector->base.base.id);522 523 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);524 if (ret < 0) {525 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");526 return false;527 }528 529 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0],530 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK);531 532 return true;533}534 535bool dm_helpers_dp_mst_stop_top_mgr(536 struct dc_context *ctx,537 struct dc_link *link)538{539 struct amdgpu_dm_connector *aconnector = link->priv;540 541 if (!aconnector) {542 DRM_ERROR("Failed to find connector for link!");543 return false;544 }545 546 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",547 aconnector, aconnector->base.base.id);548 549 if (aconnector->mst_mgr.mst_state == true) {550 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);551 link->cur_link_settings.lane_count = 0;552 }553 554 return false;555}556 557bool dm_helpers_dp_read_dpcd(558 struct dc_context *ctx,559 const struct dc_link *link,560 uint32_t address,561 uint8_t *data,562 uint32_t size)563{564 565 struct amdgpu_dm_connector *aconnector = link->priv;566 567 if (!aconnector)568 return false;569 570 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data,571 size) == size;572}573 574bool dm_helpers_dp_write_dpcd(575 struct dc_context *ctx,576 const struct dc_link *link,577 uint32_t address,578 const uint8_t *data,579 uint32_t size)580{581 struct amdgpu_dm_connector *aconnector = link->priv;582 583 if (!aconnector)584 return false;585 586 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,587 address, (uint8_t *)data, size) > 0;588}589 590bool dm_helpers_submit_i2c(591 struct dc_context *ctx,592 const struct dc_link *link,593 struct i2c_command *cmd)594{595 struct amdgpu_dm_connector *aconnector = link->priv;596 struct i2c_msg *msgs;597 int i = 0;598 int num = cmd->number_of_payloads;599 bool result;600 601 if (!aconnector) {602 DRM_ERROR("Failed to find connector for link!");603 return false;604 }605 606 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);607 608 if (!msgs)609 return false;610 611 for (i = 0; i < num; i++) {612 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;613 msgs[i].addr = cmd->payloads[i].address;614 msgs[i].len = cmd->payloads[i].length;615 msgs[i].buf = cmd->payloads[i].data;616 }617 618 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;619 620 kfree(msgs);621 622 return result;623}624 625static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,626 bool is_write_cmd,627 unsigned char cmd,628 unsigned int length,629 unsigned int offset,630 unsigned char *data)631{632 bool success = false;633 unsigned char rc_data[16] = {0};634 unsigned char rc_offset[4] = {0};635 unsigned char rc_length[2] = {0};636 unsigned char rc_cmd = 0;637 unsigned char rc_result = 0xFF;638 unsigned char i = 0;639 int ret;640 641 if (is_write_cmd) {642 // write rc data643 memmove(rc_data, data, length);644 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));645 }646 647 // write rc offset648 rc_offset[0] = (unsigned char) offset & 0xFF;649 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;650 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;651 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;652 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));653 654 // write rc length655 rc_length[0] = (unsigned char) length & 0xFF;656 rc_length[1] = (unsigned char) (length >> 8) & 0xFF;657 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));658 659 // write rc cmd660 rc_cmd = cmd | 0x80;661 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));662 663 if (ret < 0) {664 DRM_ERROR("%s: write cmd ..., err = %d\n", __func__, ret);665 return false;666 }667 668 // poll until active is 0669 for (i = 0; i < 10; i++) {670 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));671 if (rc_cmd == cmd)672 // active is 0673 break;674 msleep(10);675 }676 677 // read rc result678 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));679 success = (rc_result == 0);680 681 if (success && !is_write_cmd) {682 // read rc data683 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);684 }685 686 drm_dbg_dp(aux->drm_dev, "success = %d\n", success);687 688 return success;689}690 691static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)692{693 unsigned char data[16] = {0};694 695 drm_dbg_dp(aux->drm_dev, "Start\n");696 697 // Step 2698 data[0] = 'P';699 data[1] = 'R';700 data[2] = 'I';701 data[3] = 'U';702 data[4] = 'S';703 704 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))705 return;706 707 // Step 3 and 4708 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))709 return;710 711 data[0] &= (~(1 << 1)); // set bit 1 to 0712 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))713 return;714 715 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))716 return;717 718 data[0] &= (~(1 << 1)); // set bit 1 to 0719 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))720 return;721 722 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))723 return;724 725 data[0] &= (~(1 << 1)); // set bit 1 to 0726 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))727 return;728 729 // Step 3 and 5730 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))731 return;732 733 data[0] |= (1 << 1); // set bit 1 to 1734 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))735 return;736 737 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))738 return;739 740 data[0] |= (1 << 1); // set bit 1 to 1741 742 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))743 return;744 745 data[0] |= (1 << 1); // set bit 1 to 1746 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))747 return;748 749 // Step 6750 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))751 return;752 753 drm_dbg_dp(aux->drm_dev, "Done\n");754}755 756/* MST Dock */757static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";758 759static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(760 struct drm_dp_aux *aux,761 const struct dc_stream_state *stream,762 bool enable)763{764 uint8_t ret = 0;765 766 drm_dbg_dp(aux->drm_dev,767 "MST_DSC Configure DSC to non-virtual dpcd synaptics\n");768 769 if (enable) {770 /* When DSC is enabled on previous boot and reboot with the hub,771 * there is a chance that Synaptics hub gets stuck during reboot sequence.772 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream773 */774 if (!stream->link->link_status.link_active &&775 memcmp(stream->link->dpcd_caps.branch_dev_name,776 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)777 apply_synaptics_fifo_reset_wa(aux);778 779 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);780 DRM_INFO("MST_DSC Send DSC enable to synaptics\n");781 782 } else {783 /* Synaptics hub not support virtual dpcd,784 * external monitor occur garbage while disable DSC,785 * Disable DSC only when entire link status turn to false,786 */787 if (!stream->link->link_status.link_active) {788 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);789 DRM_INFO("MST_DSC Send DSC disable to synaptics\n");790 }791 }792 793 return ret;794}795 796bool dm_helpers_dp_write_dsc_enable(797 struct dc_context *ctx,798 const struct dc_stream_state *stream,799 bool enable)800{801 static const uint8_t DSC_DISABLE;802 static const uint8_t DSC_DECODING = 0x01;803 static const uint8_t DSC_PASSTHROUGH = 0x02;804 805 struct amdgpu_dm_connector *aconnector =806 (struct amdgpu_dm_connector *)stream->dm_stream_context;807 struct drm_device *dev = aconnector->base.dev;808 struct drm_dp_mst_port *port;809 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;810 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;811 uint8_t ret = 0;812 813 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {814 if (!aconnector->dsc_aux)815 return false;816 817 // apply w/a to synaptics818 if (needs_dsc_aux_workaround(aconnector->dc_link) &&819 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)820 return write_dsc_enable_synaptics_non_virtual_dpcd_mst(821 aconnector->dsc_aux, stream, enable_dsc);822 823 port = aconnector->mst_output_port;824 825 if (enable) {826 if (port->passthrough_aux) {827 ret = drm_dp_dpcd_write(port->passthrough_aux,828 DP_DSC_ENABLE,829 &enable_passthrough, 1);830 drm_dbg_dp(dev,831 "MST_DSC Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",832 ret);833 }834 835 ret = drm_dp_dpcd_write(aconnector->dsc_aux,836 DP_DSC_ENABLE, &enable_dsc, 1);837 drm_dbg_dp(dev,838 "MST_DSC Sent DSC decoding enable to %s port, ret = %u\n",839 (port->passthrough_aux) ? "remote RX" :840 "virtual dpcd",841 ret);842 } else {843 ret = drm_dp_dpcd_write(aconnector->dsc_aux,844 DP_DSC_ENABLE, &enable_dsc, 1);845 drm_dbg_dp(dev,846 "MST_DSC Sent DSC decoding disable to %s port, ret = %u\n",847 (port->passthrough_aux) ? "remote RX" :848 "virtual dpcd",849 ret);850 851 if (port->passthrough_aux) {852 ret = drm_dp_dpcd_write(port->passthrough_aux,853 DP_DSC_ENABLE,854 &enable_passthrough, 1);855 drm_dbg_dp(dev,856 "MST_DSC Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",857 ret);858 }859 }860 }861 862 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {863 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {864 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);865 drm_dbg_dp(dev,866 "SST_DSC Send DSC %s to SST RX\n",867 enable_dsc ? "enable" : "disable");868 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {869 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);870 drm_dbg_dp(dev,871 "SST_DSC Send DSC %s to DP-HDMI PCON\n",872 enable_dsc ? "enable" : "disable");873 }874 }875 876 return ret;877}878 879bool dm_helpers_is_dp_sink_present(struct dc_link *link)880{881 bool dp_sink_present;882 struct amdgpu_dm_connector *aconnector = link->priv;883 884 if (!aconnector) {885 BUG_ON("Failed to find connector for link!");886 return true;887 }888 889 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);890 dp_sink_present = dc_link_is_dp_sink_present(link);891 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);892 return dp_sink_present;893}894 895enum dc_edid_status dm_helpers_read_local_edid(896 struct dc_context *ctx,897 struct dc_link *link,898 struct dc_sink *sink)899{900 struct amdgpu_dm_connector *aconnector = link->priv;901 struct drm_connector *connector = &aconnector->base;902 struct i2c_adapter *ddc;903 int retry = 3;904 enum dc_edid_status edid_status;905 struct edid *edid;906 907 if (link->aux_mode)908 ddc = &aconnector->dm_dp_aux.aux.ddc;909 else910 ddc = &aconnector->i2c->base;911 912 /* some dongles read edid incorrectly the first time,913 * do check sum and retry to make sure read correct edid.914 */915 do {916 917 edid = drm_get_edid(&aconnector->base, ddc);918 919 /* DP Compliance Test 4.2.2.6 */920 if (link->aux_mode && connector->edid_corrupt)921 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);922 923 if (!edid && connector->edid_corrupt) {924 connector->edid_corrupt = false;925 return EDID_BAD_CHECKSUM;926 }927 928 if (!edid)929 return EDID_NO_RESPONSE;930 931 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);932 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);933 934 /* We don't need the original edid anymore */935 kfree(edid);936 937 edid_status = dm_helpers_parse_edid_caps(938 link,939 &sink->dc_edid,940 &sink->edid_caps);941 942 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);943 944 if (edid_status != EDID_OK)945 DRM_ERROR("EDID err: %d, on connector: %s",946 edid_status,947 aconnector->base.name);948 if (link->aux_mode) {949 union test_request test_request = {0};950 union test_response test_response = {0};951 952 dm_helpers_dp_read_dpcd(ctx,953 link,954 DP_TEST_REQUEST,955 &test_request.raw,956 sizeof(union test_request));957 958 if (!test_request.bits.EDID_READ)959 return edid_status;960 961 test_response.bits.EDID_CHECKSUM_WRITE = 1;962 963 dm_helpers_dp_write_dpcd(ctx,964 link,965 DP_TEST_EDID_CHECKSUM,966 &sink->dc_edid.raw_edid[sink->dc_edid.length-1],967 1);968 969 dm_helpers_dp_write_dpcd(ctx,970 link,971 DP_TEST_RESPONSE,972 &test_response.raw,973 sizeof(test_response));974 975 }976 977 return edid_status;978}979int dm_helper_dmub_aux_transfer_sync(980 struct dc_context *ctx,981 const struct dc_link *link,982 struct aux_payload *payload,983 enum aux_return_code_type *operation_result)984{985 if (!link->hpd_status) {986 *operation_result = AUX_RET_ERROR_HPD_DISCON;987 return -1;988 }989 990 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload,991 operation_result);992}993 994int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,995 const struct dc_link *link,996 struct set_config_cmd_payload *payload,997 enum set_config_status *operation_result)998{999 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload,1000 operation_result);1001}1002 1003void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)1004{1005 /* TODO: something */1006}1007 1008void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)1009{1010 // TODO:1011 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);1012}1013 1014void dm_helpers_init_panel_settings(1015 struct dc_context *ctx,1016 struct dc_panel_config *panel_config,1017 struct dc_sink *sink)1018{1019 // Extra Panel Power Sequence1020 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;1021 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;1022 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;1023 panel_config->pps.extra_post_t7_ms = 0;1024 panel_config->pps.extra_pre_t11_ms = 0;1025 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;1026 panel_config->pps.extra_post_OUI_ms = 0;1027 // Feature DSC1028 panel_config->dsc.disable_dsc_edp = false;1029 panel_config->dsc.force_dsc_edp_policy = 0;1030}1031 1032void dm_helpers_override_panel_settings(1033 struct dc_context *ctx,1034 struct dc_panel_config *panel_config)1035{1036 // Feature DSC1037 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)1038 panel_config->dsc.disable_dsc_edp = true;1039}1040 1041void *dm_helpers_allocate_gpu_mem(1042 struct dc_context *ctx,1043 enum dc_gpu_mem_alloc_type type,1044 size_t size,1045 long long *addr)1046{1047 struct amdgpu_device *adev = ctx->driver_context;1048 1049 return dm_allocate_gpu_mem(adev, type, size, addr);1050}1051 1052void dm_helpers_free_gpu_mem(1053 struct dc_context *ctx,1054 enum dc_gpu_mem_alloc_type type,1055 void *pvMem)1056{1057 struct amdgpu_device *adev = ctx->driver_context;1058 struct dal_allocation *da;1059 1060 /* walk the da list in DM */1061 list_for_each_entry(da, &adev->dm.da_list, list) {1062 if (pvMem == da->cpu_ptr) {1063 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);1064 list_del(&da->list);1065 kfree(da);1066 break;1067 }1068 }1069}1070 1071bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)1072{1073 enum dc_irq_source irq_source;1074 bool ret;1075 1076 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;1077 1078 ret = dc_interrupt_set(ctx->dc, irq_source, enable);1079 1080 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",1081 enable ? "en" : "dis", ret);1082 return ret;1083}1084 1085void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)1086{1087 /* TODO: virtual DPCD */1088 struct dc_link *link = stream->link;1089 union down_spread_ctrl old_downspread;1090 union down_spread_ctrl new_downspread;1091 1092 if (link->aux_access_disabled)1093 return;1094 1095 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,1096 &old_downspread.raw,1097 sizeof(old_downspread)))1098 return;1099 1100 new_downspread.raw = old_downspread.raw;1101 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =1102 (stream->ignore_msa_timing_param) ? 1 : 0;1103 1104 if (new_downspread.raw != old_downspread.raw)1105 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,1106 &new_downspread.raw,1107 sizeof(new_downspread));1108}1109 1110bool dm_helpers_dp_handle_test_pattern_request(1111 struct dc_context *ctx,1112 const struct dc_link *link,1113 union link_test_pattern dpcd_test_pattern,1114 union test_misc dpcd_test_params)1115{1116 enum dp_test_pattern test_pattern;1117 enum dp_test_pattern_color_space test_pattern_color_space =1118 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;1119 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;1120 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;1121 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;1122 struct pipe_ctx *pipe_ctx = NULL;1123 struct amdgpu_dm_connector *aconnector = link->priv;1124 struct drm_device *dev = aconnector->base.dev;1125 struct dc_state *dc_state = ctx->dc->current_state;1126 struct clk_mgr *clk_mgr = ctx->dc->clk_mgr;1127 int i;1128 1129 for (i = 0; i < MAX_PIPES; i++) {1130 if (pipes[i].stream == NULL)1131 continue;1132 1133 if (pipes[i].stream->link == link && !pipes[i].top_pipe &&1134 !pipes[i].prev_odm_pipe) {1135 pipe_ctx = &pipes[i];1136 break;1137 }1138 }1139 1140 if (pipe_ctx == NULL)1141 return false;1142 1143 switch (dpcd_test_pattern.bits.PATTERN) {1144 case LINK_TEST_PATTERN_COLOR_RAMP:1145 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;1146 break;1147 case LINK_TEST_PATTERN_VERTICAL_BARS:1148 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;1149 break; /* black and white */1150 case LINK_TEST_PATTERN_COLOR_SQUARES:1151 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==1152 TEST_DYN_RANGE_VESA ?1153 DP_TEST_PATTERN_COLOR_SQUARES :1154 DP_TEST_PATTERN_COLOR_SQUARES_CEA);1155 break;1156 default:1157 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;1158 break;1159 }1160 1161 if (dpcd_test_params.bits.CLR_FORMAT == 0)1162 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;1163 else1164 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?1165 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :1166 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;1167 1168 switch (dpcd_test_params.bits.BPC) {1169 case 0: // 6 bits1170 requestColorDepth = COLOR_DEPTH_666;1171 break;1172 case 1: // 8 bits1173 requestColorDepth = COLOR_DEPTH_888;1174 break;1175 case 2: // 10 bits1176 requestColorDepth = COLOR_DEPTH_101010;1177 break;1178 case 3: // 12 bits1179 requestColorDepth = COLOR_DEPTH_121212;1180 break;1181 default:1182 break;1183 }1184 1185 switch (dpcd_test_params.bits.CLR_FORMAT) {1186 case 0:1187 requestPixelEncoding = PIXEL_ENCODING_RGB;1188 break;1189 case 1:1190 requestPixelEncoding = PIXEL_ENCODING_YCBCR422;1191 break;1192 case 2:1193 requestPixelEncoding = PIXEL_ENCODING_YCBCR444;1194 break;1195 default:1196 requestPixelEncoding = PIXEL_ENCODING_RGB;1197 break;1198 }1199 1200 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED1201 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth)1202 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED1203 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {1204 drm_dbg(dev,1205 "original bpc %d pix encoding %d, changing to %d %d\n",1206 pipe_ctx->stream->timing.display_color_depth,1207 pipe_ctx->stream->timing.pixel_encoding,1208 requestColorDepth,1209 requestPixelEncoding);1210 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;1211 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;1212 1213 dc_link_update_dsc_config(pipe_ctx);1214 1215 aconnector->timing_changed = true;1216 /* store current timing */1217 if (aconnector->timing_requested)1218 *aconnector->timing_requested = pipe_ctx->stream->timing;1219 else1220 drm_err(dev, "timing storage failed\n");1221 1222 }1223 1224 pipe_ctx->stream->test_pattern.type = test_pattern;1225 pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;1226 1227 /* Temp W/A for compliance test failure */1228 dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false;1229 dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?1230 clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz;1231 dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz;1232 ctx->dc->clk_mgr->funcs->update_clocks(1233 ctx->dc->clk_mgr,1234 dc_state,1235 false);1236 1237 dc_link_dp_set_test_pattern(1238 (struct dc_link *) link,1239 test_pattern,1240 test_pattern_color_space,1241 NULL,1242 NULL,1243 0);1244 1245 return false;1246}1247 1248void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)1249{1250 // TODO1251}1252 1253void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)1254{1255 struct amdgpu_device *adev = ctx->driver_context;1256 1257 if (adev->dm.idle_workqueue) {1258 adev->dm.idle_workqueue->enable = enable;1259 if (enable && !adev->dm.idle_workqueue->running && amdgpu_dm_is_headless(adev))1260 schedule_work(&adev->dm.idle_workqueue->work);1261 }1262}1263 1264void dm_helpers_dp_mst_update_branch_bandwidth(1265 struct dc_context *ctx,1266 struct dc_link *link)1267{1268 // TODO1269}1270 1271static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)1272{1273 bool ret_val = false;1274 1275 switch (branch_dev_id) {1276 case DP_BRANCH_DEVICE_ID_0060AD:1277 case DP_BRANCH_DEVICE_ID_00E04C:1278 case DP_BRANCH_DEVICE_ID_90CC24:1279 ret_val = true;1280 break;1281 default:1282 break;1283 }1284 1285 return ret_val;1286}1287 1288enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)1289{1290 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;1291 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;1292 1293 switch (dpcd_caps->dongle_type) {1294 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:1295 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&1296 dpcd_caps->allow_invalid_MSA_timing_param == true &&1297 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id))1298 as_type = FREESYNC_TYPE_PCON_IN_WHITELIST;1299 break;1300 default:1301 break;1302 }1303 1304 return as_type;1305}1306 1307bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream)1308{1309 // TODO1310 return false;1311}1312 1313bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream)1314{1315 // TODO1316 return false;1317}