735 lines · c
1/*2 * Copyright 2018 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#undef TRACE_SYSTEM27#define TRACE_SYSTEM amdgpu_dm28 29#if !defined(_AMDGPU_DM_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)30#define _AMDGPU_DM_TRACE_H_31 32#include <linux/tracepoint.h>33#include <drm/drm_connector.h>34#include <drm/drm_crtc.h>35#include <drm/drm_plane.h>36#include <drm/drm_fourcc.h>37#include <drm/drm_framebuffer.h>38#include <drm/drm_encoder.h>39#include <drm/drm_atomic.h>40#include "dc/inc/hw/optc.h"41 42#include "dc/inc/core_types.h"43 44DECLARE_EVENT_CLASS(amdgpu_dc_reg_template,45 TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),46 TP_ARGS(count, reg, value),47 48 TP_STRUCT__entry(49 __field(uint32_t, reg)50 __field(uint32_t, value)51 ),52 53 TP_fast_assign(54 __entry->reg = reg;55 __entry->value = value;56 *count = *count + 1;57 ),58 59 TP_printk("reg=0x%08lx, value=0x%08lx",60 (unsigned long)__entry->reg,61 (unsigned long)__entry->value)62);63 64DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_rreg,65 TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),66 TP_ARGS(count, reg, value));67 68DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_wreg,69 TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),70 TP_ARGS(count, reg, value));71 72TRACE_EVENT(amdgpu_dc_performance,73 TP_PROTO(unsigned long read_count, unsigned long write_count,74 unsigned long *last_read, unsigned long *last_write,75 const char *func, unsigned int line),76 TP_ARGS(read_count, write_count, last_read, last_write, func, line),77 TP_STRUCT__entry(78 __field(uint32_t, reads)79 __field(uint32_t, writes)80 __field(uint32_t, read_delta)81 __field(uint32_t, write_delta)82 __string(func, func)83 __field(uint32_t, line)84 ),85 TP_fast_assign(86 __entry->reads = read_count;87 __entry->writes = write_count;88 __entry->read_delta = read_count - *last_read;89 __entry->write_delta = write_count - *last_write;90 __assign_str(func);91 __entry->line = line;92 *last_read = read_count;93 *last_write = write_count;94 ),95 TP_printk("%s:%d reads=%08ld (%08ld total), writes=%08ld (%08ld total)",96 __get_str(func), __entry->line,97 (unsigned long)__entry->read_delta,98 (unsigned long)__entry->reads,99 (unsigned long)__entry->write_delta,100 (unsigned long)__entry->writes)101);102 103TRACE_EVENT(amdgpu_dm_connector_atomic_check,104 TP_PROTO(const struct drm_connector_state *state),105 TP_ARGS(state),106 107 TP_STRUCT__entry(108 __field(uint32_t, conn_id)109 __field(const struct drm_connector_state *, conn_state)110 __field(const struct drm_atomic_state *, state)111 __field(const struct drm_crtc_commit *, commit)112 __field(uint32_t, crtc_id)113 __field(uint32_t, best_encoder_id)114 __field(enum drm_link_status, link_status)115 __field(bool, self_refresh_aware)116 __field(enum hdmi_picture_aspect, picture_aspect_ratio)117 __field(unsigned int, content_type)118 __field(unsigned int, hdcp_content_type)119 __field(unsigned int, content_protection)120 __field(unsigned int, scaling_mode)121 __field(u32, colorspace)122 __field(u8, max_requested_bpc)123 __field(u8, max_bpc)124 ),125 126 TP_fast_assign(127 __entry->conn_id = state->connector->base.id;128 __entry->conn_state = state;129 __entry->state = state->state;130 __entry->commit = state->commit;131 __entry->crtc_id = state->crtc ? state->crtc->base.id : 0;132 __entry->best_encoder_id = state->best_encoder ?133 state->best_encoder->base.id : 0;134 __entry->link_status = state->link_status;135 __entry->self_refresh_aware = state->self_refresh_aware;136 __entry->picture_aspect_ratio = state->picture_aspect_ratio;137 __entry->content_type = state->content_type;138 __entry->hdcp_content_type = state->hdcp_content_type;139 __entry->content_protection = state->content_protection;140 __entry->scaling_mode = state->scaling_mode;141 __entry->colorspace = state->colorspace;142 __entry->max_requested_bpc = state->max_requested_bpc;143 __entry->max_bpc = state->max_bpc;144 ),145 146 TP_printk("conn_id=%u conn_state=%p state=%p commit=%p crtc_id=%u "147 "best_encoder_id=%u link_status=%d self_refresh_aware=%d "148 "picture_aspect_ratio=%d content_type=%u "149 "hdcp_content_type=%u content_protection=%u scaling_mode=%u "150 "colorspace=%u max_requested_bpc=%u max_bpc=%u",151 __entry->conn_id, __entry->conn_state, __entry->state,152 __entry->commit, __entry->crtc_id, __entry->best_encoder_id,153 __entry->link_status, __entry->self_refresh_aware,154 __entry->picture_aspect_ratio, __entry->content_type,155 __entry->hdcp_content_type, __entry->content_protection,156 __entry->scaling_mode, __entry->colorspace,157 __entry->max_requested_bpc, __entry->max_bpc)158);159 160TRACE_EVENT(amdgpu_dm_crtc_atomic_check,161 TP_PROTO(const struct drm_crtc_state *state),162 TP_ARGS(state),163 164 TP_STRUCT__entry(165 __field(const struct drm_atomic_state *, state)166 __field(const struct drm_crtc_state *, crtc_state)167 __field(const struct drm_crtc_commit *, commit)168 __field(uint32_t, crtc_id)169 __field(bool, enable)170 __field(bool, active)171 __field(bool, planes_changed)172 __field(bool, mode_changed)173 __field(bool, active_changed)174 __field(bool, connectors_changed)175 __field(bool, zpos_changed)176 __field(bool, color_mgmt_changed)177 __field(bool, no_vblank)178 __field(bool, async_flip)179 __field(bool, vrr_enabled)180 __field(bool, self_refresh_active)181 __field(u32, plane_mask)182 __field(u32, connector_mask)183 __field(u32, encoder_mask)184 ),185 186 TP_fast_assign(187 __entry->state = state->state;188 __entry->crtc_state = state;189 __entry->crtc_id = state->crtc->base.id;190 __entry->commit = state->commit;191 __entry->enable = state->enable;192 __entry->active = state->active;193 __entry->planes_changed = state->planes_changed;194 __entry->mode_changed = state->mode_changed;195 __entry->active_changed = state->active_changed;196 __entry->connectors_changed = state->connectors_changed;197 __entry->zpos_changed = state->zpos_changed;198 __entry->color_mgmt_changed = state->color_mgmt_changed;199 __entry->no_vblank = state->no_vblank;200 __entry->async_flip = state->async_flip;201 __entry->vrr_enabled = state->vrr_enabled;202 __entry->self_refresh_active = state->self_refresh_active;203 __entry->plane_mask = state->plane_mask;204 __entry->connector_mask = state->connector_mask;205 __entry->encoder_mask = state->encoder_mask;206 ),207 208 TP_printk("crtc_id=%u crtc_state=%p state=%p commit=%p changed("209 "planes=%d mode=%d active=%d conn=%d zpos=%d color_mgmt=%d) "210 "state(enable=%d active=%d async_flip=%d vrr_enabled=%d "211 "self_refresh_active=%d no_vblank=%d) mask(plane=%x conn=%x "212 "enc=%x)",213 __entry->crtc_id, __entry->crtc_state, __entry->state,214 __entry->commit, __entry->planes_changed,215 __entry->mode_changed, __entry->active_changed,216 __entry->connectors_changed, __entry->zpos_changed,217 __entry->color_mgmt_changed, __entry->enable, __entry->active,218 __entry->async_flip, __entry->vrr_enabled,219 __entry->self_refresh_active, __entry->no_vblank,220 __entry->plane_mask, __entry->connector_mask,221 __entry->encoder_mask)222);223 224DECLARE_EVENT_CLASS(amdgpu_dm_plane_state_template,225 TP_PROTO(const struct drm_plane_state *state),226 TP_ARGS(state),227 TP_STRUCT__entry(228 __field(uint32_t, plane_id)229 __field(enum drm_plane_type, plane_type)230 __field(const struct drm_plane_state *, plane_state)231 __field(const struct drm_atomic_state *, state)232 __field(uint32_t, crtc_id)233 __field(uint32_t, fb_id)234 __field(uint32_t, fb_format)235 __field(uint8_t, fb_planes)236 __field(uint64_t, fb_modifier)237 __field(const struct dma_fence *, fence)238 __field(int32_t, crtc_x)239 __field(int32_t, crtc_y)240 __field(uint32_t, crtc_w)241 __field(uint32_t, crtc_h)242 __field(uint32_t, src_x)243 __field(uint32_t, src_y)244 __field(uint32_t, src_w)245 __field(uint32_t, src_h)246 __field(u32, alpha)247 __field(uint32_t, pixel_blend_mode)248 __field(unsigned int, rotation)249 __field(unsigned int, zpos)250 __field(unsigned int, normalized_zpos)251 __field(enum drm_color_encoding, color_encoding)252 __field(enum drm_color_range, color_range)253 __field(bool, visible)254 ),255 256 TP_fast_assign(257 __entry->plane_id = state->plane->base.id;258 __entry->plane_type = state->plane->type;259 __entry->plane_state = state;260 __entry->state = state->state;261 __entry->crtc_id = state->crtc ? state->crtc->base.id : 0;262 __entry->fb_id = state->fb ? state->fb->base.id : 0;263 __entry->fb_format = state->fb ? state->fb->format->format : 0;264 __entry->fb_planes = state->fb ? state->fb->format->num_planes : 0;265 __entry->fb_modifier = state->fb ? state->fb->modifier : 0;266 __entry->fence = state->fence;267 __entry->crtc_x = state->crtc_x;268 __entry->crtc_y = state->crtc_y;269 __entry->crtc_w = state->crtc_w;270 __entry->crtc_h = state->crtc_h;271 __entry->src_x = state->src_x >> 16;272 __entry->src_y = state->src_y >> 16;273 __entry->src_w = state->src_w >> 16;274 __entry->src_h = state->src_h >> 16;275 __entry->alpha = state->alpha;276 __entry->pixel_blend_mode = state->pixel_blend_mode;277 __entry->rotation = state->rotation;278 __entry->zpos = state->zpos;279 __entry->normalized_zpos = state->normalized_zpos;280 __entry->color_encoding = state->color_encoding;281 __entry->color_range = state->color_range;282 __entry->visible = state->visible;283 ),284 285 TP_printk("plane_id=%u plane_type=%d plane_state=%p state=%p "286 "crtc_id=%u fb(id=%u fmt=%c%c%c%c planes=%u mod=%llu) "287 "fence=%p crtc_x=%d crtc_y=%d crtc_w=%u crtc_h=%u "288 "src_x=%u src_y=%u src_w=%u src_h=%u alpha=%u "289 "pixel_blend_mode=%u rotation=%u zpos=%u "290 "normalized_zpos=%u color_encoding=%d color_range=%d "291 "visible=%d",292 __entry->plane_id, __entry->plane_type, __entry->plane_state,293 __entry->state, __entry->crtc_id, __entry->fb_id,294 (__entry->fb_format & 0xff) ? (__entry->fb_format & 0xff) : 'N',295 ((__entry->fb_format >> 8) & 0xff) ? ((__entry->fb_format >> 8) & 0xff) : 'O',296 ((__entry->fb_format >> 16) & 0xff) ? ((__entry->fb_format >> 16) & 0xff) : 'N',297 ((__entry->fb_format >> 24) & 0x7f) ? ((__entry->fb_format >> 24) & 0x7f) : 'E',298 __entry->fb_planes,299 __entry->fb_modifier, __entry->fence, __entry->crtc_x,300 __entry->crtc_y, __entry->crtc_w, __entry->crtc_h,301 __entry->src_x, __entry->src_y, __entry->src_w, __entry->src_h,302 __entry->alpha, __entry->pixel_blend_mode, __entry->rotation,303 __entry->zpos, __entry->normalized_zpos,304 __entry->color_encoding, __entry->color_range,305 __entry->visible)306);307 308DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_plane_atomic_check,309 TP_PROTO(const struct drm_plane_state *state),310 TP_ARGS(state));311 312DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_atomic_update_cursor,313 TP_PROTO(const struct drm_plane_state *state),314 TP_ARGS(state));315 316TRACE_EVENT(amdgpu_dm_atomic_state_template,317 TP_PROTO(const struct drm_atomic_state *state),318 TP_ARGS(state),319 320 TP_STRUCT__entry(321 __field(const struct drm_atomic_state *, state)322 __field(bool, allow_modeset)323 __field(bool, legacy_cursor_update)324 __field(bool, async_update)325 __field(bool, duplicated)326 __field(int, num_connector)327 __field(int, num_private_objs)328 ),329 330 TP_fast_assign(331 __entry->state = state;332 __entry->allow_modeset = state->allow_modeset;333 __entry->legacy_cursor_update = state->legacy_cursor_update;334 __entry->async_update = state->async_update;335 __entry->duplicated = state->duplicated;336 __entry->num_connector = state->num_connector;337 __entry->num_private_objs = state->num_private_objs;338 ),339 340 TP_printk("state=%p allow_modeset=%d legacy_cursor_update=%d "341 "async_update=%d duplicated=%d num_connector=%d "342 "num_private_objs=%d",343 __entry->state, __entry->allow_modeset, __entry->legacy_cursor_update,344 __entry->async_update, __entry->duplicated, __entry->num_connector,345 __entry->num_private_objs)346);347 348DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_begin,349 TP_PROTO(const struct drm_atomic_state *state),350 TP_ARGS(state));351 352DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_finish,353 TP_PROTO(const struct drm_atomic_state *state),354 TP_ARGS(state));355 356DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_check_begin,357 TP_PROTO(const struct drm_atomic_state *state),358 TP_ARGS(state));359 360TRACE_EVENT(amdgpu_dm_atomic_check_finish,361 TP_PROTO(const struct drm_atomic_state *state, int res),362 TP_ARGS(state, res),363 364 TP_STRUCT__entry(365 __field(const struct drm_atomic_state *, state)366 __field(int, res)367 __field(bool, async_update)368 __field(bool, allow_modeset)369 ),370 371 TP_fast_assign(372 __entry->state = state;373 __entry->res = res;374 __entry->async_update = state->async_update;375 __entry->allow_modeset = state->allow_modeset;376 ),377 378 TP_printk("state=%p res=%d async_update=%d allow_modeset=%d",379 __entry->state, __entry->res,380 __entry->async_update, __entry->allow_modeset)381);382 383TRACE_EVENT(amdgpu_dm_dc_pipe_state,384 TP_PROTO(int pipe_idx, const struct dc_plane_state *plane_state,385 const struct dc_stream_state *stream,386 const struct plane_resource *plane_res,387 int update_flags),388 TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),389 390 TP_STRUCT__entry(391 __field(int, pipe_idx)392 __field(const void *, stream)393 __field(int, stream_w)394 __field(int, stream_h)395 __field(int, dst_x)396 __field(int, dst_y)397 __field(int, dst_w)398 __field(int, dst_h)399 __field(int, src_x)400 __field(int, src_y)401 __field(int, src_w)402 __field(int, src_h)403 __field(int, clip_x)404 __field(int, clip_y)405 __field(int, clip_w)406 __field(int, clip_h)407 __field(int, recout_x)408 __field(int, recout_y)409 __field(int, recout_w)410 __field(int, recout_h)411 __field(int, viewport_x)412 __field(int, viewport_y)413 __field(int, viewport_w)414 __field(int, viewport_h)415 __field(int, flip_immediate)416 __field(int, surface_pitch)417 __field(int, format)418 __field(int, swizzle)419 __field(unsigned int, update_flags)420 ),421 422 TP_fast_assign(423 __entry->pipe_idx = pipe_idx;424 __entry->stream = stream;425 __entry->stream_w = stream->timing.h_addressable;426 __entry->stream_h = stream->timing.v_addressable;427 __entry->dst_x = plane_state->dst_rect.x;428 __entry->dst_y = plane_state->dst_rect.y;429 __entry->dst_w = plane_state->dst_rect.width;430 __entry->dst_h = plane_state->dst_rect.height;431 __entry->src_x = plane_state->src_rect.x;432 __entry->src_y = plane_state->src_rect.y;433 __entry->src_w = plane_state->src_rect.width;434 __entry->src_h = plane_state->src_rect.height;435 __entry->clip_x = plane_state->clip_rect.x;436 __entry->clip_y = plane_state->clip_rect.y;437 __entry->clip_w = plane_state->clip_rect.width;438 __entry->clip_h = plane_state->clip_rect.height;439 __entry->recout_x = plane_res->scl_data.recout.x;440 __entry->recout_y = plane_res->scl_data.recout.y;441 __entry->recout_w = plane_res->scl_data.recout.width;442 __entry->recout_h = plane_res->scl_data.recout.height;443 __entry->viewport_x = plane_res->scl_data.viewport.x;444 __entry->viewport_y = plane_res->scl_data.viewport.y;445 __entry->viewport_w = plane_res->scl_data.viewport.width;446 __entry->viewport_h = plane_res->scl_data.viewport.height;447 __entry->flip_immediate = plane_state->flip_immediate;448 __entry->surface_pitch = plane_state->plane_size.surface_pitch;449 __entry->format = plane_state->format;450 __entry->swizzle = plane_state->tiling_info.gfx9.swizzle;451 __entry->update_flags = update_flags;452 ),453 TP_printk("pipe_idx=%d stream=%p rct(%d,%d) dst=(%d,%d,%d,%d) "454 "src=(%d,%d,%d,%d) clip=(%d,%d,%d,%d) recout=(%d,%d,%d,%d) "455 "viewport=(%d,%d,%d,%d) flip_immediate=%d pitch=%d "456 "format=%d swizzle=%d update_flags=%x",457 __entry->pipe_idx,458 __entry->stream,459 __entry->stream_w,460 __entry->stream_h,461 __entry->dst_x,462 __entry->dst_y,463 __entry->dst_w,464 __entry->dst_h,465 __entry->src_x,466 __entry->src_y,467 __entry->src_w,468 __entry->src_h,469 __entry->clip_x,470 __entry->clip_y,471 __entry->clip_w,472 __entry->clip_h,473 __entry->recout_x,474 __entry->recout_y,475 __entry->recout_w,476 __entry->recout_h,477 __entry->viewport_x,478 __entry->viewport_y,479 __entry->viewport_w,480 __entry->viewport_h,481 __entry->flip_immediate,482 __entry->surface_pitch,483 __entry->format,484 __entry->swizzle,485 __entry->update_flags486 )487);488 489TRACE_EVENT(amdgpu_dm_dc_clocks_state,490 TP_PROTO(const struct dc_clocks *clk),491 TP_ARGS(clk),492 493 TP_STRUCT__entry(494 __field(int, dispclk_khz)495 __field(int, dppclk_khz)496 __field(int, disp_dpp_voltage_level_khz)497 __field(int, dcfclk_khz)498 __field(int, socclk_khz)499 __field(int, dcfclk_deep_sleep_khz)500 __field(int, fclk_khz)501 __field(int, phyclk_khz)502 __field(int, dramclk_khz)503 __field(int, p_state_change_support)504 __field(int, prev_p_state_change_support)505 __field(int, pwr_state)506 __field(int, dtm_level)507 __field(int, max_supported_dppclk_khz)508 __field(int, max_supported_dispclk_khz)509 __field(int, bw_dppclk_khz)510 __field(int, bw_dispclk_khz)511 ),512 TP_fast_assign(513 __entry->dispclk_khz = clk->dispclk_khz;514 __entry->dppclk_khz = clk->dppclk_khz;515 __entry->dcfclk_khz = clk->dcfclk_khz;516 __entry->socclk_khz = clk->socclk_khz;517 __entry->dcfclk_deep_sleep_khz = clk->dcfclk_deep_sleep_khz;518 __entry->fclk_khz = clk->fclk_khz;519 __entry->phyclk_khz = clk->phyclk_khz;520 __entry->dramclk_khz = clk->dramclk_khz;521 __entry->p_state_change_support = clk->p_state_change_support;522 __entry->prev_p_state_change_support = clk->prev_p_state_change_support;523 __entry->pwr_state = clk->pwr_state;524 __entry->prev_p_state_change_support = clk->prev_p_state_change_support;525 __entry->dtm_level = clk->dtm_level;526 __entry->max_supported_dppclk_khz = clk->max_supported_dppclk_khz;527 __entry->max_supported_dispclk_khz = clk->max_supported_dispclk_khz;528 __entry->bw_dppclk_khz = clk->bw_dppclk_khz;529 __entry->bw_dispclk_khz = clk->bw_dispclk_khz;530 ),531 TP_printk("dispclk_khz=%d dppclk_khz=%d disp_dpp_voltage_level_khz=%d dcfclk_khz=%d socclk_khz=%d "532 "dcfclk_deep_sleep_khz=%d fclk_khz=%d phyclk_khz=%d "533 "dramclk_khz=%d p_state_change_support=%d "534 "prev_p_state_change_support=%d pwr_state=%d prev_p_state_change_support=%d "535 "dtm_level=%d max_supported_dppclk_khz=%d max_supported_dispclk_khz=%d "536 "bw_dppclk_khz=%d bw_dispclk_khz=%d ",537 __entry->dispclk_khz,538 __entry->dppclk_khz,539 __entry->disp_dpp_voltage_level_khz,540 __entry->dcfclk_khz,541 __entry->socclk_khz,542 __entry->dcfclk_deep_sleep_khz,543 __entry->fclk_khz,544 __entry->phyclk_khz,545 __entry->dramclk_khz,546 __entry->p_state_change_support,547 __entry->prev_p_state_change_support,548 __entry->pwr_state,549 __entry->prev_p_state_change_support,550 __entry->dtm_level,551 __entry->max_supported_dppclk_khz,552 __entry->max_supported_dispclk_khz,553 __entry->bw_dppclk_khz,554 __entry->bw_dispclk_khz555 )556);557 558TRACE_EVENT(amdgpu_dm_dce_clocks_state,559 TP_PROTO(const struct dce_bw_output *clk),560 TP_ARGS(clk),561 562 TP_STRUCT__entry(563 __field(bool, cpuc_state_change_enable)564 __field(bool, cpup_state_change_enable)565 __field(bool, stutter_mode_enable)566 __field(bool, nbp_state_change_enable)567 __field(bool, all_displays_in_sync)568 __field(int, sclk_khz)569 __field(int, sclk_deep_sleep_khz)570 __field(int, yclk_khz)571 __field(int, dispclk_khz)572 __field(int, blackout_recovery_time_us)573 ),574 TP_fast_assign(575 __entry->cpuc_state_change_enable = clk->cpuc_state_change_enable;576 __entry->cpup_state_change_enable = clk->cpup_state_change_enable;577 __entry->stutter_mode_enable = clk->stutter_mode_enable;578 __entry->nbp_state_change_enable = clk->nbp_state_change_enable;579 __entry->all_displays_in_sync = clk->all_displays_in_sync;580 __entry->sclk_khz = clk->sclk_khz;581 __entry->sclk_deep_sleep_khz = clk->sclk_deep_sleep_khz;582 __entry->yclk_khz = clk->yclk_khz;583 __entry->dispclk_khz = clk->dispclk_khz;584 __entry->blackout_recovery_time_us = clk->blackout_recovery_time_us;585 ),586 TP_printk("cpuc_state_change_enable=%d cpup_state_change_enable=%d stutter_mode_enable=%d "587 "nbp_state_change_enable=%d all_displays_in_sync=%d sclk_khz=%d sclk_deep_sleep_khz=%d "588 "yclk_khz=%d dispclk_khz=%d blackout_recovery_time_us=%d",589 __entry->cpuc_state_change_enable,590 __entry->cpup_state_change_enable,591 __entry->stutter_mode_enable,592 __entry->nbp_state_change_enable,593 __entry->all_displays_in_sync,594 __entry->sclk_khz,595 __entry->sclk_deep_sleep_khz,596 __entry->yclk_khz,597 __entry->dispclk_khz,598 __entry->blackout_recovery_time_us599 )600);601 602TRACE_EVENT(amdgpu_dmub_trace_high_irq,603 TP_PROTO(uint32_t trace_code, uint32_t tick_count, uint32_t param0,604 uint32_t param1),605 TP_ARGS(trace_code, tick_count, param0, param1),606 TP_STRUCT__entry(607 __field(uint32_t, trace_code)608 __field(uint32_t, tick_count)609 __field(uint32_t, param0)610 __field(uint32_t, param1)611 ),612 TP_fast_assign(613 __entry->trace_code = trace_code;614 __entry->tick_count = tick_count;615 __entry->param0 = param0;616 __entry->param1 = param1;617 ),618 TP_printk("trace_code=%u tick_count=%u param0=%u param1=%u",619 __entry->trace_code, __entry->tick_count,620 __entry->param0, __entry->param1)621);622 623TRACE_EVENT(amdgpu_refresh_rate_track,624 TP_PROTO(int crtc_index, ktime_t refresh_rate_ns, uint32_t refresh_rate_hz),625 TP_ARGS(crtc_index, refresh_rate_ns, refresh_rate_hz),626 TP_STRUCT__entry(627 __field(int, crtc_index)628 __field(ktime_t, refresh_rate_ns)629 __field(uint32_t, refresh_rate_hz)630 ),631 TP_fast_assign(632 __entry->crtc_index = crtc_index;633 __entry->refresh_rate_ns = refresh_rate_ns;634 __entry->refresh_rate_hz = refresh_rate_hz;635 ),636 TP_printk("crtc_index=%d refresh_rate=%dHz (%lld)",637 __entry->crtc_index,638 __entry->refresh_rate_hz,639 __entry->refresh_rate_ns)640);641 642TRACE_EVENT(dcn_fpu,643 TP_PROTO(bool begin, const char *function, const int line, const int recursion_depth),644 TP_ARGS(begin, function, line, recursion_depth),645 646 TP_STRUCT__entry(647 __field(bool, begin)648 __field(const char *, function)649 __field(int, line)650 __field(int, recursion_depth)651 ),652 TP_fast_assign(653 __entry->begin = begin;654 __entry->function = function;655 __entry->line = line;656 __entry->recursion_depth = recursion_depth;657 ),658 TP_printk("%s: recursion_depth: %d: %s()+%d:",659 __entry->begin ? "begin" : "end",660 __entry->recursion_depth,661 __entry->function,662 __entry->line663 )664);665 666TRACE_EVENT(dcn_optc_lock_unlock_state,667 TP_PROTO(const struct optc *optc_state, int instance, bool lock, const char *function, const int line),668 TP_ARGS(optc_state, instance, lock, function, line),669 670 TP_STRUCT__entry(671 __field(const char *, function)672 __field(int, instance)673 __field(bool, lock)674 __field(int, line)675 __field(int, opp_count)676 __field(int, max_h_total)677 __field(int, max_v_total)678 __field(int, min_h_blank)679 __field(int, min_h_sync_width)680 __field(int, min_v_sync_width)681 __field(int, min_v_blank)682 __field(int, min_v_blank_interlace)683 __field(int, vstartup_start)684 __field(int, vupdate_offset)685 __field(int, vupdate_width)686 __field(int, vready_offset)687 ),688 TP_fast_assign(689 __entry->function = function;690 __entry->instance = instance;691 __entry->lock = lock;692 __entry->line = line;693 __entry->opp_count = optc_state->opp_count;694 __entry->max_h_total = optc_state->max_h_total;695 __entry->max_v_total = optc_state->max_v_total;696 __entry->min_h_blank = optc_state->min_h_blank;697 __entry->min_h_sync_width = optc_state->min_h_sync_width;698 __entry->min_v_sync_width = optc_state->min_v_sync_width;699 __entry->min_v_blank = optc_state->min_v_blank;700 __entry->min_v_blank_interlace = optc_state->min_v_blank_interlace;701 __entry->vstartup_start = optc_state->vstartup_start;702 __entry->vupdate_offset = optc_state->vupdate_offset;703 __entry->vupdate_width = optc_state->vupdate_width;704 __entry->vready_offset = optc_state->vupdate_offset;705 ),706 TP_printk("%s: %s()+%d: optc_instance=%d opp_count=%d max_h_total=%d max_v_total=%d "707 "min_h_blank=%d min_h_sync_width=%d min_v_sync_width=%d min_v_blank=%d "708 "min_v_blank_interlace=%d vstartup_start=%d vupdate_offset=%d vupdate_width=%d "709 "vready_offset=%d",710 __entry->lock ? "Lock" : "Unlock",711 __entry->function,712 __entry->line,713 __entry->instance,714 __entry->opp_count,715 __entry->max_h_total,716 __entry->max_v_total,717 __entry->min_h_blank,718 __entry->min_h_sync_width,719 __entry->min_v_sync_width,720 __entry->min_v_blank,721 __entry->min_v_blank_interlace,722 __entry->vstartup_start,723 __entry->vupdate_offset,724 __entry->vupdate_width,725 __entry->vready_offset726 )727);728 729#endif /* _AMDGPU_DM_TRACE_H_ */730 731#undef TRACE_INCLUDE_PATH732#define TRACE_INCLUDE_PATH .733#define TRACE_INCLUDE_FILE amdgpu_dm_trace734#include <trace/define_trace.h>735