brintos / linux-shallow public Read only

1/*2 * Copyright 2012-2023 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef DC_INTERFACE_H_27#define DC_INTERFACE_H_28 29#include "dc_types.h"30#include "dc_state.h"31#include "dc_plane.h"32#include "grph_object_defs.h"33#include "logger_types.h"34#include "hdcp_msg_types.h"35#include "gpio_types.h"36#include "link_service_types.h"37#include "grph_object_ctrl_defs.h"38#include <inc/hw/opp.h>39 40#include "hwss/hw_sequencer.h"41#include "inc/compressor.h"42#include "inc/hw/dmcu.h"43#include "dml/display_mode_lib.h"44 45#include "dml2/dml2_wrapper.h"46 47#include "dmub/inc/dmub_cmd.h"48 49#include "spl/dc_spl_types.h"50 51struct abm_save_restore;52 53/* forward declaration */54struct aux_payload;55struct set_config_cmd_payload;56struct dmub_notification;57 58#define DC_VER "3.2.301"59 60#define MAX_SURFACES 361#define MAX_PLANES 662#define MAX_STREAMS 663#define MIN_VIEWPORT_SIZE 1264#define MAX_NUM_EDP 265#define MAX_HOST_ROUTERS_NUM 266 67/* Display Core Interfaces */68struct dc_versions {69	const char *dc_ver;70	struct dmcu_version dmcu_version;71};72 73enum dp_protocol_version {74	DP_VERSION_1_4 = 0,75	DP_VERSION_2_1,76	DP_VERSION_UNKNOWN,77};78 79enum dc_plane_type {80	DC_PLANE_TYPE_INVALID,81	DC_PLANE_TYPE_DCE_RGB,82	DC_PLANE_TYPE_DCE_UNDERLAY,83	DC_PLANE_TYPE_DCN_UNIVERSAL,84};85 86// Sizes defined as multiples of 64KB87enum det_size {88	DET_SIZE_DEFAULT = 0,89	DET_SIZE_192KB = 3,90	DET_SIZE_256KB = 4,91	DET_SIZE_320KB = 5,92	DET_SIZE_384KB = 693};94 95 96struct dc_plane_cap {97	enum dc_plane_type type;98	uint32_t per_pixel_alpha : 1;99	struct {100		uint32_t argb8888 : 1;101		uint32_t nv12 : 1;102		uint32_t fp16 : 1;103		uint32_t p010 : 1;104		uint32_t ayuv : 1;105	} pixel_format_support;106	// max upscaling factor x1000107	// upscaling factors are always >= 1108	// for example, 1080p -> 8K is 4.0, or 4000 raw value109	struct {110		uint32_t argb8888;111		uint32_t nv12;112		uint32_t fp16;113	} max_upscale_factor;114	// max downscale factor x1000115	// downscale factors are always <= 1116	// for example, 8K -> 1080p is 0.25, or 250 raw value117	struct {118		uint32_t argb8888;119		uint32_t nv12;120		uint32_t fp16;121	} max_downscale_factor;122	// minimal width/height123	uint32_t min_width;124	uint32_t min_height;125};126 127/**128 * DOC: color-management-caps129 *130 * **Color management caps (DPP and MPC)**131 *132 * Modules/color calculates various color operations which are translated to133 * abstracted HW. DCE 5-12 had almost no important changes, but starting with134 * DCN1, every new generation comes with fairly major differences in color135 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can136 * decide mapping to HW block based on logical capabilities.137 */138 139/**140 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma141 * @srgb: RGB color space transfer func142 * @bt2020: BT.2020 transfer func143 * @gamma2_2: standard gamma144 * @pq: perceptual quantizer transfer function145 * @hlg: hybrid log–gamma transfer function146 */147struct rom_curve_caps {148	uint16_t srgb : 1;149	uint16_t bt2020 : 1;150	uint16_t gamma2_2 : 1;151	uint16_t pq : 1;152	uint16_t hlg : 1;153};154 155/**156 * struct dpp_color_caps - color pipeline capabilities for display pipe and157 * plane blocks158 *159 * @dcn_arch: all DCE generations treated the same160 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,161 * just plain 256-entry lookup162 * @icsc: input color space conversion163 * @dgam_ram: programmable degamma LUT164 * @post_csc: post color space conversion, before gamut remap165 * @gamma_corr: degamma correction166 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared167 * with MPC by setting mpc:shared_3d_lut flag168 * @ogam_ram: programmable out/blend gamma LUT169 * @ocsc: output color space conversion170 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes171 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT172 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT173 *174 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)175 */176struct dpp_color_caps {177	uint16_t dcn_arch : 1;178	uint16_t input_lut_shared : 1;179	uint16_t icsc : 1;180	uint16_t dgam_ram : 1;181	uint16_t post_csc : 1;182	uint16_t gamma_corr : 1;183	uint16_t hw_3d_lut : 1;184	uint16_t ogam_ram : 1;185	uint16_t ocsc : 1;186	uint16_t dgam_rom_for_yuv : 1;187	struct rom_curve_caps dgam_rom_caps;188	struct rom_curve_caps ogam_rom_caps;189};190 191/**192 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and193 * plane combined blocks194 *195 * @gamut_remap: color transformation matrix196 * @ogam_ram: programmable out gamma LUT197 * @ocsc: output color space conversion matrix198 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT199 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single200 * instance201 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT202 */203struct mpc_color_caps {204	uint16_t gamut_remap : 1;205	uint16_t ogam_ram : 1;206	uint16_t ocsc : 1;207	uint16_t num_3dluts : 3;208	uint16_t shared_3d_lut:1;209	struct rom_curve_caps ogam_rom_caps;210};211 212/**213 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks214 * @dpp: color pipes caps for DPP215 * @mpc: color pipes caps for MPC216 */217struct dc_color_caps {218	struct dpp_color_caps dpp;219	struct mpc_color_caps mpc;220};221 222struct dc_dmub_caps {223	bool psr;224	bool mclk_sw;225	bool subvp_psr;226	bool gecc_enable;227	uint8_t fams_ver;228};229 230struct dc_caps {231	uint32_t max_streams;232	uint32_t max_links;233	uint32_t max_audios;234	uint32_t max_slave_planes;235	uint32_t max_slave_yuv_planes;236	uint32_t max_slave_rgb_planes;237	uint32_t max_planes;238	uint32_t max_downscale_ratio;239	uint32_t i2c_speed_in_khz;240	uint32_t i2c_speed_in_khz_hdcp;241	uint32_t dmdata_alloc_size;242	unsigned int max_cursor_size;243	unsigned int max_video_width;244	/*245	 * max video plane width that can be safely assumed to be always246	 * supported by single DPP pipe.247	 */248	unsigned int max_optimizable_video_width;249	unsigned int min_horizontal_blanking_period;250	int linear_pitch_alignment;251	bool dcc_const_color;252	bool dynamic_audio;253	bool is_apu;254	bool dual_link_dvi;255	bool post_blend_color_processing;256	bool force_dp_tps4_for_cp2520;257	bool disable_dp_clk_share;258	bool psp_setup_panel_mode;259	bool extended_aux_timeout_support;260	bool dmcub_support;261	bool zstate_support;262	bool ips_support;263	uint32_t num_of_internal_disp;264	enum dp_protocol_version max_dp_protocol_version;265	unsigned int mall_size_per_mem_channel;266	unsigned int mall_size_total;267	unsigned int cursor_cache_size;268	struct dc_plane_cap planes[MAX_PLANES];269	struct dc_color_caps color;270	struct dc_dmub_caps dmub_caps;271	bool dp_hpo;272	bool dp_hdmi21_pcon_support;273	bool edp_dsc_support;274	bool vbios_lttpr_aware;275	bool vbios_lttpr_enable;276	uint32_t max_otg_num;277	uint32_t max_cab_allocation_bytes;278	uint32_t cache_line_size;279	uint32_t cache_num_ways;280	uint16_t subvp_fw_processing_delay_us;281	uint8_t subvp_drr_max_vblank_margin_us;282	uint16_t subvp_prefetch_end_to_mall_start_us;283	uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height284	uint16_t subvp_pstate_allow_width_us;285	uint16_t subvp_vertical_int_margin_us;286	bool seamless_odm;287	uint32_t max_v_total;288	uint32_t max_disp_clock_khz_at_vmin;289	uint8_t subvp_drr_vblank_start_margin_us;290	bool cursor_not_scaled;291	bool dcmode_power_limits_present;292	bool sequential_ono;293	/* Conservative limit for DCC cases which require ODM4:1 to support*/294	uint32_t dcc_plane_width_limit;295};296 297struct dc_bug_wa {298	bool no_connect_phy_config;299	bool dedcn20_305_wa;300	bool skip_clock_update;301	bool lt_early_cr_pattern;302	struct {303		uint8_t uclk : 1;304		uint8_t fclk : 1;305		uint8_t dcfclk : 1;306		uint8_t dcfclk_ds: 1;307	} clock_update_disable_mask;308	bool skip_psr_ips_crtc_disable;309};310struct dc_dcc_surface_param {311	struct dc_size surface_size;312	enum surface_pixel_format format;313	unsigned int plane0_pitch;314	struct dc_size plane1_size;315	unsigned int plane1_pitch;316	union {317		enum swizzle_mode_values swizzle_mode;318		enum swizzle_mode_addr3_values swizzle_mode_addr3;319	};320	enum dc_scan_direction scan;321};322 323struct dc_dcc_setting {324	unsigned int max_compressed_blk_size;325	unsigned int max_uncompressed_blk_size;326	bool independent_64b_blks;327	//These bitfields to be used starting with DCN 3.0328	struct {329		uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)330		uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN 3.0331		uint32_t dcc_256_128_128 : 1;		//available starting with DCN 3.0332		uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN 3.0 (the best compression case)333		uint32_t dcc_256_256 : 1;  //available in ASICs starting with DCN 4.0x (the best compression case)334		uint32_t dcc_256_128 : 1;  //available in ASICs starting with DCN 4.0x335		uint32_t dcc_256_64 : 1;   //available in ASICs starting with DCN 4.0x (the worst compression case)336	} dcc_controls;337};338 339struct dc_surface_dcc_cap {340	union {341		struct {342			struct dc_dcc_setting rgb;343		} grph;344 345		struct {346			struct dc_dcc_setting luma;347			struct dc_dcc_setting chroma;348		} video;349	};350 351	bool capable;352	bool const_color_support;353};354 355struct dc_static_screen_params {356	struct {357		bool force_trigger;358		bool cursor_update;359		bool surface_update;360		bool overlay_update;361	} triggers;362	unsigned int num_frames;363};364 365 366/* Surface update type is used by dc_update_surfaces_and_stream367 * The update type is determined at the very beginning of the function based368 * on parameters passed in and decides how much programming (or updating) is369 * going to be done during the call.370 *371 * UPDATE_TYPE_FAST is used for really fast updates that do not require much372 * logical calculations or hardware register programming. This update MUST be373 * ISR safe on windows. Currently fast update will only be used to flip surface374 * address.375 *376 * UPDATE_TYPE_MED is used for slower updates which require significant hw377 * re-programming however do not affect bandwidth consumption or clock378 * requirements. At present, this is the level at which front end updates379 * that do not require us to run bw_calcs happen. These are in/out transfer func380 * updates, viewport offset changes, recout size changes and pixel depth changes.381 * This update can be done at ISR, but we want to minimize how often this happens.382 *383 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our384 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front385 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or386 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do387 * a full update. This cannot be done at ISR level and should be a rare event.388 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting389 * underscan we don't expect to see this call at all.390 */391 392enum surface_update_type {393	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */394	UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/395	UPDATE_TYPE_FULL, /* may need to shuffle resources */396};397 398/* Forward declaration*/399struct dc;400struct dc_plane_state;401struct dc_state;402 403struct dc_cap_funcs {404	bool (*get_dcc_compression_cap)(const struct dc *dc,405			const struct dc_dcc_surface_param *input,406			struct dc_surface_dcc_cap *output);407	bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);408};409 410struct link_training_settings;411 412union allow_lttpr_non_transparent_mode {413	struct {414		bool DP1_4A : 1;415		bool DP2_0 : 1;416	} bits;417	unsigned char raw;418};419 420/* Structure to hold configuration flags set by dm at dc creation. */421struct dc_config {422	bool gpu_vm_support;423	bool disable_disp_pll_sharing;424	bool fbc_support;425	bool disable_fractional_pwm;426	bool allow_seamless_boot_optimization;427	bool seamless_boot_edp_requested;428	bool edp_not_connected;429	bool edp_no_power_sequencing;430	bool force_enum_edp;431	bool forced_clocks;432	union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;433	bool multi_mon_pp_mclk_switch;434	bool disable_dmcu;435	bool enable_4to1MPC;436	bool enable_windowed_mpo_odm;437	bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520438	uint32_t allow_edp_hotplug_detection;439	bool clamp_min_dcfclk;440	uint64_t vblank_alignment_dto_params;441	uint8_t  vblank_alignment_max_frame_time_diff;442	bool is_asymmetric_memory;443	bool is_single_rank_dimm;444	bool is_vmin_only_asic;445	bool use_spl;446	bool prefer_easf;447	bool use_pipe_ctx_sync_logic;448	bool ignore_dpref_ss;449	bool enable_mipi_converter_optimization;450	bool use_default_clock_table;451	bool force_bios_enable_lttpr;452	uint8_t force_bios_fixed_vs;453	int sdpif_request_limit_words_per_umc;454	bool dc_mode_clk_limit_support;455	bool EnableMinDispClkODM;456	bool enable_auto_dpm_test_logs;457	unsigned int disable_ips;458	unsigned int disable_ips_in_vpb;459	bool usb4_bw_alloc_support;460	bool allow_0_dtb_clk;461	bool use_assr_psp_message;462	bool support_edp0_on_dp1;463	unsigned int enable_fpo_flicker_detection;464	bool disable_hbr_audio_dp2;465	bool consolidated_dpia_dp_lt;466};467 468enum visual_confirm {469	VISUAL_CONFIRM_DISABLE = 0,470	VISUAL_CONFIRM_SURFACE = 1,471	VISUAL_CONFIRM_HDR = 2,472	VISUAL_CONFIRM_MPCTREE = 4,473	VISUAL_CONFIRM_PSR = 5,474	VISUAL_CONFIRM_SWAPCHAIN = 6,475	VISUAL_CONFIRM_FAMS = 7,476	VISUAL_CONFIRM_SWIZZLE = 9,477	VISUAL_CONFIRM_REPLAY = 12,478	VISUAL_CONFIRM_SUBVP = 14,479	VISUAL_CONFIRM_MCLK_SWITCH = 16,480	VISUAL_CONFIRM_FAMS2 = 19,481	VISUAL_CONFIRM_HW_CURSOR = 20,482};483 484enum dc_psr_power_opts {485	psr_power_opt_invalid = 0x0,486	psr_power_opt_smu_opt_static_screen = 0x1,487	psr_power_opt_z10_static_screen = 0x10,488	psr_power_opt_ds_disable_allow = 0x100,489};490 491enum dml_hostvm_override_opts {492	DML_HOSTVM_NO_OVERRIDE = 0x0,493	DML_HOSTVM_OVERRIDE_FALSE = 0x1,494	DML_HOSTVM_OVERRIDE_TRUE = 0x2,495};496 497enum dc_replay_power_opts {498	replay_power_opt_invalid		= 0x0,499	replay_power_opt_smu_opt_static_screen	= 0x1,500	replay_power_opt_z10_static_screen	= 0x10,501};502 503enum dcc_option {504	DCC_ENABLE = 0,505	DCC_DISABLE = 1,506	DCC_HALF_REQ_DISALBE = 2,507};508 509enum in_game_fams_config {510	INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams511	INGAME_FAMS_DISABLE, // disable in-game fams512	INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display513	INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies514};515 516/**517 * enum pipe_split_policy - Pipe split strategy supported by DCN518 *519 * This enum is used to define the pipe split policy supported by DCN. By520 * default, DC favors MPC_SPLIT_DYNAMIC.521 */522enum pipe_split_policy {523	/**524	 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the525	 * pipe in order to bring the best trade-off between performance and526	 * power consumption. This is the recommended option.527	 */528	MPC_SPLIT_DYNAMIC = 0,529 530	/**531	 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not532	 * try any sort of split optimization.533	 */534	MPC_SPLIT_AVOID = 1,535 536	/**537	 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to538	 * optimize the pipe utilization when using a single display; if the539	 * user connects to a second display, DC will avoid pipe split.540	 */541	MPC_SPLIT_AVOID_MULT_DISP = 2,542};543 544enum wm_report_mode {545	WM_REPORT_DEFAULT = 0,546	WM_REPORT_OVERRIDE = 1,547};548enum dtm_pstate{549	dtm_level_p0 = 0,/*highest voltage*/550	dtm_level_p1,551	dtm_level_p2,552	dtm_level_p3,553	dtm_level_p4,/*when active_display_count = 0*/554};555 556enum dcn_pwr_state {557	DCN_PWR_STATE_UNKNOWN = -1,558	DCN_PWR_STATE_MISSION_MODE = 0,559	DCN_PWR_STATE_LOW_POWER = 3,560};561 562enum dcn_zstate_support_state {563	DCN_ZSTATE_SUPPORT_UNKNOWN,564	DCN_ZSTATE_SUPPORT_ALLOW,565	DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,566	DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,567	DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,568	DCN_ZSTATE_SUPPORT_DISALLOW,569};570 571/*572 * struct dc_clocks - DC pipe clocks573 *574 * For any clocks that may differ per pipe only the max is stored in this575 * structure576 */577struct dc_clocks {578	int dispclk_khz;579	int actual_dispclk_khz;580	int dppclk_khz;581	int actual_dppclk_khz;582	int disp_dpp_voltage_level_khz;583	int dcfclk_khz;584	int socclk_khz;585	int dcfclk_deep_sleep_khz;586	int fclk_khz;587	int phyclk_khz;588	int dramclk_khz;589	bool p_state_change_support;590	enum dcn_zstate_support_state zstate_support;591	bool dtbclk_en;592	int ref_dtbclk_khz;593	bool fclk_p_state_change_support;594	enum dcn_pwr_state pwr_state;595	/*596	 * Elements below are not compared for the purposes of597	 * optimization required598	 */599	bool prev_p_state_change_support;600	bool fclk_prev_p_state_change_support;601	int num_ways;602	int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM];603 604	/*605	 * @fw_based_mclk_switching606	 *607	 * DC has a mechanism that leverage the variable refresh rate to switch608	 * memory clock in cases that we have a large latency to achieve the609	 * memory clock change and a short vblank window. DC has some610	 * requirements to enable this feature, and this field describes if the611	 * system support or not such a feature.612	 */613	bool fw_based_mclk_switching;614	bool fw_based_mclk_switching_shut_down;615	int prev_num_ways;616	enum dtm_pstate dtm_level;617	int max_supported_dppclk_khz;618	int max_supported_dispclk_khz;619	int bw_dppclk_khz; /*a copy of dppclk_khz*/620	int bw_dispclk_khz;621	int idle_dramclk_khz;622	int idle_fclk_khz;623};624 625struct dc_bw_validation_profile {626	bool enable;627 628	unsigned long long total_ticks;629	unsigned long long voltage_level_ticks;630	unsigned long long watermark_ticks;631	unsigned long long rq_dlg_ticks;632 633	unsigned long long total_count;634	unsigned long long skip_fast_count;635	unsigned long long skip_pass_count;636	unsigned long long skip_fail_count;637};638 639#define BW_VAL_TRACE_SETUP() \640		unsigned long long end_tick = 0; \641		unsigned long long voltage_level_tick = 0; \642		unsigned long long watermark_tick = 0; \643		unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \644				dm_get_timestamp(dc->ctx) : 0645 646#define BW_VAL_TRACE_COUNT() \647		if (dc->debug.bw_val_profile.enable) \648			dc->debug.bw_val_profile.total_count++649 650#define BW_VAL_TRACE_SKIP(status) \651		if (dc->debug.bw_val_profile.enable) { \652			if (!voltage_level_tick) \653				voltage_level_tick = dm_get_timestamp(dc->ctx); \654			dc->debug.bw_val_profile.skip_ ## status ## _count++; \655		}656 657#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \658		if (dc->debug.bw_val_profile.enable) \659			voltage_level_tick = dm_get_timestamp(dc->ctx)660 661#define BW_VAL_TRACE_END_WATERMARKS() \662		if (dc->debug.bw_val_profile.enable) \663			watermark_tick = dm_get_timestamp(dc->ctx)664 665#define BW_VAL_TRACE_FINISH() \666		if (dc->debug.bw_val_profile.enable) { \667			end_tick = dm_get_timestamp(dc->ctx); \668			dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \669			dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \670			if (watermark_tick) { \671				dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \672				dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \673			} \674		}675 676union mem_low_power_enable_options {677	struct {678		bool vga: 1;679		bool i2c: 1;680		bool dmcu: 1;681		bool dscl: 1;682		bool cm: 1;683		bool mpc: 1;684		bool optc: 1;685		bool vpg: 1;686		bool afmt: 1;687	} bits;688	uint32_t u32All;689};690 691union root_clock_optimization_options {692	struct {693		bool dpp: 1;694		bool dsc: 1;695		bool hdmistream: 1;696		bool hdmichar: 1;697		bool dpstream: 1;698		bool symclk32_se: 1;699		bool symclk32_le: 1;700		bool symclk_fe: 1;701		bool physymclk: 1;702		bool dpiasymclk: 1;703		uint32_t reserved: 22;704	} bits;705	uint32_t u32All;706};707 708union fine_grain_clock_gating_enable_options {709	struct {710		bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */711		bool dchub : 1;	   /* Display controller hub */712		bool dchubbub : 1;713		bool dpp : 1;	   /* Display pipes and planes */714		bool opp : 1;	   /* Output pixel processing */715		bool optc : 1;	   /* Output pipe timing combiner */716		bool dio : 1;	   /* Display output */717		bool dwb : 1;	   /* Display writeback */718		bool mmhubbub : 1; /* Multimedia hub */719		bool dmu : 1;	   /* Display core management unit */720		bool az : 1;	   /* Azalia */721		bool dchvm : 1;722		bool dsc : 1;	   /* Display stream compression */723 724		uint32_t reserved : 19;725	} bits;726	uint32_t u32All;727};728 729enum pg_hw_pipe_resources {730	PG_HUBP = 0,731	PG_DPP,732	PG_DSC,733	PG_MPCC,734	PG_OPP,735	PG_OPTC,736	PG_DPSTREAM,737	PG_HDMISTREAM,738	PG_PHYSYMCLK,739	PG_HW_PIPE_RESOURCES_NUM_ELEMENT740};741 742enum pg_hw_resources {743	PG_DCCG = 0,744	PG_DCIO,745	PG_DIO,746	PG_DCHUBBUB,747	PG_DCHVM,748	PG_DWB,749	PG_HPO,750	PG_HW_RESOURCES_NUM_ELEMENT751};752 753struct pg_block_update {754	bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];755	bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT];756};757 758union dpia_debug_options {759	struct {760		uint32_t disable_dpia:1; /* bit 0 */761		uint32_t force_non_lttpr:1; /* bit 1 */762		uint32_t extend_aux_rd_interval:1; /* bit 2 */763		uint32_t disable_mst_dsc_work_around:1; /* bit 3 */764		uint32_t enable_force_tbt3_work_around:1; /* bit 4 */765		uint32_t disable_usb4_pm_support:1; /* bit 5 */766		uint32_t enable_consolidated_dpia_dp_lt:1; /* bit 6 */767		uint32_t reserved:25;768	} bits;769	uint32_t raw;770};771 772/* AUX wake work around options773 * 0: enable/disable work around774 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS775 * 15-2: reserved776 * 31-16: timeout in ms777 */778union aux_wake_wa_options {779	struct {780		uint32_t enable_wa : 1;781		uint32_t use_default_timeout : 1;782		uint32_t rsvd: 14;783		uint32_t timeout_ms : 16;784	} bits;785	uint32_t raw;786};787 788struct dc_debug_data {789	uint32_t ltFailCount;790	uint32_t i2cErrorCount;791	uint32_t auxErrorCount;792};793 794struct dc_phy_addr_space_config {795	struct {796		uint64_t start_addr;797		uint64_t end_addr;798		uint64_t fb_top;799		uint64_t fb_offset;800		uint64_t fb_base;801		uint64_t agp_top;802		uint64_t agp_bot;803		uint64_t agp_base;804	} system_aperture;805 806	struct {807		uint64_t page_table_start_addr;808		uint64_t page_table_end_addr;809		uint64_t page_table_base_addr;810		bool base_addr_is_mc_addr;811	} gart_config;812 813	bool valid;814	bool is_hvm_enabled;815	uint64_t page_table_default_page_addr;816};817 818struct dc_virtual_addr_space_config {819	uint64_t	page_table_base_addr;820	uint64_t	page_table_start_addr;821	uint64_t	page_table_end_addr;822	uint32_t	page_table_block_size_in_bytes;823	uint8_t		page_table_depth; // 1 = 1 level, 2 = 2 level, etc.  0 = invalid824};825 826struct dc_bounding_box_overrides {827	int sr_exit_time_ns;828	int sr_enter_plus_exit_time_ns;829	int sr_exit_z8_time_ns;830	int sr_enter_plus_exit_z8_time_ns;831	int urgent_latency_ns;832	int percent_of_ideal_drambw;833	int dram_clock_change_latency_ns;834	int dummy_clock_change_latency_ns;835	int fclk_clock_change_latency_ns;836	/* This forces a hard min on the DCFCLK we use837	 * for DML.  Unlike the debug option for forcing838	 * DCFCLK, this override affects watermark calculations839	 */840	int min_dcfclk_mhz;841};842 843struct dc_state;844struct resource_pool;845struct dce_hwseq;846struct link_service;847 848/*849 * struct dc_debug_options - DC debug struct850 *851 * This struct provides a simple mechanism for developers to change some852 * configurations, enable/disable features, and activate extra debug options.853 * This can be very handy to narrow down whether some specific feature is854 * causing an issue or not.855 */856struct dc_debug_options {857	bool native422_support;858	bool disable_dsc;859	enum visual_confirm visual_confirm;860	int visual_confirm_rect_height;861 862	bool sanity_checks;863	bool max_disp_clk;864	bool surface_trace;865	bool timing_trace;866	bool clock_trace;867	bool validation_trace;868	bool bandwidth_calcs_trace;869	int max_downscale_src_width;870 871	/* stutter efficiency related */872	bool disable_stutter;873	bool use_max_lb;874	enum dcc_option disable_dcc;875 876	/*877	 * @pipe_split_policy: Define which pipe split policy is used by the878	 * display core.879	 */880	enum pipe_split_policy pipe_split_policy;881	bool force_single_disp_pipe_split;882	bool voltage_align_fclk;883	bool disable_min_fclk;884 885	bool disable_dfs_bypass;886	bool disable_dpp_power_gate;887	bool disable_hubp_power_gate;888	bool disable_dsc_power_gate;889	bool disable_optc_power_gate;890	bool disable_hpo_power_gate;891	int dsc_min_slice_height_override;892	int dsc_bpp_increment_div;893	bool disable_pplib_wm_range;894	enum wm_report_mode pplib_wm_report_mode;895	unsigned int min_disp_clk_khz;896	unsigned int min_dpp_clk_khz;897	unsigned int min_dram_clk_khz;898	int sr_exit_time_dpm0_ns;899	int sr_enter_plus_exit_time_dpm0_ns;900	int sr_exit_time_ns;901	int sr_enter_plus_exit_time_ns;902	int sr_exit_z8_time_ns;903	int sr_enter_plus_exit_z8_time_ns;904	int urgent_latency_ns;905	uint32_t underflow_assert_delay_us;906	int percent_of_ideal_drambw;907	int dram_clock_change_latency_ns;908	bool optimized_watermark;909	int always_scale;910	bool disable_pplib_clock_request;911	bool disable_clock_gate;912	bool disable_mem_low_power;913	bool pstate_enabled;914	bool disable_dmcu;915	bool force_abm_enable;916	bool disable_stereo_support;917	bool vsr_support;918	bool performance_trace;919	bool az_endpoint_mute_only;920	bool always_use_regamma;921	bool recovery_enabled;922	bool avoid_vbios_exec_table;923	bool scl_reset_length10;924	bool hdmi20_disable;925	bool skip_detection_link_training;926	uint32_t edid_read_retry_times;927	unsigned int force_odm_combine; //bit vector based on otg inst928	unsigned int seamless_boot_odm_combine;929	unsigned int force_odm_combine_4to1; //bit vector based on otg inst930	int minimum_z8_residency_time;931	int minimum_z10_residency_time;932	bool disable_z9_mpc;933	unsigned int force_fclk_khz;934	bool enable_tri_buf;935	bool ips_disallow_entry;936	bool dmub_offload_enabled;937	bool dmcub_emulation;938	bool disable_idle_power_optimizations;939	unsigned int mall_size_override;940	unsigned int mall_additional_timer_percent;941	bool mall_error_as_fatal;942	bool dmub_command_table; /* for testing only */943	struct dc_bw_validation_profile bw_val_profile;944	bool disable_fec;945	bool disable_48mhz_pwrdwn;946	/* This forces a hard min on the DCFCLK requested to SMU/PP947	 * watermarks are not affected.948	 */949	unsigned int force_min_dcfclk_mhz;950	int dwb_fi_phase;951	bool disable_timing_sync;952	bool cm_in_bypass;953	int force_clock_mode;/*every mode change.*/954 955	bool disable_dram_clock_change_vactive_support;956	bool validate_dml_output;957	bool enable_dmcub_surface_flip;958	bool usbc_combo_phy_reset_wa;959	bool enable_dram_clock_change_one_display_vactive;960	/* TODO - remove once tested */961	bool legacy_dp2_lt;962	bool set_mst_en_for_sst;963	bool disable_uhbr;964	bool force_dp2_lt_fallback_method;965	bool ignore_cable_id;966	union mem_low_power_enable_options enable_mem_low_power;967	union root_clock_optimization_options root_clock_optimization;968	union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating;969	bool hpo_optimization;970	bool force_vblank_alignment;971 972	/* Enable dmub aux for legacy ddc */973	bool enable_dmub_aux_for_legacy_ddc;974	bool disable_fams;975	enum in_game_fams_config disable_fams_gaming;976	/* FEC/PSR1 sequence enable delay in 100us */977	uint8_t fec_enable_delay_in100us;978	bool enable_driver_sequence_debug;979	enum det_size crb_alloc_policy;980	int crb_alloc_policy_min_disp_count;981	bool disable_z10;982	bool enable_z9_disable_interface;983	bool psr_skip_crtc_disable;984	uint32_t ips_skip_crtc_disable_mask;985	union dpia_debug_options dpia_debug;986	bool disable_fixed_vs_aux_timeout_wa;987	uint32_t fixed_vs_aux_delay_config_wa;988	bool force_disable_subvp;989	bool force_subvp_mclk_switch;990	bool allow_sw_cursor_fallback;991	unsigned int force_subvp_num_ways;992	unsigned int force_mall_ss_num_ways;993	bool alloc_extra_way_for_cursor;994	uint32_t subvp_extra_lines;995	bool force_usr_allow;996	/* uses value at boot and disables switch */997	bool disable_dtb_ref_clk_switch;998	bool extended_blank_optimization;999	union aux_wake_wa_options aux_wake_wa;1000	uint32_t mst_start_top_delay;1001	uint8_t psr_power_use_phy_fsm;1002	enum dml_hostvm_override_opts dml_hostvm_override;1003	bool dml_disallow_alternate_prefetch_modes;1004	bool use_legacy_soc_bb_mechanism;1005	bool exit_idle_opt_for_cursor_updates;1006	bool using_dml2;1007	bool enable_single_display_2to1_odm_policy;1008	bool enable_double_buffered_dsc_pg_support;1009	bool enable_dp_dig_pixel_rate_div_policy;1010	bool using_dml21;1011	enum lttpr_mode lttpr_mode_override;1012	unsigned int dsc_delay_factor_wa_x1000;1013	unsigned int min_prefetch_in_strobe_ns;1014	bool disable_unbounded_requesting;1015	bool dig_fifo_off_in_blank;1016	bool override_dispclk_programming;1017	bool otg_crc_db;1018	bool disallow_dispclk_dppclk_ds;1019	bool disable_fpo_optimizations;1020	bool support_eDP1_5;1021	uint32_t fpo_vactive_margin_us;1022	bool disable_fpo_vactive;1023	bool disable_boot_optimizations;1024	bool override_odm_optimization;1025	bool minimize_dispclk_using_odm;1026	bool disable_subvp_high_refresh;1027	bool disable_dp_plus_plus_wa;1028	uint32_t fpo_vactive_min_active_margin_us;1029	uint32_t fpo_vactive_max_blank_us;1030	bool enable_hpo_pg_support;1031	bool enable_legacy_fast_update;1032	bool disable_dc_mode_overwrite;1033	bool replay_skip_crtc_disabled;1034	bool ignore_pg;/*do nothing, let pmfw control it*/1035	bool psp_disabled_wa;1036	unsigned int ips2_eval_delay_us;1037	unsigned int ips2_entry_delay_us;1038	bool optimize_ips_handshake;1039	bool disable_dmub_reallow_idle;1040	bool disable_timeout;1041	bool disable_extblankadj;1042	bool enable_idle_reg_checks;1043	unsigned int static_screen_wait_frames;1044	uint32_t pwm_freq;1045	bool force_chroma_subsampling_1tap;1046	unsigned int dcc_meta_propagation_delay_us;1047	bool disable_422_left_edge_pixel;1048	bool dml21_force_pstate_method;1049	uint32_t dml21_force_pstate_method_values[MAX_PIPES];1050	uint32_t dml21_disable_pstate_method_mask;1051	union dmub_fams2_global_feature_config fams2_config;1052	bool enable_legacy_clock_update;1053	unsigned int force_cositing;1054	unsigned int disable_spl;1055	unsigned int force_easf;1056	unsigned int force_sharpness;1057	unsigned int force_sharpness_level;1058	unsigned int force_lls;1059	bool notify_dpia_hr_bw;1060	bool enable_ips_visual_confirm;1061	unsigned int sharpen_policy;1062	unsigned int scale_to_sharpness_policy;1063	bool skip_full_updated_if_possible;1064};1065 1066 1067/* Generic structure that can be used to query properties of DC. More fields1068 * can be added as required.1069 */1070struct dc_current_properties {1071	unsigned int cursor_size_limit;1072};1073 1074enum frame_buffer_mode {1075	FRAME_BUFFER_MODE_LOCAL_ONLY = 0,1076	FRAME_BUFFER_MODE_ZFB_ONLY,1077	FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,1078} ;1079 1080struct dchub_init_data {1081	int64_t zfb_phys_addr_base;1082	int64_t zfb_mc_base_addr;1083	uint64_t zfb_size_in_byte;1084	enum frame_buffer_mode fb_mode;1085	bool dchub_initialzied;1086	bool dchub_info_valid;1087};1088 1089struct dml2_soc_bb;1090 1091struct dc_init_data {1092	struct hw_asic_id asic_id;1093	void *driver; /* ctx */1094	struct cgs_device *cgs_device;1095	struct dc_bounding_box_overrides bb_overrides;1096 1097	int num_virtual_links;1098	/*1099	 * If 'vbios_override' not NULL, it will be called instead1100	 * of the real VBIOS. Intended use is Diagnostics on FPGA.1101	 */1102	struct dc_bios *vbios_override;1103	enum dce_environment dce_environment;1104 1105	struct dmub_offload_funcs *dmub_if;1106	struct dc_reg_helper_state *dmub_offload;1107 1108	struct dc_config flags;1109	uint64_t log_mask;1110 1111	struct dpcd_vendor_signature vendor_signature;1112	bool force_smu_not_present;1113	/*1114	 * IP offset for run time initializaion of register addresses1115	 *1116	 * DCN3.5+ will fail dc_create() if these fields are null for them. They are1117	 * applicable starting with DCN32/321 and are not used for ASICs upstreamed1118	 * before them.1119	 */1120	uint32_t *dcn_reg_offsets;1121	uint32_t *nbio_reg_offsets;1122	uint32_t *clk_reg_offsets;1123	struct dml2_soc_bb *bb_from_dmub;1124};1125 1126struct dc_callback_init {1127	struct cp_psp cp_psp;1128};1129 1130struct dc *dc_create(const struct dc_init_data *init_params);1131void dc_hardware_init(struct dc *dc);1132 1133int dc_get_vmid_use_vector(struct dc *dc);1134void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);1135/* Returns the number of vmids supported */1136int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);1137void dc_init_callbacks(struct dc *dc,1138		const struct dc_callback_init *init_params);1139void dc_deinit_callbacks(struct dc *dc);1140void dc_destroy(struct dc **dc);1141 1142/* Surface Interfaces */1143 1144enum {1145	TRANSFER_FUNC_POINTS = 10251146};1147 1148struct dc_hdr_static_metadata {1149	/* display chromaticities and white point in units of 0.00001 */1150	unsigned int chromaticity_green_x;1151	unsigned int chromaticity_green_y;1152	unsigned int chromaticity_blue_x;1153	unsigned int chromaticity_blue_y;1154	unsigned int chromaticity_red_x;1155	unsigned int chromaticity_red_y;1156	unsigned int chromaticity_white_point_x;1157	unsigned int chromaticity_white_point_y;1158 1159	uint32_t min_luminance;1160	uint32_t max_luminance;1161	uint32_t maximum_content_light_level;1162	uint32_t maximum_frame_average_light_level;1163};1164 1165enum dc_transfer_func_type {1166	TF_TYPE_PREDEFINED,1167	TF_TYPE_DISTRIBUTED_POINTS,1168	TF_TYPE_BYPASS,1169	TF_TYPE_HWPWL1170};1171 1172struct dc_transfer_func_distributed_points {1173	struct fixed31_32 red[TRANSFER_FUNC_POINTS];1174	struct fixed31_32 green[TRANSFER_FUNC_POINTS];1175	struct fixed31_32 blue[TRANSFER_FUNC_POINTS];1176 1177	uint16_t end_exponent;1178	uint16_t x_point_at_y1_red;1179	uint16_t x_point_at_y1_green;1180	uint16_t x_point_at_y1_blue;1181};1182 1183enum dc_transfer_func_predefined {1184	TRANSFER_FUNCTION_SRGB,1185	TRANSFER_FUNCTION_BT709,1186	TRANSFER_FUNCTION_PQ,1187	TRANSFER_FUNCTION_LINEAR,1188	TRANSFER_FUNCTION_UNITY,1189	TRANSFER_FUNCTION_HLG,1190	TRANSFER_FUNCTION_HLG12,1191	TRANSFER_FUNCTION_GAMMA22,1192	TRANSFER_FUNCTION_GAMMA24,1193	TRANSFER_FUNCTION_GAMMA261194};1195 1196 1197struct dc_transfer_func {1198	struct kref refcount;1199	enum dc_transfer_func_type type;1200	enum dc_transfer_func_predefined tf;1201	/* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/1202	uint32_t sdr_ref_white_level;1203	union {1204		struct pwl_params pwl;1205		struct dc_transfer_func_distributed_points tf_pts;1206	};1207};1208 1209 1210union dc_3dlut_state {1211	struct {1212		uint32_t initialized:1;		/*if 3dlut is went through color module for initialization */1213		uint32_t rmu_idx_valid:1;	/*if mux settings are valid*/1214		uint32_t rmu_mux_num:3;		/*index of mux to use*/1215		uint32_t mpc_rmu0_mux:4;	/*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/1216		uint32_t mpc_rmu1_mux:4;1217		uint32_t mpc_rmu2_mux:4;1218		uint32_t reserved:15;1219	} bits;1220	uint32_t raw;1221};1222 1223 1224struct dc_3dlut {1225	struct kref refcount;1226	struct tetrahedral_params lut_3d;1227	struct fixed31_32 hdr_multiplier;1228	union dc_3dlut_state state;1229};1230/*1231 * This structure is filled in by dc_surface_get_status and contains1232 * the last requested address and the currently active address so the called1233 * can determine if there are any outstanding flips1234 */1235struct dc_plane_status {1236	struct dc_plane_address requested_address;1237	struct dc_plane_address current_address;1238	bool is_flip_pending;1239	bool is_right_eye;1240};1241 1242union surface_update_flags {1243 1244	struct {1245		uint32_t addr_update:1;1246		/* Medium updates */1247		uint32_t dcc_change:1;1248		uint32_t color_space_change:1;1249		uint32_t horizontal_mirror_change:1;1250		uint32_t per_pixel_alpha_change:1;1251		uint32_t global_alpha_change:1;1252		uint32_t hdr_mult:1;1253		uint32_t rotation_change:1;1254		uint32_t swizzle_change:1;1255		uint32_t scaling_change:1;1256		uint32_t clip_size_change: 1;1257		uint32_t position_change:1;1258		uint32_t in_transfer_func_change:1;1259		uint32_t input_csc_change:1;1260		uint32_t coeff_reduction_change:1;1261		uint32_t output_tf_change:1;1262		uint32_t pixel_format_change:1;1263		uint32_t plane_size_change:1;1264		uint32_t gamut_remap_change:1;1265 1266		/* Full updates */1267		uint32_t new_plane:1;1268		uint32_t bpp_change:1;1269		uint32_t gamma_change:1;1270		uint32_t bandwidth_change:1;1271		uint32_t clock_change:1;1272		uint32_t stereo_format_change:1;1273		uint32_t lut_3d:1;1274		uint32_t tmz_changed:1;1275		uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */1276		uint32_t full_update:1;1277		uint32_t sdr_white_level_nits:1;1278	} bits;1279 1280	uint32_t raw;1281};1282 1283#define DC_REMOVE_PLANE_POINTERS 11284 1285struct dc_plane_state {1286	struct dc_plane_address address;1287	struct dc_plane_flip_time time;1288	bool triplebuffer_flips;1289	struct scaling_taps scaling_quality;1290	struct rect src_rect;1291	struct rect dst_rect;1292	struct rect clip_rect;1293 1294	struct plane_size plane_size;1295	union dc_tiling_info tiling_info;1296 1297	struct dc_plane_dcc_param dcc;1298 1299	struct dc_gamma gamma_correction;1300	struct dc_transfer_func in_transfer_func;1301	struct dc_bias_and_scale bias_and_scale;1302	struct dc_csc_transform input_csc_color_matrix;1303	struct fixed31_32 coeff_reduction_factor;1304	struct fixed31_32 hdr_mult;1305	struct colorspace_transform gamut_remap_matrix;1306 1307	// TODO: No longer used, remove1308	struct dc_hdr_static_metadata hdr_static_ctx;1309 1310	enum dc_color_space color_space;1311 1312	struct dc_3dlut lut3d_func;1313	struct dc_transfer_func in_shaper_func;1314	struct dc_transfer_func blend_tf;1315 1316	struct dc_transfer_func *gamcor_tf;1317	enum surface_pixel_format format;1318	enum dc_rotation_angle rotation;1319	enum plane_stereo_format stereo_format;1320 1321	bool is_tiling_rotated;1322	bool per_pixel_alpha;1323	bool pre_multiplied_alpha;1324	bool global_alpha;1325	int  global_alpha_value;1326	bool visible;1327	bool flip_immediate;1328	bool horizontal_mirror;1329	int layer_index;1330 1331	union surface_update_flags update_flags;1332	bool flip_int_enabled;1333	bool skip_manual_trigger;1334 1335	/* private to DC core */1336	struct dc_plane_status status;1337	struct dc_context *ctx;1338 1339	/* HACK: Workaround for forcing full reprogramming under some conditions */1340	bool force_full_update;1341 1342	bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead1343 1344	/* private to dc_surface.c */1345	enum dc_irq_source irq_source;1346	struct kref refcount;1347	struct tg_color visual_confirm_color;1348 1349	bool is_statically_allocated;1350	enum chroma_cositing cositing;1351	enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting;1352	bool mcm_lut1d_enable;1353	struct dc_cm2_func_luts mcm_luts;1354	bool lut_bank_a;1355	enum mpcc_movable_cm_location mcm_location;1356	struct dc_csc_transform cursor_csc_color_matrix;1357	bool adaptive_sharpness_en;1358	int sharpness_level;1359	enum linear_light_scaling linear_light_scaling;1360	unsigned int sdr_white_level_nits;1361};1362 1363struct dc_plane_info {1364	struct plane_size plane_size;1365	union dc_tiling_info tiling_info;1366	struct dc_plane_dcc_param dcc;1367	enum surface_pixel_format format;1368	enum dc_rotation_angle rotation;1369	enum plane_stereo_format stereo_format;1370	enum dc_color_space color_space;1371	bool horizontal_mirror;1372	bool visible;1373	bool per_pixel_alpha;1374	bool pre_multiplied_alpha;1375	bool global_alpha;1376	int  global_alpha_value;1377	bool input_csc_enabled;1378	int layer_index;1379	enum chroma_cositing cositing;1380};1381 1382#include "dc_stream.h"1383 1384struct dc_scratch_space {1385	/* used to temporarily backup plane states of a stream during1386	 * dc update. The reason is that plane states are overwritten1387	 * with surface updates in dc update. Once they are overwritten1388	 * current state is no longer valid. We want to temporarily1389	 * store current value in plane states so we can still recover1390	 * a valid current state during dc update.1391	 */1392	struct dc_plane_state plane_states[MAX_SURFACE_NUM];1393 1394	struct dc_stream_state stream_state;1395};1396 1397struct dc {1398	struct dc_debug_options debug;1399	struct dc_versions versions;1400	struct dc_caps caps;1401	struct dc_cap_funcs cap_funcs;1402	struct dc_config config;1403	struct dc_bounding_box_overrides bb_overrides;1404	struct dc_bug_wa work_arounds;1405	struct dc_context *ctx;1406	struct dc_phy_addr_space_config vm_pa_config;1407 1408	uint8_t link_count;1409	struct dc_link *links[MAX_LINKS];1410	struct link_service *link_srv;1411 1412	struct dc_state *current_state;1413	struct resource_pool *res_pool;1414 1415	struct clk_mgr *clk_mgr;1416 1417	/* Display Engine Clock levels */1418	struct dm_pp_clock_levels sclk_lvls;1419 1420	/* Inputs into BW and WM calculations. */1421	struct bw_calcs_dceip *bw_dceip;1422	struct bw_calcs_vbios *bw_vbios;1423	struct dcn_soc_bounding_box *dcn_soc;1424	struct dcn_ip_params *dcn_ip;1425	struct display_mode_lib dml;1426 1427	/* HW functions */1428	struct hw_sequencer_funcs hwss;1429	struct dce_hwseq *hwseq;1430 1431	/* Require to optimize clocks and bandwidth for added/removed planes */1432	bool optimized_required;1433	bool wm_optimized_required;1434	bool idle_optimizations_allowed;1435	bool enable_c20_dtm_b0;1436 1437	/* Require to maintain clocks and bandwidth for UEFI enabled HW */1438 1439	/* FBC compressor */1440	struct compressor *fbc_compressor;1441 1442	struct dc_debug_data debug_data;1443	struct dpcd_vendor_signature vendor_signature;1444 1445	const char *build_id;1446	struct vm_helper *vm_helper;1447 1448	uint32_t *dcn_reg_offsets;1449	uint32_t *nbio_reg_offsets;1450	uint32_t *clk_reg_offsets;1451 1452	/* Scratch memory */1453	struct {1454		struct {1455			/*1456			 * For matching clock_limits table in driver with table1457			 * from PMFW.1458			 */1459			struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];1460		} update_bw_bounding_box;1461		struct dc_scratch_space current_state;1462		struct dc_scratch_space new_state;1463		struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack1464	} scratch;1465 1466	struct dml2_configuration_options dml2_options;1467	struct dml2_configuration_options dml2_tmp;1468	enum dc_acpi_cm_power_state power_state;1469 1470};1471 1472struct dc_scaling_info {1473	struct rect src_rect;1474	struct rect dst_rect;1475	struct rect clip_rect;1476	struct scaling_taps scaling_quality;1477};1478 1479struct dc_fast_update {1480	const struct dc_flip_addrs *flip_addr;1481	const struct dc_gamma *gamma;1482	const struct colorspace_transform *gamut_remap_matrix;1483	const struct dc_csc_transform *input_csc_color_matrix;1484	const struct fixed31_32 *coeff_reduction_factor;1485	struct dc_transfer_func *out_transfer_func;1486	struct dc_csc_transform *output_csc_transform;1487	const struct dc_csc_transform *cursor_csc_color_matrix;1488};1489 1490struct dc_surface_update {1491	struct dc_plane_state *surface;1492 1493	/* isr safe update parameters.  null means no updates */1494	const struct dc_flip_addrs *flip_addr;1495	const struct dc_plane_info *plane_info;1496	const struct dc_scaling_info *scaling_info;1497	struct fixed31_32 hdr_mult;1498	/* following updates require alloc/sleep/spin that is not isr safe,1499	 * null means no updates1500	 */1501	const struct dc_gamma *gamma;1502	const struct dc_transfer_func *in_transfer_func;1503 1504	const struct dc_csc_transform *input_csc_color_matrix;1505	const struct fixed31_32 *coeff_reduction_factor;1506	const struct dc_transfer_func *func_shaper;1507	const struct dc_3dlut *lut3d_func;1508	const struct dc_transfer_func *blend_tf;1509	const struct colorspace_transform *gamut_remap_matrix;1510	/*1511	 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT)1512	 *1513	 * change cm2_params.component_settings: Full update1514	 * change cm2_params.cm2_luts: Fast update1515	 */1516	struct dc_cm2_parameters *cm2_params;1517	const struct dc_csc_transform *cursor_csc_color_matrix;1518	unsigned int sdr_white_level_nits;1519};1520 1521/*1522 * Create a new surface with default parameters;1523 */1524void dc_gamma_retain(struct dc_gamma *dc_gamma);1525void dc_gamma_release(struct dc_gamma **dc_gamma);1526struct dc_gamma *dc_create_gamma(void);1527 1528void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);1529void dc_transfer_func_release(struct dc_transfer_func *dc_tf);1530struct dc_transfer_func *dc_create_transfer_func(void);1531 1532struct dc_3dlut *dc_create_3dlut_func(void);1533void dc_3dlut_func_release(struct dc_3dlut *lut);1534void dc_3dlut_func_retain(struct dc_3dlut *lut);1535 1536void dc_post_update_surfaces_to_stream(1537		struct dc *dc);1538 1539#include "dc_stream.h"1540 1541/**1542 * struct dc_validation_set - Struct to store surface/stream associations for validation1543 */1544struct dc_validation_set {1545	/**1546	 * @stream: Stream state properties1547	 */1548	struct dc_stream_state *stream;1549 1550	/**1551	 * @plane_states: Surface state1552	 */1553	struct dc_plane_state *plane_states[MAX_SURFACES];1554 1555	/**1556	 * @plane_count: Total of active planes1557	 */1558	uint8_t plane_count;1559};1560 1561bool dc_validate_boot_timing(const struct dc *dc,1562				const struct dc_sink *sink,1563				struct dc_crtc_timing *crtc_timing);1564 1565enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);1566 1567void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);1568 1569enum dc_status dc_validate_with_context(struct dc *dc,1570					const struct dc_validation_set set[],1571					int set_count,1572					struct dc_state *context,1573					bool fast_validate);1574 1575bool dc_set_generic_gpio_for_stereo(bool enable,1576		struct gpio_service *gpio_service);1577 1578/*1579 * fast_validate: we return after determining if we can support the new state,1580 * but before we populate the programming info1581 */1582enum dc_status dc_validate_global_state(1583		struct dc *dc,1584		struct dc_state *new_ctx,1585		bool fast_validate);1586 1587bool dc_acquire_release_mpc_3dlut(1588		struct dc *dc, bool acquire,1589		struct dc_stream_state *stream,1590		struct dc_3dlut **lut,1591		struct dc_transfer_func **shaper);1592 1593bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);1594void get_audio_check(struct audio_info *aud_modes,1595	struct audio_check *aud_chk);1596 1597bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count);1598void populate_fast_updates(struct dc_fast_update *fast_update,1599		struct dc_surface_update *srf_updates,1600		int surface_count,1601		struct dc_stream_update *stream_update);1602/*1603 * Set up streams and links associated to drive sinks1604 * The streams parameter is an absolute set of all active streams.1605 *1606 * After this call:1607 *   Phy, Encoder, Timing Generator are programmed and enabled.1608 *   New streams are enabled with blank stream; no memory read.1609 */1610enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);1611 1612 1613struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,1614		struct dc_stream_state *stream,1615		int mpcc_inst);1616 1617 1618uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);1619 1620void dc_set_disable_128b_132b_stream_overhead(bool disable);1621 1622/* The function returns minimum bandwidth required to drive a given timing1623 * return - minimum required timing bandwidth in kbps.1624 */1625uint32_t dc_bandwidth_in_kbps_from_timing(1626		const struct dc_crtc_timing *timing,1627		const enum dc_link_encoding_format link_encoding);1628 1629/* Link Interfaces */1630/*1631 * A link contains one or more sinks and their connected status.1632 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.1633 */1634struct dc_link {1635	struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];1636	unsigned int sink_count;1637	struct dc_sink *local_sink;1638	unsigned int link_index;1639	enum dc_connection_type type;1640	enum signal_type connector_signal;1641	enum dc_irq_source irq_source_hpd;1642	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */1643 1644	bool is_hpd_filter_disabled;1645	bool dp_ss_off;1646 1647	/**1648	 * @link_state_valid:1649	 *1650	 * If there is no link and local sink, this variable should be set to1651	 * false. Otherwise, it should be set to true; usually, the function1652	 * core_link_enable_stream sets this field to true.1653	 */1654	bool link_state_valid;1655	bool aux_access_disabled;1656	bool sync_lt_in_progress;1657	bool skip_stream_reenable;1658	bool is_internal_display;1659	/** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */1660	bool is_dig_mapping_flexible;1661	bool hpd_status; /* HPD status of link without physical HPD pin. */1662	bool is_hpd_pending; /* Indicates a new received hpd */1663 1664	/* USB4 DPIA links skip verifying link cap, instead performing the fallback method1665	 * for every link training. This is incompatible with DP LL compliance automation,1666	 * which expects the same link settings to be used every retry on a link loss.1667	 * This flag is used to skip the fallback when link loss occurs during automation.1668	 */1669	bool skip_fallback_on_link_loss;1670 1671	bool edp_sink_present;1672 1673	struct dp_trace dp_trace;1674 1675	/* caps is the same as reported_link_cap. link_traing use1676	 * reported_link_cap. Will clean up.  TODO1677	 */1678	struct dc_link_settings reported_link_cap;1679	struct dc_link_settings verified_link_cap;1680	struct dc_link_settings cur_link_settings;1681	struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];1682	struct dc_link_settings preferred_link_setting;1683	/* preferred_training_settings are override values that1684	 * come from DM. DM is responsible for the memory1685	 * management of the override pointers.1686	 */1687	struct dc_link_training_overrides preferred_training_settings;1688	struct dp_audio_test_data audio_test_data;1689 1690	uint8_t ddc_hw_inst;1691 1692	uint8_t hpd_src;1693 1694	uint8_t link_enc_hw_inst;1695	/* DIG link encoder ID. Used as index in link encoder resource pool.1696	 * For links with fixed mapping to DIG, this is not changed after dc_link1697	 * object creation.1698	 */1699	enum engine_id eng_id;1700	enum engine_id dpia_preferred_eng_id;1701 1702	bool test_pattern_enabled;1703	/* Pending/Current test pattern are only used to perform and track1704	 * FIXED_VS retimer test pattern/lane adjustment override state.1705	 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern,1706	 * to perform specific lane adjust overrides before setting certain1707	 * PHY test patterns. In cases when lane adjust and set test pattern1708	 * calls are not performed atomically (i.e. performing link training),1709	 * pending_test_pattern will be invalid or contain a non-PHY test pattern1710	 * and current_test_pattern will contain required context for any future1711	 * set pattern/set lane adjust to transition between override state(s).1712	 * */1713	enum dp_test_pattern current_test_pattern;1714	enum dp_test_pattern pending_test_pattern;1715 1716	union compliance_test_state compliance_test_state;1717 1718	void *priv;1719 1720	struct ddc_service *ddc;1721 1722	enum dp_panel_mode panel_mode;1723	bool aux_mode;1724 1725	/* Private to DC core */1726 1727	const struct dc *dc;1728 1729	struct dc_context *ctx;1730 1731	struct panel_cntl *panel_cntl;1732	struct link_encoder *link_enc;1733	struct graphics_object_id link_id;1734	/* Endpoint type distinguishes display endpoints which do not have entries1735	 * in the BIOS connector table from those that do. Helps when tracking link1736	 * encoder to display endpoint assignments.1737	 */1738	enum display_endpoint_type ep_type;1739	union ddi_channel_mapping ddi_channel_mapping;1740	struct connector_device_tag_info device_tag;1741	struct dpcd_caps dpcd_caps;1742	uint32_t dongle_max_pix_clk;1743	unsigned short chip_caps;1744	unsigned int dpcd_sink_count;1745	struct hdcp_caps hdcp_caps;1746	enum edp_revision edp_revision;1747	union dpcd_sink_ext_caps dpcd_sink_ext_caps;1748 1749	struct psr_settings psr_settings;1750	struct replay_settings replay_settings;1751 1752	/* Drive settings read from integrated info table */1753	struct dc_lane_settings bios_forced_drive_settings;1754 1755	/* Vendor specific LTTPR workaround variables */1756	uint8_t vendor_specific_lttpr_link_rate_wa;1757	bool apply_vendor_specific_lttpr_link_rate_wa;1758 1759	/* MST record stream using this link */1760	struct link_flags {1761		bool dp_keep_receiver_powered;1762		bool dp_skip_DID2;1763		bool dp_skip_reset_segment;1764		bool dp_skip_fs_144hz;1765		bool dp_mot_reset_segment;1766		/* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */1767		bool dpia_mst_dsc_always_on;1768		/* Forced DPIA into TBT3 compatibility mode. */1769		bool dpia_forced_tbt3_mode;1770		bool dongle_mode_timing_override;1771		bool blank_stream_on_ocs_change;1772		bool read_dpcd204h_on_irq_hpd;1773		bool disable_assr_for_uhbr;1774	} wa_flags;1775	struct link_mst_stream_allocation_table mst_stream_alloc_table;1776 1777	struct dc_link_status link_status;1778	struct dprx_states dprx_states;1779 1780	struct gpio *hpd_gpio;1781	enum dc_link_fec_state fec_state;1782	bool link_powered_externally;	// Used to bypass hardware sequencing delays when panel is powered down forcibly1783 1784	struct dc_panel_config panel_config;1785	struct phy_state phy_state;1786	// BW ALLOCATON USB4 ONLY1787	struct dc_dpia_bw_alloc dpia_bw_alloc_config;1788	bool skip_implict_edp_power_control;1789};1790 1791/* Return an enumerated dc_link.1792 * dc_link order is constant and determined at1793 * boot time.  They cannot be created or destroyed.1794 * Use dc_get_caps() to get number of links.1795 */1796struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);1797 1798/* Return instance id of the edp link. Inst 0 is primary edp link. */1799bool dc_get_edp_link_panel_inst(const struct dc *dc,1800		const struct dc_link *link,1801		unsigned int *inst_out);1802 1803/* Return an array of link pointers to edp links. */1804void dc_get_edp_links(const struct dc *dc,1805		struct dc_link **edp_links,1806		int *edp_num);1807 1808void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,1809				 bool powerOn);1810 1811/* The function initiates detection handshake over the given link. It first1812 * determines if there are display connections over the link. If so it initiates1813 * detection protocols supported by the connected receiver device. The function1814 * contains protocol specific handshake sequences which are sometimes mandatory1815 * to establish a proper connection between TX and RX. So it is always1816 * recommended to call this function as the first link operation upon HPD event1817 * or power up event. Upon completion, the function will update link structure1818 * in place based on latest RX capabilities. The function may also cause dpms1819 * to be reset to off for all currently enabled streams to the link. It is DM's1820 * responsibility to serialize detection and DPMS updates.1821 *1822 * @reason - Indicate which event triggers this detection. dc may customize1823 * detection flow depending on the triggering events.1824 * return false - if detection is not fully completed. This could happen when1825 * there is an unrecoverable error during detection or detection is partially1826 * completed (detection has been delegated to dm mst manager ie.1827 * link->connection_type == dc_connection_mst_branch when returning false).1828 * return true - detection is completed, link has been fully updated with latest1829 * detection result.1830 */1831bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);1832 1833struct dc_sink_init_data;1834 1835/* When link connection type is dc_connection_mst_branch, remote sink can be1836 * added to the link. The interface creates a remote sink and associates it with1837 * current link. The sink will be retained by link until remove remote sink is1838 * called.1839 *1840 * @dc_link - link the remote sink will be added to.1841 * @edid - byte array of EDID raw data.1842 * @len - size of the edid in byte1843 * @init_data -1844 */1845struct dc_sink *dc_link_add_remote_sink(1846		struct dc_link *dc_link,1847		const uint8_t *edid,1848		int len,1849		struct dc_sink_init_data *init_data);1850 1851/* Remove remote sink from a link with dc_connection_mst_branch connection type.1852 * @link - link the sink should be removed from1853 * @sink - sink to be removed.1854 */1855void dc_link_remove_remote_sink(1856	struct dc_link *link,1857	struct dc_sink *sink);1858 1859/* Enable HPD interrupt handler for a given link */1860void dc_link_enable_hpd(const struct dc_link *link);1861 1862/* Disable HPD interrupt handler for a given link */1863void dc_link_disable_hpd(const struct dc_link *link);1864 1865/* determine if there is a sink connected to the link1866 *1867 * @type - dc_connection_single if connected, dc_connection_none otherwise.1868 * return - false if an unexpected error occurs, true otherwise.1869 *1870 * NOTE: This function doesn't detect downstream sink connections i.e1871 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will1872 * return dc_connection_single if the branch device is connected despite of1873 * downstream sink's connection status.1874 */1875bool dc_link_detect_connection_type(struct dc_link *link,1876		enum dc_connection_type *type);1877 1878/* query current hpd pin value1879 * return - true HPD is asserted (HPD high), false otherwise (HPD low)1880 *1881 */1882bool dc_link_get_hpd_state(struct dc_link *link);1883 1884/* Getter for cached link status from given link */1885const struct dc_link_status *dc_link_get_status(const struct dc_link *link);1886 1887/* enable/disable hardware HPD filter.1888 *1889 * @link - The link the HPD pin is associated with.1890 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq1891 * handler once after no HPD change has been detected within dc default HPD1892 * filtering interval since last HPD event. i.e if display keeps toggling hpd1893 * pulses within default HPD interval, no HPD event will be received until HPD1894 * toggles have stopped. Then HPD event will be queued to irq handler once after1895 * dc default HPD filtering interval since last HPD event.1896 *1897 * @enable = false - disable hardware HPD filter. HPD event will be queued1898 * immediately to irq handler after no HPD change has been detected within1899 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms).1900 */1901void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);1902 1903/* submit i2c read/write payloads through ddc channel1904 * @link_index - index to a link with ddc in i2c mode1905 * @cmd - i2c command structure1906 * return - true if success, false otherwise.1907 */1908bool dc_submit_i2c(1909		struct dc *dc,1910		uint32_t link_index,1911		struct i2c_command *cmd);1912 1913/* submit i2c read/write payloads through oem channel1914 * @link_index - index to a link with ddc in i2c mode1915 * @cmd - i2c command structure1916 * return - true if success, false otherwise.1917 */1918bool dc_submit_i2c_oem(1919		struct dc *dc,1920		struct i2c_command *cmd);1921 1922enum aux_return_code_type;1923/* Attempt to transfer the given aux payload. This function does not perform1924 * retries or handle error states. The reply is returned in the payload->reply1925 * and the result through operation_result. Returns the number of bytes1926 * transferred,or -1 on a failure.1927 */1928int dc_link_aux_transfer_raw(struct ddc_service *ddc,1929		struct aux_payload *payload,1930		enum aux_return_code_type *operation_result);1931 1932bool dc_is_oem_i2c_device_present(1933	struct dc *dc,1934	size_t slave_address1935);1936 1937/* return true if the connected receiver supports the hdcp version */1938bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);1939bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);1940 1941/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).1942 *1943 * TODO - When defer_handling is true the function will have a different purpose.1944 * It no longer does complete hpd rx irq handling. We should create a separate1945 * interface specifically for this case.1946 *1947 * Return:1948 * true - Downstream port status changed. DM should call DC to do the1949 * detection.1950 * false - no change in Downstream port status. No further action required1951 * from DM.1952 */1953bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,1954		union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,1955		bool defer_handling, bool *has_left_work);1956/* handle DP specs define test automation sequence*/1957void dc_link_dp_handle_automated_test(struct dc_link *link);1958 1959/* handle DP Link loss sequence and try to recover RX link loss with best1960 * effort1961 */1962void dc_link_dp_handle_link_loss(struct dc_link *link);1963 1964/* Determine if hpd rx irq should be handled or ignored1965 * return true - hpd rx irq should be handled.1966 * return false - it is safe to ignore hpd rx irq event1967 */1968bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);1969 1970/* Determine if link loss is indicated with a given hpd_irq_dpcd_data.1971 * @link - link the hpd irq data associated with1972 * @hpd_irq_dpcd_data - input hpd irq data1973 * return - true if hpd irq data indicates a link lost1974 */1975bool dc_link_check_link_loss_status(struct dc_link *link,1976		union hpd_irq_data *hpd_irq_dpcd_data);1977 1978/* Read hpd rx irq data from a given link1979 * @link - link where the hpd irq data should be read from1980 * @irq_data - output hpd irq data1981 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data1982 * read has failed.1983 */1984enum dc_status dc_link_dp_read_hpd_rx_irq_data(1985	struct dc_link *link,1986	union hpd_irq_data *irq_data);1987 1988/* The function clears recorded DP RX states in the link. DM should call this1989 * function when it is resuming from S3 power state to previously connected links.1990 *1991 * TODO - in the future we should consider to expand link resume interface to1992 * support clearing previous rx states. So we don't have to rely on dm to call1993 * this interface explicitly.1994 */1995void dc_link_clear_dprx_states(struct dc_link *link);1996 1997/* Destruct the mst topology of the link and reset the allocated payload table1998 *1999 * NOTE: this should only be called if DM chooses not to call dc_link_detect but2000 * still wants to reset MST topology on an unplug event */2001bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);2002 2003/* The function calculates effective DP link bandwidth when a given link is2004 * using the given link settings.2005 *2006 * return - total effective link bandwidth in kbps.2007 */2008uint32_t dc_link_bandwidth_kbps(2009	const struct dc_link *link,2010	const struct dc_link_settings *link_setting);2011 2012/* The function takes a snapshot of current link resource allocation state2013 * @dc: pointer to dc of the dm calling this2014 * @map: a dc link resource snapshot defined internally to dc.2015 *2016 * DM needs to capture a snapshot of current link resource allocation mapping2017 * and store it in its persistent storage.2018 *2019 * Some of the link resource is using first come first serve policy.2020 * The allocation mapping depends on original hotplug order. This information2021 * is lost after driver is loaded next time. The snapshot is used in order to2022 * restore link resource to its previous state so user will get consistent2023 * link capability allocation across reboot.2024 *2025 */2026void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);2027 2028/* This function restores link resource allocation state from a snapshot2029 * @dc: pointer to dc of the dm calling this2030 * @map: a dc link resource snapshot defined internally to dc.2031 *2032 * DM needs to call this function after initial link detection on boot and2033 * before first commit streams to restore link resource allocation state2034 * from previous boot session.2035 *2036 * Some of the link resource is using first come first serve policy.2037 * The allocation mapping depends on original hotplug order. This information2038 * is lost after driver is loaded next time. The snapshot is used in order to2039 * restore link resource to its previous state so user will get consistent2040 * link capability allocation across reboot.2041 *2042 */2043void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);2044 2045/* TODO: this is not meant to be exposed to DM. Should switch to stream update2046 * interface i.e stream_update->dsc_config2047 */2048bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);2049 2050/* translate a raw link rate data to bandwidth in kbps */2051uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);2052 2053/* determine the optimal bandwidth given link and required bw.2054 * @link - current detected link2055 * @req_bw - requested bandwidth in kbps2056 * @link_settings - returned most optimal link settings that can fit the2057 * requested bandwidth2058 * return - false if link can't support requested bandwidth, true if link2059 * settings is found.2060 */2061bool dc_link_decide_edp_link_settings(struct dc_link *link,2062		struct dc_link_settings *link_settings,2063		uint32_t req_bw);2064 2065/* return the max dp link settings can be driven by the link without considering2066 * connected RX device and its capability2067 */2068bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,2069		struct dc_link_settings *max_link_enc_cap);2070 2071/* determine when the link is driving MST mode, what DP link channel coding2072 * format will be used. The decision will remain unchanged until next HPD event.2073 *2074 * @link -  a link with DP RX connection2075 * return - if stream is committed to this link with MST signal type, type of2076 * channel coding format dc will choose.2077 */2078enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(2079		const struct dc_link *link);2080 2081/* get max dp link settings the link can enable with all things considered. (i.e2082 * TX/RX/Cable capabilities and dp override policies.2083 *2084 * @link - a link with DP RX connection2085 * return - max dp link settings the link can enable.2086 *2087 */2088const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link);2089 2090/* Get the highest encoding format that the link supports; highest meaning the2091 * encoding format which supports the maximum bandwidth.2092 *2093 * @link - a link with DP RX connection2094 * return - highest encoding format link supports.2095 */2096enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link);2097 2098/* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected2099 * to a link with dp connector signal type.2100 * @link - a link with dp connector signal type2101 * return - true if connected, false otherwise2102 */2103bool dc_link_is_dp_sink_present(struct dc_link *link);2104 2105/* Force DP lane settings update to main-link video signal and notify the change2106 * to DP RX via DPCD. This is a debug interface used for video signal integrity2107 * tuning purpose. The interface assumes link has already been enabled with DP2108 * signal.2109 *2110 * @lt_settings - a container structure with desired hw_lane_settings2111 */2112void dc_link_set_drive_settings(struct dc *dc,2113				struct link_training_settings *lt_settings,2114				struct dc_link *link);2115 2116/* Enable a test pattern in Link or PHY layer in an active link for compliance2117 * test or debugging purpose. The test pattern will remain until next un-plug.2118 *2119 * @link - active link with DP signal output enabled.2120 * @test_pattern - desired test pattern to output.2121 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern.2122 * @test_pattern_color_space - for video test pattern choose a desired color2123 * space.2124 * @p_link_settings - For PHY pattern choose a desired link settings2125 * @p_custom_pattern - some test pattern will require a custom input to2126 * customize some pattern details. Otherwise keep it to NULL.2127 * @cust_pattern_size - size of the custom pattern input.2128 *2129 */2130bool dc_link_dp_set_test_pattern(2131	struct dc_link *link,2132	enum dp_test_pattern test_pattern,2133	enum dp_test_pattern_color_space test_pattern_color_space,2134	const struct link_training_settings *p_link_settings,2135	const unsigned char *p_custom_pattern,2136	unsigned int cust_pattern_size);2137 2138/* Force DP link settings to always use a specific value until reboot to a2139 * specific link. If link has already been enabled, the interface will also2140 * switch to desired link settings immediately. This is a debug interface to2141 * generic dp issue trouble shooting.2142 */2143void dc_link_set_preferred_link_settings(struct dc *dc,2144		struct dc_link_settings *link_setting,2145		struct dc_link *link);2146 2147/* Force DP link to customize a specific link training behavior by overriding to2148 * standard DP specs defined protocol. This is a debug interface to trouble shoot2149 * display specific link training issues or apply some display specific2150 * workaround in link training.2151 *2152 * @link_settings - if not NULL, force preferred link settings to the link.2153 * @lt_override - a set of override pointers. If any pointer is none NULL, dc2154 * will apply this particular override in future link training. If NULL is2155 * passed in, dc resets previous overrides.2156 * NOTE: DM must keep the memory from override pointers until DM resets preferred2157 * training settings.2158 */2159void dc_link_set_preferred_training_settings(struct dc *dc,2160		struct dc_link_settings *link_setting,2161		struct dc_link_training_overrides *lt_overrides,2162		struct dc_link *link,2163		bool skip_immediate_retrain);2164 2165/* return - true if FEC is supported with connected DP RX, false otherwise */2166bool dc_link_is_fec_supported(const struct dc_link *link);2167 2168/* query FEC enablement policy to determine if FEC will be enabled by dc during2169 * link enablement.2170 * return - true if FEC should be enabled, false otherwise.2171 */2172bool dc_link_should_enable_fec(const struct dc_link *link);2173 2174/* determine lttpr mode the current link should be enabled with a specific link2175 * settings.2176 */2177enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link,2178		struct dc_link_settings *link_setting);2179 2180/* Force DP RX to update its power state.2181 * NOTE: this interface doesn't update dp main-link. Calling this function will2182 * cause DP TX main-link and DP RX power states out of sync. DM has to restore2183 * RX power state back upon finish DM specific execution requiring DP RX in a2184 * specific power state.2185 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power2186 * state.2187 */2188void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on);2189 2190/* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite2191 * current value read from extended receiver cap from 02200h - 0220Fh.2192 * Some DP RX has problems of providing accurate DP receiver caps from extended2193 * field, this interface is a workaround to revert link back to use base caps.2194 */2195void dc_link_overwrite_extended_receiver_cap(2196		struct dc_link *link);2197 2198void dc_link_edp_panel_backlight_power_on(struct dc_link *link,2199		bool wait_for_hpd);2200 2201/* Set backlight level of an embedded panel (eDP, LVDS).2202 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer2203 * and 16 bit fractional, where 1.0 is max backlight value.2204 */2205bool dc_link_set_backlight_level(const struct dc_link *dc_link,2206		uint32_t backlight_pwm_u16_16,2207		uint32_t frame_ramp);2208 2209/* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */2210bool dc_link_set_backlight_level_nits(struct dc_link *link,2211		bool isHDR,2212		uint32_t backlight_millinits,2213		uint32_t transition_time_in_ms);2214 2215bool dc_link_get_backlight_level_nits(struct dc_link *link,2216		uint32_t *backlight_millinits,2217		uint32_t *backlight_millinits_peak);2218 2219int dc_link_get_backlight_level(const struct dc_link *dc_link);2220 2221int dc_link_get_target_backlight_pwm(const struct dc_link *link);2222 2223bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable,2224		bool wait, bool force_static, const unsigned int *power_opts);2225 2226bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state);2227 2228bool dc_link_setup_psr(struct dc_link *dc_link,2229		const struct dc_stream_state *stream, struct psr_config *psr_config,2230		struct psr_context *psr_context);2231 2232/*2233 * Communicate with DMUB to allow or disallow Panel Replay on the specified link:2234 *2235 * @link: pointer to the dc_link struct instance2236 * @enable: enable(active) or disable(inactive) replay2237 * @wait: state transition need to wait the active set completed.2238 * @force_static: force disable(inactive) the replay2239 * @power_opts: set power optimazation parameters to DMUB.2240 *2241 * return: allow Replay active will return true, else will return false.2242 */2243bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,2244		bool wait, bool force_static, const unsigned int *power_opts);2245 2246bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state);2247 2248/* On eDP links this function call will stall until T12 has elapsed.2249 * If the panel is not in power off state, this function will return2250 * immediately.2251 */2252bool dc_link_wait_for_t12(struct dc_link *link);2253 2254/* Determine if dp trace has been initialized to reflect upto date result *2255 * return - true if trace is initialized and has valid data. False dp trace2256 * doesn't have valid result.2257 */2258bool dc_dp_trace_is_initialized(struct dc_link *link);2259 2260/* Query a dp trace flag to indicate if the current dp trace data has been2261 * logged before2262 */2263bool dc_dp_trace_is_logged(struct dc_link *link,2264		bool in_detection);2265 2266/* Set dp trace flag to indicate whether DM has already logged the current dp2267 * trace data. DM can set is_logged to true upon logging and check2268 * dc_dp_trace_is_logged before logging to avoid logging the same result twice.2269 */2270void dc_dp_trace_set_is_logged_flag(struct dc_link *link,2271		bool in_detection,2272		bool is_logged);2273 2274/* Obtain driver time stamp for last dp link training end. The time stamp is2275 * formatted based on dm_get_timestamp DM function.2276 * @in_detection - true to get link training end time stamp of last link2277 * training in detection sequence. false to get link training end time stamp2278 * of last link training in commit (dpms) sequence2279 */2280unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link,2281		bool in_detection);2282 2283/* Get how many link training attempts dc has done with latest sequence.2284 * @in_detection - true to get link training count of last link2285 * training in detection sequence. false to get link training count of last link2286 * training in commit (dpms) sequence2287 */2288const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link,2289		bool in_detection);2290 2291/* Get how many link loss has happened since last link training attempts */2292unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link);2293 2294/*2295 *  USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS2296 */2297/*2298 * Send a request from DP-Tx requesting to allocate BW remotely after2299 * allocating it locally. This will get processed by CM and a CB function2300 * will be called.2301 *2302 * @link: pointer to the dc_link struct instance2303 * @req_bw: The requested bw in Kbyte to allocated2304 *2305 * return: none2306 */2307void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw);2308 2309/*2310 * Handle function for when the status of the Request above is complete.2311 * We will find out the result of allocating on CM and update structs.2312 *2313 * @link: pointer to the dc_link struct instance2314 * @bw: Allocated or Estimated BW depending on the result2315 * @result: Response type2316 *2317 * return: none2318 */2319void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link,2320		uint8_t bw, uint8_t result);2321 2322/*2323 * Handle the USB4 BW Allocation related functionality here:2324 * Plug => Try to allocate max bw from timing parameters supported by the sink2325 * Unplug => de-allocate bw2326 *2327 * @link: pointer to the dc_link struct instance2328 * @peak_bw: Peak bw used by the link/sink2329 *2330 * return: allocated bw else return 02331 */2332int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(2333		struct dc_link *link, int peak_bw);2334 2335/*2336 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed2337 * available BW for each host router2338 *2339 * @dc: pointer to dc struct2340 * @stream: pointer to all possible streams2341 * @count: number of valid DPIA streams2342 *2343 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE2344 */2345bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams,2346		const unsigned int count);2347 2348/* Sink Interfaces - A sink corresponds to a display output device */2349 2350struct dc_container_id {2351	// 128bit GUID in binary form2352	unsigned char  guid[16];2353	// 8 byte port ID -> ELD.PortID2354	unsigned int   portId[2];2355	// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName2356	unsigned short manufacturerName;2357	// 2 byte product code -> ELD.ProductCode2358	unsigned short productCode;2359};2360 2361 2362struct dc_sink_dsc_caps {2363	// 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),2364	// 'false' if they are sink's DSC caps2365	bool is_virtual_dpcd_dsc;2366	// 'true' if MST topology supports DSC passthrough for sink2367	// 'false' if MST topology does not support DSC passthrough2368	bool is_dsc_passthrough_supported;2369	struct dsc_dec_dpcd_caps dsc_dec_caps;2370};2371 2372struct dc_sink_fec_caps {2373	bool is_rx_fec_supported;2374	bool is_topology_fec_supported;2375};2376 2377struct scdc_caps {2378	union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI;2379	union hdmi_scdc_device_id_data device_id;2380};2381 2382/*2383 * The sink structure contains EDID and other display device properties2384 */2385struct dc_sink {2386	enum signal_type sink_signal;2387	struct dc_edid dc_edid; /* raw edid */2388	struct dc_edid_caps edid_caps; /* parse display caps */2389	struct dc_container_id *dc_container_id;2390	uint32_t dongle_max_pix_clk;2391	void *priv;2392	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];2393	bool converter_disable_audio;2394 2395	struct scdc_caps scdc_caps;2396	struct dc_sink_dsc_caps dsc_caps;2397	struct dc_sink_fec_caps fec_caps;2398 2399	bool is_vsc_sdp_colorimetry_supported;2400 2401	/* private to DC core */2402	struct dc_link *link;2403	struct dc_context *ctx;2404 2405	uint32_t sink_id;2406 2407	/* private to dc_sink.c */2408	// refcount must be the last member in dc_sink, since we want the2409	// sink structure to be logically cloneable up to (but not including)2410	// refcount2411	struct kref refcount;2412};2413 2414void dc_sink_retain(struct dc_sink *sink);2415void dc_sink_release(struct dc_sink *sink);2416 2417struct dc_sink_init_data {2418	enum signal_type sink_signal;2419	struct dc_link *link;2420	uint32_t dongle_max_pix_clk;2421	bool converter_disable_audio;2422};2423 2424struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);2425 2426/* Newer interfaces  */2427struct dc_cursor {2428	struct dc_plane_address address;2429	struct dc_cursor_attributes attributes;2430};2431 2432 2433/* Interrupt interfaces */2434enum dc_irq_source dc_interrupt_to_irq_source(2435		struct dc *dc,2436		uint32_t src_id,2437		uint32_t ext_id);2438bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);2439void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);2440enum dc_irq_source dc_get_hpd_irq_source_at_index(2441		struct dc *dc, uint32_t link_index);2442 2443void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);2444 2445/* Power Interfaces */2446 2447void dc_set_power_state(2448		struct dc *dc,2449		enum dc_acpi_cm_power_state power_state);2450void dc_resume(struct dc *dc);2451 2452void dc_power_down_on_boot(struct dc *dc);2453 2454/*2455 * HDCP Interfaces2456 */2457enum hdcp_message_status dc_process_hdcp_msg(2458		enum signal_type signal,2459		struct dc_link *link,2460		struct hdcp_protection_message *message_info);2461bool dc_is_dmcu_initialized(struct dc *dc);2462 2463enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);2464void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);2465 2466bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,2467		unsigned int pitch,2468		unsigned int height,2469		enum surface_pixel_format format,2470		struct dc_cursor_attributes *cursor_attr);2471 2472#define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__)2473#define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__)2474 2475void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name);2476void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name);2477bool dc_dmub_is_ips_idle_state(struct dc *dc);2478 2479/* set min and max memory clock to lowest and highest DPM level, respectively */2480void dc_unlock_memory_clock_frequency(struct dc *dc);2481 2482/* set min memory clock to the min required for current mode, max to maxDPM */2483void dc_lock_memory_clock_frequency(struct dc *dc);2484 2485/* set soft max for memclk, to be used for AC/DC switching clock limitations */2486void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);2487 2488/* cleanup on driver unload */2489void dc_hardware_release(struct dc *dc);2490 2491/* disables fw based mclk switch */2492void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);2493 2494bool dc_set_psr_allow_active(struct dc *dc, bool enable);2495 2496bool dc_set_replay_allow_active(struct dc *dc, bool active);2497 2498bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips);2499 2500void dc_z10_restore(const struct dc *dc);2501void dc_z10_save_init(struct dc *dc);2502 2503bool dc_is_dmub_outbox_supported(struct dc *dc);2504bool dc_enable_dmub_notifications(struct dc *dc);2505 2506bool dc_abm_save_restore(2507		struct dc *dc,2508		struct dc_stream_state *stream,2509		struct abm_save_restore *pData);2510 2511void dc_enable_dmub_outbox(struct dc *dc);2512 2513bool dc_process_dmub_aux_transfer_async(struct dc *dc,2514				uint32_t link_index,2515				struct aux_payload *payload);2516 2517/* Get dc link index from dpia port index */2518uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,2519				uint8_t dpia_port_index);2520 2521bool dc_process_dmub_set_config_async(struct dc *dc,2522				uint32_t link_index,2523				struct set_config_cmd_payload *payload,2524				struct dmub_notification *notify);2525 2526enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,2527				uint32_t link_index,2528				uint8_t mst_alloc_slots,2529				uint8_t *mst_slots_in_use);2530 2531void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps);2532 2533void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,2534				uint32_t hpd_int_enable);2535 2536void dc_print_dmub_diagnostic_data(const struct dc *dc);2537 2538void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);2539 2540struct dc_power_profile {2541	int power_level; /* Lower is better */2542};2543 2544struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context);2545 2546/* DSC Interfaces */2547#include "dc_dsc.h"2548 2549/* Disable acc mode Interfaces */2550void dc_disable_accelerated_mode(struct dc *dc);2551 2552bool dc_is_timing_changed(struct dc_stream_state *cur_stream,2553		       struct dc_stream_state *new_stream);2554 2555#endif /* DC_INTERFACE_H_ */2556