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1/*2 * Copyright 2012-15 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef __DC_LINK_ENCODER__DCE110_H__27#define __DC_LINK_ENCODER__DCE110_H__28 29#include "link_encoder.h"30 31#define TO_DCE110_LINK_ENC(link_encoder)\32 container_of(link_encoder, struct dce110_link_encoder, base)33 34/* Not found regs in dce120 spec35 * BIOS_SCRATCH_236 * DP_DPHY_INTERNAL_CTRL37 */38 39#define AUX_REG_LIST(id)\40 SRI(AUX_CONTROL, DP_AUX, id), \41 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \42 SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)43 44#define HPD_REG_LIST(id)\45 SRI(DC_HPD_CONTROL, HPD, id)46 47#define LE_COMMON_REG_LIST_BASE(id) \48 SR(DMCU_RAM_ACCESS_CTRL), \49 SR(DMCU_IRAM_RD_CTRL), \50 SR(DMCU_IRAM_RD_DATA), \51 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \52 SRI(DIG_BE_CNTL, DIG, id), \53 SRI(DIG_BE_EN_CNTL, DIG, id), \54 SRI(DP_CONFIG, DP, id), \55 SRI(DP_DPHY_CNTL, DP, id), \56 SRI(DP_DPHY_PRBS_CNTL, DP, id), \57 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\58 SRI(DP_DPHY_SYM0, DP, id), \59 SRI(DP_DPHY_SYM1, DP, id), \60 SRI(DP_DPHY_SYM2, DP, id), \61 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \62 SRI(DP_LINK_CNTL, DP, id), \63 SRI(DP_LINK_FRAMING_CNTL, DP, id), \64 SRI(DP_MSE_SAT0, DP, id), \65 SRI(DP_MSE_SAT1, DP, id), \66 SRI(DP_MSE_SAT2, DP, id), \67 SRI(DP_MSE_SAT_UPDATE, DP, id), \68 SRI(DP_SEC_CNTL, DP, id), \69 SRI(DP_VID_STREAM_CNTL, DP, id), \70 SRI(DP_DPHY_FAST_TRAINING, DP, id), \71 SRI(DP_SEC_CNTL1, DP, id)72 73#define LE_COMMON_REG_LIST(id)\74 LE_COMMON_REG_LIST_BASE(id), \75 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \76 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \77 SR(DCI_MEM_PWR_STATUS)78 79#if defined(CONFIG_DRM_AMD_DC_SI)80#define LE_DCE60_REG_LIST(id)\81 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \82 SR(DMCU_RAM_ACCESS_CTRL), \83 SR(DMCU_IRAM_RD_CTRL), \84 SR(DMCU_IRAM_RD_DATA), \85 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \86 SRI(DIG_BE_CNTL, DIG, id), \87 SRI(DIG_BE_EN_CNTL, DIG, id), \88 SRI(DP_CONFIG, DP, id), \89 SRI(DP_DPHY_CNTL, DP, id), \90 SRI(DP_DPHY_PRBS_CNTL, DP, id), \91 SRI(DP_DPHY_SYM0, DP, id), \92 SRI(DP_DPHY_SYM1, DP, id), \93 SRI(DP_DPHY_SYM2, DP, id), \94 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \95 SRI(DP_LINK_CNTL, DP, id), \96 SRI(DP_LINK_FRAMING_CNTL, DP, id), \97 SRI(DP_MSE_SAT0, DP, id), \98 SRI(DP_MSE_SAT1, DP, id), \99 SRI(DP_MSE_SAT2, DP, id), \100 SRI(DP_MSE_SAT_UPDATE, DP, id), \101 SRI(DP_SEC_CNTL, DP, id), \102 SRI(DP_VID_STREAM_CNTL, DP, id), \103 SRI(DP_DPHY_FAST_TRAINING, DP, id), \104 SRI(DP_SEC_CNTL1, DP, id)105#endif106 107#define LE_DCE80_REG_LIST(id)\108 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \109 LE_COMMON_REG_LIST_BASE(id)110 111#define LE_DCE100_REG_LIST(id)\112 LE_COMMON_REG_LIST_BASE(id), \113 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \114 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \115 SR(DCI_MEM_PWR_STATUS)116 117#define LE_DCE110_REG_LIST(id)\118 LE_COMMON_REG_LIST_BASE(id), \119 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \120 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \121 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \122 SR(DCI_MEM_PWR_STATUS)123 124#define LE_DCE120_REG_LIST(id)\125 LE_COMMON_REG_LIST_BASE(id), \126 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \127 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \128 SR(DCI_MEM_PWR_STATUS)129 130#define LE_DCN10_REG_LIST(id)\131 LE_COMMON_REG_LIST_BASE(id), \132 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \133 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \134 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)135 136struct dce110_link_enc_aux_registers {137 uint32_t AUX_CONTROL;138 uint32_t AUX_DPHY_RX_CONTROL0;139 uint32_t AUX_DPHY_RX_CONTROL1;140};141 142struct dce110_link_enc_hpd_registers {143 uint32_t DC_HPD_CONTROL;144};145 146struct dce110_link_enc_registers {147 /* DMCU registers */148 uint32_t MASTER_COMM_DATA_REG1;149 uint32_t MASTER_COMM_DATA_REG2;150 uint32_t MASTER_COMM_DATA_REG3;151 uint32_t MASTER_COMM_CMD_REG;152 uint32_t MASTER_COMM_CNTL_REG;153 uint32_t DMCU_RAM_ACCESS_CTRL;154 uint32_t DCI_MEM_PWR_STATUS;155 uint32_t DMU_MEM_PWR_CNTL;156 uint32_t DMCU_IRAM_RD_CTRL;157 uint32_t DMCU_IRAM_RD_DATA;158 uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;159 160 /* Common DP registers */161 uint32_t DIG_BE_CNTL;162 uint32_t DIG_BE_EN_CNTL;163 uint32_t DP_CONFIG;164 uint32_t DP_DPHY_CNTL;165 uint32_t DP_DPHY_INTERNAL_CTRL;166 uint32_t DP_DPHY_PRBS_CNTL;167 uint32_t DP_DPHY_SCRAM_CNTL;168 uint32_t DP_DPHY_SYM0;169 uint32_t DP_DPHY_SYM1;170 uint32_t DP_DPHY_SYM2;171 uint32_t DP_DPHY_TRAINING_PATTERN_SEL;172 uint32_t DP_LINK_CNTL;173 uint32_t DP_LINK_FRAMING_CNTL;174 uint32_t DP_MSE_SAT0;175 uint32_t DP_MSE_SAT1;176 uint32_t DP_MSE_SAT2;177 uint32_t DP_MSE_SAT_UPDATE;178 uint32_t DP_SEC_CNTL;179 uint32_t DP_VID_STREAM_CNTL;180 uint32_t DP_DPHY_FAST_TRAINING;181 uint32_t DP_DPHY_BS_SR_SWAP_CNTL;182 uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;183 uint32_t DP_SEC_CNTL1;184};185 186struct dce110_link_encoder {187 struct link_encoder base;188 const struct dce110_link_enc_registers *link_regs;189 const struct dce110_link_enc_aux_registers *aux_regs;190 const struct dce110_link_enc_hpd_registers *hpd_regs;191};192 193 194void dce110_link_encoder_construct(195 struct dce110_link_encoder *enc110,196 const struct encoder_init_data *init_data,197 const struct encoder_feature_support *enc_features,198 const struct dce110_link_enc_registers *link_regs,199 const struct dce110_link_enc_aux_registers *aux_regs,200 const struct dce110_link_enc_hpd_registers *hpd_regs);201 202#if defined(CONFIG_DRM_AMD_DC_SI)203void dce60_link_encoder_construct(204 struct dce110_link_encoder *enc110,205 const struct encoder_init_data *init_data,206 const struct encoder_feature_support *enc_features,207 const struct dce110_link_enc_registers *link_regs,208 const struct dce110_link_enc_aux_registers *aux_regs,209 const struct dce110_link_enc_hpd_registers *hpd_regs);210#endif211 212bool dce110_link_encoder_validate_dvi_output(213 const struct dce110_link_encoder *enc110,214 enum signal_type connector_signal,215 enum signal_type signal,216 const struct dc_crtc_timing *crtc_timing);217 218bool dce110_link_encoder_validate_rgb_output(219 const struct dce110_link_encoder *enc110,220 const struct dc_crtc_timing *crtc_timing);221 222bool dce110_link_encoder_validate_dp_output(223 const struct dce110_link_encoder *enc110,224 const struct dc_crtc_timing *crtc_timing);225 226bool dce110_link_encoder_validate_wireless_output(227 const struct dce110_link_encoder *enc110,228 const struct dc_crtc_timing *crtc_timing);229 230bool dce110_link_encoder_validate_output_with_stream(231 struct link_encoder *enc,232 const struct dc_stream_state *stream);233 234/****************** HW programming ************************/235 236/* initialize HW */ /* why do we initialze aux in here? */237void dce110_link_encoder_hw_init(struct link_encoder *enc);238 239void dce110_link_encoder_destroy(struct link_encoder **enc);240 241/* program DIG_MODE in DIG_BE */242/* TODO can this be combined with enable_output? */243void dce110_link_encoder_setup(244 struct link_encoder *enc,245 enum signal_type signal);246 247/* enables TMDS PHY output */248/* TODO: still need depth or just pass in adjusted pixel clock? */249void dce110_link_encoder_enable_tmds_output(250 struct link_encoder *enc,251 enum clock_source_id clock_source,252 enum dc_color_depth color_depth,253 enum signal_type signal,254 uint32_t pixel_clock);255 256/* enables DP PHY output */257void dce110_link_encoder_enable_dp_output(258 struct link_encoder *enc,259 const struct dc_link_settings *link_settings,260 enum clock_source_id clock_source);261 262/* enables DP PHY output in MST mode */263void dce110_link_encoder_enable_dp_mst_output(264 struct link_encoder *enc,265 const struct dc_link_settings *link_settings,266 enum clock_source_id clock_source);267 268/* enables LVDS PHY output */269void dce110_link_encoder_enable_lvds_output(270 struct link_encoder *enc,271 enum clock_source_id clock_source,272 uint32_t pixel_clock);273 274/* disable PHY output */275void dce110_link_encoder_disable_output(276 struct link_encoder *enc,277 enum signal_type signal);278 279/* set DP lane settings */280void dce110_link_encoder_dp_set_lane_settings(281 struct link_encoder *enc,282 const struct dc_link_settings *link_settings,283 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);284 285void dce110_link_encoder_dp_set_phy_pattern(286 struct link_encoder *enc,287 const struct encoder_set_dp_phy_pattern_param *param);288 289/* programs DP MST VC payload allocation */290void dce110_link_encoder_update_mst_stream_allocation_table(291 struct link_encoder *enc,292 const struct link_mst_stream_allocation_table *table);293 294void dce110_link_encoder_connect_dig_be_to_fe(295 struct link_encoder *enc,296 enum engine_id engine,297 bool connect);298 299unsigned int dce110_get_dig_frontend(struct link_encoder *enc);300 301void dce110_link_encoder_set_dp_phy_pattern_training_pattern(302 struct link_encoder *enc,303 uint32_t index);304 305void dce110_link_encoder_enable_hpd(struct link_encoder *enc);306 307void dce110_link_encoder_disable_hpd(struct link_encoder *enc);308 309void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,310 bool exit_link_training_required);311 312void dce110_psr_program_secondary_packet(struct link_encoder *enc,313 unsigned int sdp_transmit_line_num_deadline);314 315bool dce110_is_dig_enabled(struct link_encoder *enc);316 317void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc,318 struct dc_link_settings *link_settings);319 320#endif /* __DC_LINK_ENCODER__DCE110_H__ */321