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1/*2 * Copyright 2017 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef _DCN10_IPP_H_27#define _DCN10_IPP_H_28 29#include "ipp.h"30 31#define TO_DCN10_IPP(ipp)\32 container_of(ipp, struct dcn10_ipp, base)33 34#define IPP_REG_LIST_DCN(id) \35 SRI(FORMAT_CONTROL, CNVC_CFG, id), \36 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \37 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \38 SRI(CURSOR0_COLOR0, CNVC_CUR, id), \39 SRI(CURSOR0_COLOR1, CNVC_CUR, id)40 41#define IPP_REG_LIST_DCN10(id) \42 IPP_REG_LIST_DCN(id), \43 SRI(CURSOR_SETTINS, HUBPREQ, id), \44 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \45 SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \46 SRI(CURSOR_SIZE, CURSOR, id), \47 SRI(CURSOR_CONTROL, CURSOR, id), \48 SRI(CURSOR_POSITION, CURSOR, id), \49 SRI(CURSOR_HOT_SPOT, CURSOR, id), \50 SRI(CURSOR_DST_OFFSET, CURSOR, id)51 52#define IPP_REG_LIST_DCN20(id) \53 IPP_REG_LIST_DCN(id), \54 SRI(CURSOR_SETTINGS, HUBPREQ, id), \55 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \56 SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \57 SRI(CURSOR_SIZE, CURSOR0_, id), \58 SRI(CURSOR_CONTROL, CURSOR0_, id), \59 SRI(CURSOR_POSITION, CURSOR0_, id), \60 SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \61 SRI(CURSOR_DST_OFFSET, CURSOR0_, id)62 63#define IPP_REG_LIST_DCN201(id) \64 IPP_REG_LIST_DCN(id), \65 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \66 SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \67 SRI(CURSOR_SIZE, CURSOR0_, id), \68 SRI(CURSOR_CONTROL, CURSOR0_, id), \69 SRI(CURSOR_POSITION, CURSOR0_, id), \70 SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \71 SRI(CURSOR_DST_OFFSET, CURSOR0_, id)72 73#define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x474#define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L75 76#define IPP_SF(reg_name, field_name, post_fix)\77 .field_name = reg_name ## __ ## field_name ## post_fix78 79#define IPP_MASK_SH_LIST_DCN(mask_sh) \80 IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \81 IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \82 IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \83 IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \84 IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \85 IPP_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \86 IPP_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \87 IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \88 IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh)89 90#define IPP_MASK_SH_LIST_DCN10(mask_sh) \91 IPP_MASK_SH_LIST_DCN(mask_sh),\92 IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \93 IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \94 IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \95 IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \96 IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \97 IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \98 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \99 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \100 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \101 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \102 IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \103 IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \104 IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \105 IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \106 IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \107 IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \108 IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh)109 110#define IPP_MASK_SH_LIST_DCN20(mask_sh) \111 IPP_MASK_SH_LIST_DCN(mask_sh), \112 IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \113 IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \114 IPP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \115 IPP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \116 IPP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \117 IPP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \118 IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \119 IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \120 IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \121 IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \122 IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \123 IPP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \124 IPP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \125 IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \126 IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \127 IPP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)128 129#define IPP_MASK_SH_LIST_DCN201(mask_sh) \130 IPP_MASK_SH_LIST_DCN(mask_sh), \131 IPP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \132 IPP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \133 IPP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \134 IPP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \135 IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \136 IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \137 IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \138 IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \139 IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \140 IPP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \141 IPP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \142 IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \143 IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \144 IPP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)145 146#define IPP_DCN10_REG_FIELD_LIST(type) \147 type CNVC_SURFACE_PIXEL_FORMAT; \148 type CNVC_BYPASS; \149 type ALPHA_EN; \150 type FORMAT_EXPANSION_MODE; \151 type CURSOR0_DST_Y_OFFSET; \152 type CURSOR0_CHUNK_HDL_ADJUST; \153 type CUR0_MODE; \154 type CUR0_COLOR0; \155 type CUR0_COLOR1; \156 type CUR0_EXPANSION_MODE; \157 type CURSOR_SURFACE_ADDRESS_HIGH; \158 type CURSOR_SURFACE_ADDRESS; \159 type CURSOR_WIDTH; \160 type CURSOR_HEIGHT; \161 type CURSOR_MODE; \162 type CURSOR_2X_MAGNIFY; \163 type CURSOR_PITCH; \164 type CURSOR_LINES_PER_CHUNK; \165 type CURSOR_ENABLE; \166 type CUR0_ENABLE; \167 type CURSOR_X_POSITION; \168 type CURSOR_Y_POSITION; \169 type CURSOR_HOT_SPOT_X; \170 type CURSOR_HOT_SPOT_Y; \171 type CURSOR_DST_X_OFFSET; \172 type OUTPUT_FP173 174struct dcn10_ipp_shift {175 IPP_DCN10_REG_FIELD_LIST(uint8_t);176};177 178struct dcn10_ipp_mask {179 IPP_DCN10_REG_FIELD_LIST(uint32_t);180};181 182struct dcn10_ipp_registers {183 uint32_t CURSOR_SETTINS;184 uint32_t CURSOR_SETTINGS;185 uint32_t CNVC_SURFACE_PIXEL_FORMAT;186 uint32_t CURSOR0_CONTROL;187 uint32_t CURSOR0_COLOR0;188 uint32_t CURSOR0_COLOR1;189 uint32_t FORMAT_CONTROL;190 uint32_t CURSOR_SURFACE_ADDRESS_HIGH;191 uint32_t CURSOR_SURFACE_ADDRESS;192 uint32_t CURSOR_SIZE;193 uint32_t CURSOR_CONTROL;194 uint32_t CURSOR_POSITION;195 uint32_t CURSOR_HOT_SPOT;196 uint32_t CURSOR_DST_OFFSET;197};198 199struct dcn10_ipp {200 struct input_pixel_processor base;201 202 const struct dcn10_ipp_registers *regs;203 const struct dcn10_ipp_shift *ipp_shift;204 const struct dcn10_ipp_mask *ipp_mask;205 206 struct dc_cursor_attributes curs_attr;207};208 209void dcn10_ipp_construct(struct dcn10_ipp *ippn10,210 struct dc_context *ctx,211 int inst,212 const struct dcn10_ipp_registers *regs,213 const struct dcn10_ipp_shift *ipp_shift,214 const struct dcn10_ipp_mask *ipp_mask);215 216void dcn20_ipp_construct(struct dcn10_ipp *ippn10,217 struct dc_context *ctx,218 int inst,219 const struct dcn10_ipp_registers *regs,220 const struct dcn10_ipp_shift *ipp_shift,221 const struct dcn10_ipp_mask *ipp_mask);222 223#endif /* _DCN10_IPP_H_ */224