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1/*2 * Copyright 2018 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef DAL_DC_DCN20_DCN20_VMID_H_27#define DAL_DC_DCN20_DCN20_VMID_H_28 29#include "vmid.h"30 31#define DCN20_VMID_REG_LIST(id)\32 SRI(CNTL, DCN_VM_CONTEXT, id),\33 SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\34 SRI(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id),\35 SRI(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id),\36 SRI(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id),\37 SRI(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id),\38 SRI(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id)39 40#define DCN20_VMID_MASK_SH_LIST(mask_sh)\41 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\42 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\43 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\44 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\45 SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\46 SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh),\47 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\48 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)49 50#define DCN20_VMID_REG_FIELD_LIST(type)\51 type VM_CONTEXT0_PAGE_TABLE_DEPTH;\52 type VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE;\53 type VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32;\54 type VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32;\55 type VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4;\56 type VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32;\57 type VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4;\58 type VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO3259 60struct dcn20_vmid_shift {61 DCN20_VMID_REG_FIELD_LIST(uint8_t);62};63 64struct dcn20_vmid_mask {65 DCN20_VMID_REG_FIELD_LIST(uint32_t);66};67 68struct dcn20_vmid {69 struct dc_context *ctx;70 const struct dcn_vmid_registers *regs;71 const struct dcn20_vmid_shift *shifts;72 const struct dcn20_vmid_mask *masks;73};74 75void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config);76 77#endif /* DAL_DC_DCN20_DCN20_VMID_H_ */78