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1/*2 * Copyright 2012-15 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#include "reg_helper.h"27 28#include "core_types.h"29#include "link_encoder.h"30#include "dcn201_link_encoder.h"31#include "stream_encoder.h"32#include "dc_bios_types.h"33 34#include "gpio_service_interface.h"35 36#define CTX \37 enc10->base.ctx38 39#define DC_LOGGER \40 enc10->base.ctx->logger41 42#define REG(reg)\43 (enc10->link_regs->reg)44 45#undef FN46#define FN(reg_name, field_name) \47 enc10->link_shift->field_name, enc10->link_mask->field_name48 49#define IND_REG(index) \50 (enc10->link_regs->index)51 52static void dcn201_link_encoder_get_max_link_cap(struct link_encoder *enc,53 struct dc_link_settings *link_settings)54{55 uint32_t value1, value2;56 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);57 58 dcn10_link_encoder_get_max_link_cap(enc, link_settings);59 REG_GET_2(RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, &value1,60 RDPCS_PHY_DPALT_DP4, &value2);61 /*limit to combo_phy*/62 if (enc->usbc_combo_phy) {63 if (!value1 && !value2 && link_settings->lane_count > LANE_COUNT_TWO)64 link_settings->lane_count = LANE_COUNT_TWO;65 }66}67 68static bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc)69{70 uint32_t value;71 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);72 73 REG_GET(RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, &value);74 75 // if value == 1 alt mode is disabled, otherwise it is enabled76 return !value;77}78 79static const struct link_encoder_funcs dcn201_link_enc_funcs = {80 .read_state = link_enc2_read_state,81 .validate_output_with_stream =82 dcn10_link_encoder_validate_output_with_stream,83 .hw_init = enc2_hw_init,84 .setup = dcn10_link_encoder_setup,85 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,86 .enable_dp_output = dcn10_link_encoder_enable_dp_output,87 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,88 .disable_output = dcn10_link_encoder_disable_output,89 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,90 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,91 .update_mst_stream_allocation_table =92 dcn10_link_encoder_update_mst_stream_allocation_table,93 .psr_program_dp_dphy_fast_training =94 dcn10_psr_program_dp_dphy_fast_training,95 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,96 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,97 .enable_hpd = dcn10_link_encoder_enable_hpd,98 .disable_hpd = dcn10_link_encoder_disable_hpd,99 .is_dig_enabled = dcn10_is_dig_enabled,100 .destroy = dcn10_link_encoder_destroy,101 .fec_set_enable = enc2_fec_set_enable,102 .fec_set_ready = enc2_fec_set_ready,103 .get_dig_frontend = dcn10_get_dig_frontend,104 .fec_is_active = enc2_fec_is_active,105 .is_in_alt_mode = dcn201_link_encoder_is_in_alt_mode,106 .get_max_link_cap = dcn201_link_encoder_get_max_link_cap,107};108 109void dcn201_link_encoder_construct(110 struct dcn20_link_encoder *enc20,111 const struct encoder_init_data *init_data,112 const struct encoder_feature_support *enc_features,113 const struct dcn10_link_enc_registers *link_regs,114 const struct dcn10_link_enc_aux_registers *aux_regs,115 const struct dcn10_link_enc_hpd_registers *hpd_regs,116 const struct dcn10_link_enc_shift *link_shift,117 const struct dcn10_link_enc_mask *link_mask)118{119 struct bp_encoder_cap_info bp_cap_info = {0};120 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;121 enum bp_result result = BP_RESULT_OK;122 struct dcn10_link_encoder *enc10 = &enc20->enc10;123 124 enc10->base.funcs = &dcn201_link_enc_funcs;125 enc10->base.ctx = init_data->ctx;126 enc10->base.id = init_data->encoder;127 128 enc10->base.hpd_source = init_data->hpd_source;129 enc10->base.connector = init_data->connector;130 131 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;132 133 enc10->base.features = *enc_features;134 135 enc10->base.transmitter = init_data->transmitter;136 137 /* set the flag to indicate whether driver poll the I2C data pin138 * while doing the DP sink detect139 */140 141 /* if (dal_adapter_service_is_feature_supported(as,142 * FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))143 * enc10->base.features.flags.bits.144 * DP_SINK_DETECT_POLL_DATA_PIN = true;145 */146 147 enc10->base.output_signals =148 SIGNAL_TYPE_DVI_SINGLE_LINK |149 SIGNAL_TYPE_DVI_DUAL_LINK |150 SIGNAL_TYPE_LVDS |151 SIGNAL_TYPE_DISPLAY_PORT |152 SIGNAL_TYPE_DISPLAY_PORT_MST |153 SIGNAL_TYPE_EDP |154 SIGNAL_TYPE_HDMI_TYPE_A;155 156 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.157 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.158 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer159 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.160 * Prefer DIG assignment is decided by board design.161 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design162 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.163 * By this, adding DIGG should not hurt DCE 8.0.164 * This will let DCE 8.1 share DCE 8.0 as much as possible165 */166 167 enc10->link_regs = link_regs;168 enc10->aux_regs = aux_regs;169 enc10->hpd_regs = hpd_regs;170 enc10->link_shift = link_shift;171 enc10->link_mask = link_mask;172 173 switch (enc10->base.transmitter) {174 case TRANSMITTER_UNIPHY_A:175 enc10->base.preferred_engine = ENGINE_ID_DIGA;176 break;177 case TRANSMITTER_UNIPHY_B:178 enc10->base.preferred_engine = ENGINE_ID_DIGB;179 break;180 default:181 ASSERT_CRITICAL(false);182 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;183 }184 185 /* default to one to mirror Windows behavior */186 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;187 188 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,189 enc10->base.id, &bp_cap_info);190 191 /* Override features with DCE-specific values */192 if (result == BP_RESULT_OK) {193 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =194 bp_cap_info.DP_HBR2_EN;195 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =196 bp_cap_info.DP_HBR3_EN;197 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;198 enc10->base.features.flags.bits.DP_IS_USB_C =199 bp_cap_info.DP_IS_USB_C;200 } else {201 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",202 __func__,203 result);204 }205 if (enc10->base.ctx->dc->debug.hdmi20_disable) {206 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;207 }208}209