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1/*2 * Copyright 2020 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef __DC_PANEL_CNTL__DCN301_H__27#define __DC_PANEL_CNTL__DCN301_H__28 29#include "panel_cntl.h"30#include "dce/dce_panel_cntl.h"31 32 33#define DCN301_PANEL_CNTL_REG_LIST(id)\34 SRIR(PWRSEQ_CNTL, CNTL, PANEL_PWRSEQ, id), \35 SRIR(PWRSEQ_STATE, STATE, PANEL_PWRSEQ, id), \36 SRIR(PWRSEQ_REF_DIV, REF_DIV, PANEL_PWRSEQ, id), \37 SRIR(BL_PWM_CNTL, CNTL, BL_PWM, id), \38 SRIR(BL_PWM_CNTL2, CNTL2, BL_PWM, id), \39 SRIR(BL_PWM_PERIOD_CNTL, PERIOD_CNTL, BL_PWM, id), \40 SRIR(BL_PWM_GRP1_REG_LOCK, GRP1_REG_LOCK, BL_PWM, id)41 42#define DCN301_PANEL_CNTL_SF(reg_name, field_name, post_fix)\43 .field_name = reg_name ## __ ## field_name ## post_fix44 45#define DCN301_PANEL_CNTL_MASK_SH_LIST(mask_sh) \46 DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_BLON, mask_sh),\47 DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_DIGON, mask_sh),\48 DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_DIGON_OVRD, mask_sh),\49 DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_STATE, PANEL_PWRSEQ_TARGET_STATE_R, mask_sh), \50 DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_REF_DIV, BL_PWM_REF_DIV, mask_sh), \51 DCN301_PANEL_CNTL_SF(BL_PWM0_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \52 DCN301_PANEL_CNTL_SF(BL_PWM0_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \53 DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \54 DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \55 DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_PWM_EN, mask_sh), \56 DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \57 DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \58 DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh)59 60#define DCN301_PANEL_CNTL_REG_FIELD_LIST(type) \61 type PANEL_BLON;\62 type PANEL_DIGON;\63 type PANEL_DIGON_OVRD;\64 type PANEL_PWRSEQ_TARGET_STATE_R; \65 type BL_PWM_EN; \66 type BL_ACTIVE_INT_FRAC_CNT; \67 type BL_PWM_FRACTIONAL_EN; \68 type BL_PWM_PERIOD; \69 type BL_PWM_PERIOD_BITCNT; \70 type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \71 type BL_PWM_GRP1_REG_LOCK; \72 type BL_PWM_GRP1_REG_UPDATE_PENDING; \73 type BL_PWM_REF_DIV74 75struct dcn301_panel_cntl_shift {76 DCN301_PANEL_CNTL_REG_FIELD_LIST(uint8_t);77};78 79struct dcn301_panel_cntl_mask {80 DCN301_PANEL_CNTL_REG_FIELD_LIST(uint32_t);81};82 83struct dcn301_panel_cntl {84 struct panel_cntl base;85 const struct dce_panel_cntl_registers *regs;86 const struct dcn301_panel_cntl_shift *shift;87 const struct dcn301_panel_cntl_mask *mask;88};89 90void dcn301_panel_cntl_construct(91 struct dcn301_panel_cntl *panel_cntl,92 const struct panel_cntl_init_data *init_data,93 const struct dce_panel_cntl_registers *regs,94 const struct dcn301_panel_cntl_shift *shift,95 const struct dcn301_panel_cntl_mask *mask);96 97#endif /* __DC_PANEL_CNTL__DCN301_H__ */98