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1/*2 * Copyright 2017 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25#ifndef __DC_FEATURES_H__26#define __DC_FEATURES_H__27 28// local features29#define DC__PRESENT 130#define DC__PRESENT__1 131#define DC__NUM_DPP 432 33/**34 * @DC__VOLTAGE_STATES:35 *36 * Define the maximum amount of states supported by the ASIC. Every ASIC has a37 * specific number of states; this macro defines the maximum number of states.38 */39#define DC__VOLTAGE_STATES 4040#define DC__NUM_DPP__4 141#define DC__NUM_DPP__0_PRESENT 142#define DC__NUM_DPP__1_PRESENT 143#define DC__NUM_DPP__2_PRESENT 144#define DC__NUM_DPP__3_PRESENT 145#define DC__NUM_DPP__MAX 846#define DC__NUM_DPP__MAX__8 147#define DC__PIPE_10BIT 048#define DC__PIPE_10BIT__0 149#define DC__PIPE_10BIT__MAX 150#define DC__PIPE_10BIT__MAX__1 151#define DC__NUM_OPP 452#define DC__NUM_OPP__4 153#define DC__NUM_OPP__0_PRESENT 154#define DC__NUM_OPP__1_PRESENT 155#define DC__NUM_OPP__2_PRESENT 156#define DC__NUM_OPP__3_PRESENT 157#define DC__NUM_OPP__MAX 658#define DC__NUM_OPP__MAX__6 159#define DC__NUM_DSC 060#define DC__NUM_DSC__0 161#define DC__NUM_DSC__MAX 662#define DC__NUM_DSC__MAX__6 163#define DC__NUM_ABM 164#define DC__NUM_ABM__1 165#define DC__NUM_ABM__0_PRESENT 166#define DC__NUM_ABM__MAX 267#define DC__NUM_ABM__MAX__2 168#define DC__ODM_PRESENT 069#define DC__ODM_PRESENT__0 170#define DC__NUM_OTG 471#define DC__NUM_OTG__4 172#define DC__NUM_OTG__0_PRESENT 173#define DC__NUM_OTG__1_PRESENT 174#define DC__NUM_OTG__2_PRESENT 175#define DC__NUM_OTG__3_PRESENT 176#define DC__NUM_OTG__MAX 677#define DC__NUM_OTG__MAX__6 178#define DC__NUM_DWB 279#define DC__NUM_DWB__2 180#define DC__NUM_DWB__0_PRESENT 181#define DC__NUM_DWB__1_PRESENT 182#define DC__NUM_DWB__MAX 283#define DC__NUM_DWB__MAX__2 184#define DC__NUM_DIG 485#define DC__NUM_DIG__4 186#define DC__NUM_DIG__0_PRESENT 187#define DC__NUM_DIG__1_PRESENT 188#define DC__NUM_DIG__2_PRESENT 189#define DC__NUM_DIG__3_PRESENT 190#define DC__NUM_DIG__MAX 691#define DC__NUM_DIG__MAX__6 192#define DC__NUM_AUX 493#define DC__NUM_AUX__4 194#define DC__NUM_AUX__0_PRESENT 195#define DC__NUM_AUX__1_PRESENT 196#define DC__NUM_AUX__2_PRESENT 197#define DC__NUM_AUX__3_PRESENT 198#define DC__NUM_AUX__MAX 699#define DC__NUM_AUX__MAX__6 1100#define DC__NUM_AUDIO_STREAMS 4101#define DC__NUM_AUDIO_STREAMS__4 1102#define DC__NUM_AUDIO_STREAMS__0_PRESENT 1103#define DC__NUM_AUDIO_STREAMS__1_PRESENT 1104#define DC__NUM_AUDIO_STREAMS__2_PRESENT 1105#define DC__NUM_AUDIO_STREAMS__3_PRESENT 1106#define DC__NUM_AUDIO_STREAMS__MAX 8107#define DC__NUM_AUDIO_STREAMS__MAX__8 1108#define DC__NUM_AUDIO_ENDPOINTS 6109#define DC__NUM_AUDIO_ENDPOINTS__6 1110#define DC__NUM_AUDIO_ENDPOINTS__0_PRESENT 1111#define DC__NUM_AUDIO_ENDPOINTS__1_PRESENT 1112#define DC__NUM_AUDIO_ENDPOINTS__2_PRESENT 1113#define DC__NUM_AUDIO_ENDPOINTS__3_PRESENT 1114#define DC__NUM_AUDIO_ENDPOINTS__4_PRESENT 1115#define DC__NUM_AUDIO_ENDPOINTS__5_PRESENT 1116#define DC__NUM_AUDIO_ENDPOINTS__MAX 8117#define DC__NUM_AUDIO_ENDPOINTS__MAX__8 1118#define DC__NUM_AUDIO_INPUT_STREAMS 0119#define DC__NUM_AUDIO_INPUT_STREAMS__0 1120#define DC__NUM_AUDIO_INPUT_STREAMS__MAX 8121#define DC__NUM_AUDIO_INPUT_STREAMS__MAX__8 1122#define DC__NUM_AUDIO_INPUT_ENDPOINTS 0123#define DC__NUM_AUDIO_INPUT_ENDPOINTS__0 1124#define DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX 8125#define DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX__8 1126#define DC__NUM_CURSOR 1127#define DC__NUM_CURSOR__1 1128#define DC__NUM_CURSOR__0_PRESENT 1129#define DC__NUM_CURSOR__MAX 2130#define DC__NUM_CURSOR__MAX__2 1131#define DC__DIGITAL_BYPASS_PRESENT 0132#define DC__DIGITAL_BYPASS_PRESENT__0 1133#define DC__HCID_HWMAJVER 1134#define DC__HCID_HWMAJVER__1 1135#define DC__HCID_HWMINVER 0136#define DC__HCID_HWMINVER__0 1137#define DC__HCID_HWREV 0138#define DC__HCID_HWREV__0 1139#define DC__ROMSTRAP_PRESENT 0140#define DC__ROMSTRAP_PRESENT__0 1141#define DC__NUM_RBBMIF_DECODES 30142#define DC__NUM_RBBMIF_DECODES__30 1143#define DC__NUM_DBG_REGS 36144#define DC__NUM_DBG_REGS__36 1145#define DC__NUM_PIPES_UNDERLAY 0146#define DC__NUM_PIPES_UNDERLAY__0 1147#define DC__NUM_PIPES_UNDERLAY__MAX 2148#define DC__NUM_PIPES_UNDERLAY__MAX__2 1149#define DC__NUM_VCE_ENGINE 1150#define DC__NUM_VCE_ENGINE__1 1151#define DC__NUM_VCE_ENGINE__0_PRESENT 1152#define DC__NUM_VCE_ENGINE__MAX 2153#define DC__NUM_VCE_ENGINE__MAX__2 1154#define DC__OTG_EXTERNAL_SYNC_PRESENT 0155#define DC__OTG_EXTERNAL_SYNC_PRESENT__0 1156#define DC__OTG_CRC_PRESENT 1157#define DC__OTG_CRC_PRESENT__1 1158#define DC__VIP_PRESENT 0159#define DC__VIP_PRESENT__0 1160#define DC__DTMTEST_PRESENT 0161#define DC__DTMTEST_PRESENT__0 1162#define DC__POWER_GATE_PRESENT 1163#define DC__POWER_GATE_PRESENT__1 1164#define DC__MEM_PG 1165#define DC__MEM_PG__1 1166#define DC__FMT_SRC_SEL_PRESENT 0167#define DC__FMT_SRC_SEL_PRESENT__0 1168#define DC__DIG_FEATURES__HDMI_PRESENT 1169#define DC__DIG_FEATURES__HDMI_PRESENT__1 1170#define DC__DIG_FEATURES__DP_PRESENT 1171#define DC__DIG_FEATURES__DP_PRESENT__1 1172#define DC__DIG_FEATURES__DP_MST_PRESENT 1173#define DC__DIG_FEATURES__DP_MST_PRESENT__1 1174#define DC__DIG_LP_FEATURES__HDMI_PRESENT 0175#define DC__DIG_LP_FEATURES__HDMI_PRESENT__0 1176#define DC__DIG_LP_FEATURES__DP_PRESENT 1177#define DC__DIG_LP_FEATURES__DP_PRESENT__1 1178#define DC__DIG_LP_FEATURES__DP_MST_PRESENT 0179#define DC__DIG_LP_FEATURES__DP_MST_PRESENT__0 1180#define DC__DIG_RESYNC_FIFO_SIZE 14181#define DC__DIG_RESYNC_FIFO_SIZE__14 1182#define DC__DIG_RESYNC_FIFO_SIZE__0_PRESENT 1183#define DC__DIG_RESYNC_FIFO_SIZE__1_PRESENT 1184#define DC__DIG_RESYNC_FIFO_SIZE__2_PRESENT 1185#define DC__DIG_RESYNC_FIFO_SIZE__3_PRESENT 1186#define DC__DIG_RESYNC_FIFO_SIZE__4_PRESENT 1187#define DC__DIG_RESYNC_FIFO_SIZE__5_PRESENT 1188#define DC__DIG_RESYNC_FIFO_SIZE__6_PRESENT 1189#define DC__DIG_RESYNC_FIFO_SIZE__7_PRESENT 1190#define DC__DIG_RESYNC_FIFO_SIZE__8_PRESENT 1191#define DC__DIG_RESYNC_FIFO_SIZE__9_PRESENT 1192#define DC__DIG_RESYNC_FIFO_SIZE__10_PRESENT 1193#define DC__DIG_RESYNC_FIFO_SIZE__11_PRESENT 1194#define DC__DIG_RESYNC_FIFO_SIZE__12_PRESENT 1195#define DC__DIG_RESYNC_FIFO_SIZE__13_PRESENT 1196#define DC__DIG_RESYNC_FIFO_SIZE__MAX 16197#define DC__DIG_RESYNC_FIFO_SIZE__MAX__16 1198#define DC__DAC_RESYNC_FIFO_SIZE 12199#define DC__DAC_RESYNC_FIFO_SIZE__12 1200#define DC__DAC_RESYNC_FIFO_SIZE__0_PRESENT 1201#define DC__DAC_RESYNC_FIFO_SIZE__1_PRESENT 1202#define DC__DAC_RESYNC_FIFO_SIZE__2_PRESENT 1203#define DC__DAC_RESYNC_FIFO_SIZE__3_PRESENT 1204#define DC__DAC_RESYNC_FIFO_SIZE__4_PRESENT 1205#define DC__DAC_RESYNC_FIFO_SIZE__5_PRESENT 1206#define DC__DAC_RESYNC_FIFO_SIZE__6_PRESENT 1207#define DC__DAC_RESYNC_FIFO_SIZE__7_PRESENT 1208#define DC__DAC_RESYNC_FIFO_SIZE__8_PRESENT 1209#define DC__DAC_RESYNC_FIFO_SIZE__9_PRESENT 1210#define DC__DAC_RESYNC_FIFO_SIZE__10_PRESENT 1211#define DC__DAC_RESYNC_FIFO_SIZE__11_PRESENT 1212#define DC__DAC_RESYNC_FIFO_SIZE__MAX 16213#define DC__DAC_RESYNC_FIFO_SIZE__MAX__16 1214#define DC__DVO_RESYNC_FIFO_SIZE 12215#define DC__DVO_RESYNC_FIFO_SIZE__12 1216#define DC__DVO_RESYNC_FIFO_SIZE__0_PRESENT 1217#define DC__DVO_RESYNC_FIFO_SIZE__1_PRESENT 1218#define DC__DVO_RESYNC_FIFO_SIZE__2_PRESENT 1219#define DC__DVO_RESYNC_FIFO_SIZE__3_PRESENT 1220#define DC__DVO_RESYNC_FIFO_SIZE__4_PRESENT 1221#define DC__DVO_RESYNC_FIFO_SIZE__5_PRESENT 1222#define DC__DVO_RESYNC_FIFO_SIZE__6_PRESENT 1223#define DC__DVO_RESYNC_FIFO_SIZE__7_PRESENT 1224#define DC__DVO_RESYNC_FIFO_SIZE__8_PRESENT 1225#define DC__DVO_RESYNC_FIFO_SIZE__9_PRESENT 1226#define DC__DVO_RESYNC_FIFO_SIZE__10_PRESENT 1227#define DC__DVO_RESYNC_FIFO_SIZE__11_PRESENT 1228#define DC__DVO_RESYNC_FIFO_SIZE__MAX 16229#define DC__DVO_RESYNC_FIFO_SIZE__MAX__16 1230#define DC__MEM_CDC_PRESENT 1231#define DC__MEM_CDC_PRESENT__1 1232#define DC__NUM_HPD 4233#define DC__NUM_HPD__4 1234#define DC__NUM_HPD__0_PRESENT 1235#define DC__NUM_HPD__1_PRESENT 1236#define DC__NUM_HPD__2_PRESENT 1237#define DC__NUM_HPD__3_PRESENT 1238#define DC__NUM_HPD__MAX 6239#define DC__NUM_HPD__MAX__6 1240#define DC__NUM_DDC_PAIRS 4241#define DC__NUM_DDC_PAIRS__4 1242#define DC__NUM_DDC_PAIRS__0_PRESENT 1243#define DC__NUM_DDC_PAIRS__1_PRESENT 1244#define DC__NUM_DDC_PAIRS__2_PRESENT 1245#define DC__NUM_DDC_PAIRS__3_PRESENT 1246#define DC__NUM_DDC_PAIRS__MAX 6247#define DC__NUM_DDC_PAIRS__MAX__6 1248#define DC__NUM_AUDIO_PLL 0249#define DC__NUM_AUDIO_PLL__0 1250#define DC__NUM_AUDIO_PLL__MAX 2251#define DC__NUM_AUDIO_PLL__MAX__2 1252#define DC__NUM_PIXEL_PLL 1253#define DC__NUM_PIXEL_PLL__1 1254#define DC__NUM_PIXEL_PLL__0_PRESENT 1255#define DC__NUM_PIXEL_PLL__MAX 4256#define DC__NUM_PIXEL_PLL__MAX__4 1257#define DC__NUM_CASCADED_PLL 0258#define DC__NUM_CASCADED_PLL__0 1259#define DC__NUM_CASCADED_PLL__MAX 3260#define DC__NUM_CASCADED_PLL__MAX__3 1261#define DC__PIXCLK_FROM_PHYPLL 1262#define DC__PIXCLK_FROM_PHYPLL__1 1263#define DC__NB_STUTTER_MODE_PRESENT 0264#define DC__NB_STUTTER_MODE_PRESENT__0 1265#define DC__I2S0_AND_SPDIF0_PRESENT 0266#define DC__I2S0_AND_SPDIF0_PRESENT__0 1267#define DC__I2S1_PRESENT 0268#define DC__I2S1_PRESENT__0 1269#define DC__SPDIF1_PRESENT 0270#define DC__SPDIF1_PRESENT__0 1271#define DC__DSI_PRESENT 0272#define DC__DSI_PRESENT__0 1273#define DC__DACA_PRESENT 0274#define DC__DACA_PRESENT__0 1275#define DC__DACB_PRESENT 0276#define DC__DACB_PRESENT__0 1277#define DC__NUM_PIPES 4278#define DC__NUM_PIPES__4 1279#define DC__NUM_PIPES__0_PRESENT 1280#define DC__NUM_PIPES__1_PRESENT 1281#define DC__NUM_PIPES__2_PRESENT 1282#define DC__NUM_PIPES__3_PRESENT 1283#define DC__NUM_PIPES__MAX 6284#define DC__NUM_PIPES__MAX__6 1285#define DC__NUM_DIG_LP 0286#define DC__NUM_DIG_LP__0 1287#define DC__NUM_DIG_LP__MAX 2288#define DC__NUM_DIG_LP__MAX__2 1289#define DC__DPDEBUG_PRESENT 0290#define DC__DPDEBUG_PRESENT__0 1291#define DC__DISPLAY_WB_PRESENT 1292#define DC__DISPLAY_WB_PRESENT__1 1293#define DC__NUM_CWB 0294#define DC__NUM_CWB__0 1295#define DC__NUM_CWB__MAX 2296#define DC__NUM_CWB__MAX__2 1297#define DC__MVP_PRESENT 0298#define DC__MVP_PRESENT__0 1299#define DC__DVO_PRESENT 0300#define DC__DVO_PRESENT__0 1301#define DC__ABM_PRESENT 0302#define DC__ABM_PRESENT__0 1303#define DC__BPHYC_PLL_PRESENT 0304#define DC__BPHYC_PLL_PRESENT__0 1305#define DC__BPHYC_UNIPHY_PRESENT 0306#define DC__BPHYC_UNIPHY_PRESENT__0 1307#define DC__PHY_BROADCAST_PRESENT 0308#define DC__PHY_BROADCAST_PRESENT__0 1309#define DC__NUM_OF_DCRX_SD 0310#define DC__NUM_OF_DCRX_SD__0 1311#define DC__DVO_17BIT_MAPPING 0312#define DC__DVO_17BIT_MAPPING__0 1313#define DC__AVSYNC_PRESENT 0314#define DC__AVSYNC_PRESENT__0 1315#define DC__NUM_OF_DCRX_PORTS 0316#define DC__NUM_OF_DCRX_PORTS__0 1317#define DC__NUM_OF_DCRX_PORTS__MAX 1318#define DC__NUM_OF_DCRX_PORTS__MAX__1 1319#define DC__NUM_PHY 4320#define DC__NUM_PHY__4 1321#define DC__NUM_PHY__0_PRESENT 1322#define DC__NUM_PHY__1_PRESENT 1323#define DC__NUM_PHY__2_PRESENT 1324#define DC__NUM_PHY__3_PRESENT 1325#define DC__NUM_PHY__MAX 7326#define DC__NUM_PHY__MAX__7 1327#define DC__NUM_PHY_LP 0328#define DC__NUM_PHY_LP__0 1329#define DC__NUM_PHY_LP__MAX 2330#define DC__NUM_PHY_LP__MAX__2 1331#define DC__SYNC_CELL vid_sync_gf14lpp332#define DC__SYNC_CELL__VID_SYNC_GF14LPP 1333#define DC__USE_NEW_VSS 1334#define DC__USE_NEW_VSS__1 1335#define DC__SYNC_CELL_DISPCLK_NUM_LATCHES 6336#define DC__SYNC_CELL_DISPCLK_NUM_LATCHES__6 1337#define DC__SYNC_CELL_DVOCLK_NUM_LATCHES 6338#define DC__SYNC_CELL_DVOCLK_NUM_LATCHES__6 1339#define DC__SYNC_CELL_PIXCLK_NUM_LATCHES 6340#define DC__SYNC_CELL_PIXCLK_NUM_LATCHES__6 1341#define DC__SYNC_CELL_SYMCLK_NUM_LATCHES 6342#define DC__SYNC_CELL_SYMCLK_NUM_LATCHES__6 1343#define DC__SYNC_CELL_DPPCLK_NUM_LATCHES 6344#define DC__SYNC_CELL_DPPCLK_NUM_LATCHES__6 1345#define DC__SYNC_CELL_DPREFCLK_NUM_LATCHES 6346#define DC__SYNC_CELL_DPREFCLK_NUM_LATCHES__6 1347#define DC__SYNC_CELL_REFCLK_NUM_LATCHES 6348#define DC__SYNC_CELL_REFCLK_NUM_LATCHES__6 1349#define DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES 6350#define DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES__6 1351#define DC__SYNC_CELL_MVPCLK_NUM_LATCHES 6352#define DC__SYNC_CELL_MVPCLK_NUM_LATCHES__6 1353#define DC__SYNC_CELL_SCLK_NUM_LATCHES 6354#define DC__SYNC_CELL_SCLK_NUM_LATCHES__6 1355#define DC__SYNC_CELL_DCEFCLK_NUM_LATCHES 6356#define DC__SYNC_CELL_DCEFCLK_NUM_LATCHES__6 1357#define DC__SYNC_CELL_AMCLK_NUM_LATCHES 6358#define DC__SYNC_CELL_AMCLK_NUM_LATCHES__6 1359#define DC__SYNC_CELL_DSICLK_NUM_LATCHES 6360#define DC__SYNC_CELL_DSICLK_NUM_LATCHES__6 1361#define DC__SYNC_CELL_BYTECLK_NUM_LATCHES 6362#define DC__SYNC_CELL_BYTECLK_NUM_LATCHES__6 1363#define DC__SYNC_CELL_ESCCLK_NUM_LATCHES 6364#define DC__SYNC_CELL_ESCCLK_NUM_LATCHES__6 1365#define DC__SYNC_CELL_DB_CLK_NUM_LATCHES 6366#define DC__SYNC_CELL_DB_CLK_NUM_LATCHES__6 1367#define UNIPHYA_PRESENT 1368#define UNIPHYA_PRESENT__1 1369#define DC__UNIPHYA_PRESENT 1370#define DC__UNIPHYA_PRESENT__1 1371#define UNIPHYB_PRESENT 1372#define UNIPHYB_PRESENT__1 1373#define DC__UNIPHYB_PRESENT 1374#define DC__UNIPHYB_PRESENT__1 1375#define UNIPHYC_PRESENT 1376#define UNIPHYC_PRESENT__1 1377#define DC__UNIPHYC_PRESENT 1378#define DC__UNIPHYC_PRESENT__1 1379#define UNIPHYD_PRESENT 1380#define UNIPHYD_PRESENT__1 1381#define DC__UNIPHYD_PRESENT 1382#define DC__UNIPHYD_PRESENT__1 1383#define UNIPHYE_PRESENT 0384#define UNIPHYE_PRESENT__0 1385#define DC__UNIPHYE_PRESENT 0386#define DC__UNIPHYE_PRESENT__0 1387#define UNIPHYF_PRESENT 0388#define UNIPHYF_PRESENT__0 1389#define DC__UNIPHYF_PRESENT 0390#define DC__UNIPHYF_PRESENT__0 1391#define UNIPHYG_PRESENT 0392#define UNIPHYG_PRESENT__0 1393#define DC__UNIPHYG_PRESENT 0394#define DC__UNIPHYG_PRESENT__0 1395#define DC__TMDS_LINK tmds_link_dual396#define DC__TMDS_LINK__TMDS_LINK_DUAL 1397#define DC__WBSCL_PIXBW 8398#define DC__WBSCL_PIXBW__8 1399#define DC__DWB_CSC_PRESENT 0400#define DC__DWB_CSC_PRESENT__0 1401#define DC__DWB_LUMA_SCL_PRESENT 0402#define DC__DWB_LUMA_SCL_PRESENT__0 1403#define DC__DENTIST_INTERFACE_PRESENT 1404#define DC__DENTIST_INTERFACE_PRESENT__1 1405#define DC__GENERICA_PRESENT 1406#define DC__GENERICA_PRESENT__1 1407#define DC__GENERICB_PRESENT 1408#define DC__GENERICB_PRESENT__1 1409#define DC__GENERICC_PRESENT 0410#define DC__GENERICC_PRESENT__0 1411#define DC__GENERICD_PRESENT 0412#define DC__GENERICD_PRESENT__0 1413#define DC__GENERICE_PRESENT 0414#define DC__GENERICE_PRESENT__0 1415#define DC__GENERICF_PRESENT 0416#define DC__GENERICF_PRESENT__0 1417#define DC__GENERICG_PRESENT 0418#define DC__GENERICG_PRESENT__0 1419#define DC__UNIPHY_VOLTAGE_MODE 1420#define DC__UNIPHY_VOLTAGE_MODE__1 1421#define DC__BLON_TYPE dedicated422#define DC__BLON_TYPE__DEDICATED 1423#define DC__UNIPHY_STAGGER_CH_PRESENT 1424#define DC__UNIPHY_STAGGER_CH_PRESENT__1 1425#define DC__XDMA_PRESENT 0426#define DC__XDMA_PRESENT__0 1427#define XDMA__PRESENT 0428#define XDMA__PRESENT__0 1429#define DC__DP_MEM_PG 0430#define DC__DP_MEM_PG__0 1431#define DP__MEM_PG 0432#define DP__MEM_PG__0 1433#define DC__AFMT_MEM_PG 0434#define DC__AFMT_MEM_PG__0 1435#define AFMT__MEM_PG 0436#define AFMT__MEM_PG__0 1437#define DC__HDMI_MEM_PG 0438#define DC__HDMI_MEM_PG__0 1439#define HDMI__MEM_PG 0440#define HDMI__MEM_PG__0 1441#define DC__I2C_MEM_PG 0442#define DC__I2C_MEM_PG__0 1443#define I2C__MEM_PG 0444#define I2C__MEM_PG__0 1445#define DC__DSCL_MEM_PG 0446#define DC__DSCL_MEM_PG__0 1447#define DSCL__MEM_PG 0448#define DSCL__MEM_PG__0 1449#define DC__CM_MEM_PG 0450#define DC__CM_MEM_PG__0 1451#define CM__MEM_PG 0452#define CM__MEM_PG__0 1453#define DC__OBUF_MEM_PG 0454#define DC__OBUF_MEM_PG__0 1455#define OBUF__MEM_PG 0456#define OBUF__MEM_PG__0 1457#define DC__WBIF_MEM_PG 1458#define DC__WBIF_MEM_PG__1 1459#define WBIF__MEM_PG 1460#define WBIF__MEM_PG__1 1461#define DC__VGA_MEM_PG 0462#define DC__VGA_MEM_PG__0 1463#define VGA__MEM_PG 0464#define VGA__MEM_PG__0 1465#define DC__FMT_MEM_PG 0466#define DC__FMT_MEM_PG__0 1467#define FMT__MEM_PG 0468#define FMT__MEM_PG__0 1469#define DC__ODM_MEM_PG 0470#define DC__ODM_MEM_PG__0 1471#define ODM__MEM_PG 0472#define ODM__MEM_PG__0 1473#define DC__DSI_MEM_PG 0474#define DC__DSI_MEM_PG__0 1475#define DSI__MEM_PG 0476#define DSI__MEM_PG__0 1477#define DC__AZ_MEM_PG 1478#define DC__AZ_MEM_PG__1 1479#define AZ__MEM_PG 1480#define AZ__MEM_PG__1 1481#define DC__WBSCL_MEM1P1024X64QS_MEM_PG 1482#define DC__WBSCL_MEM1P1024X64QS_MEM_PG__1 1483#define WBSCL_MEM1P1024X64QS__MEM_PG 1484#define WBSCL_MEM1P1024X64QS__MEM_PG__1 1485#define DC__WBSCL_MEM1P528X64QS_MEM_PG 1486#define DC__WBSCL_MEM1P528X64QS_MEM_PG__1 1487#define WBSCL_MEM1P528X64QS__MEM_PG 1488#define WBSCL_MEM1P528X64QS__MEM_PG__1 1489#define DC__DMCU_MEM1P1024X32BQS_MEM_PG 1490#define DC__DMCU_MEM1P1024X32BQS_MEM_PG__1 1491#define DMCU_MEM1P1024X32BQS__MEM_PG 1492#define DMCU_MEM1P1024X32BQS__MEM_PG__1 1493#define DC__HUBBUB_SDP_TAG_INT_MEM_PG 0494#define DC__HUBBUB_SDP_TAG_INT_MEM_PG__0 1495#define HUBBUB_SDP_TAG_INT__MEM_PG 0496#define HUBBUB_SDP_TAG_INT__MEM_PG__0 1497#define DC__HUBBUB_SDP_TAG_EXT_MEM_PG 0498#define DC__HUBBUB_SDP_TAG_EXT_MEM_PG__0 1499#define HUBBUB_SDP_TAG_EXT__MEM_PG 0500#define HUBBUB_SDP_TAG_EXT__MEM_PG__0 1501#define DC__HUBBUB_RET_ZERO_MEM_PG 0502#define DC__HUBBUB_RET_ZERO_MEM_PG__0 1503#define HUBBUB_RET_ZERO__MEM_PG 0504#define HUBBUB_RET_ZERO__MEM_PG__0 1505#define DC__HUBBUB_RET_ROB_MEM_PG 0506#define DC__HUBBUB_RET_ROB_MEM_PG__0 1507#define HUBBUB_RET_ROB__MEM_PG 0508#define HUBBUB_RET_ROB__MEM_PG__0 1509#define DC__HUBPRET_CUR_ROB_MEM_PG 0510#define DC__HUBPRET_CUR_ROB_MEM_PG__0 1511#define HUBPRET_CUR_ROB__MEM_PG 0512#define HUBPRET_CUR_ROB__MEM_PG__0 1513#define DC__HUBPRET_CUR_CDC_MEM_PG 0514#define DC__HUBPRET_CUR_CDC_MEM_PG__0 1515#define HUBPRET_CUR_CDC__MEM_PG 0516#define HUBPRET_CUR_CDC__MEM_PG__0 1517#define DC__HUBPREQ_MPTE_MEM_PG 0518#define DC__HUBPREQ_MPTE_MEM_PG__0 1519#define HUBPREQ_MPTE__MEM_PG 0520#define HUBPREQ_MPTE__MEM_PG__0 1521#define DC__HUBPREQ_META_MEM_PG 0522#define DC__HUBPREQ_META_MEM_PG__0 1523#define HUBPREQ_META__MEM_PG 0524#define HUBPREQ_META__MEM_PG__0 1525#define DC__HUBPREQ_DPTE_MEM_PG 0526#define DC__HUBPREQ_DPTE_MEM_PG__0 1527#define HUBPREQ_DPTE__MEM_PG 0528#define HUBPREQ_DPTE__MEM_PG__0 1529#define DC__HUBPRET_DET_MEM_PG 0530#define DC__HUBPRET_DET_MEM_PG__0 1531#define HUBPRET_DET__MEM_PG 0532#define HUBPRET_DET__MEM_PG__0 1533#define DC__HUBPRET_PIX_CDC_MEM_PG 0534#define DC__HUBPRET_PIX_CDC_MEM_PG__0 1535#define HUBPRET_PIX_CDC__MEM_PG 0536#define HUBPRET_PIX_CDC__MEM_PG__0 1537#define DC__TOP_BLKS__DCCG 1538#define DC__TOP_BLKS__DCHUBBUB 1539#define DC__TOP_BLKS__DCHUBP 1540#define DC__TOP_BLKS__HDA 1541#define DC__TOP_BLKS__DIO 1542#define DC__TOP_BLKS__DCIO 1543#define DC__TOP_BLKS__DMU 1544#define DC__TOP_BLKS__DPP 1545#define DC__TOP_BLKS__MPC 1546#define DC__TOP_BLKS__OPP 1547#define DC__TOP_BLKS__OPTC 1548#define DC__TOP_BLKS__MMHUBBUB 1549#define DC__TOP_BLKS__WB 1550#define DC__TOP_BLKS__MAX 13551#define DC__TOP_BLKS__MAX__13 1552#define DC__DCHUBP_DPP_SF_PIXEL_CREDITS 9553#define DC__DCHUBP_DPP_SF_PIXEL_CREDITS__9 1554#define DC__DPP_MPC_SF_PIXEL_CREDITS 9555#define DC__DPP_MPC_SF_PIXEL_CREDITS__9 1556#define DC__MPC_OPP_SF_PIXEL_CREDITS 8557#define DC__MPC_OPP_SF_PIXEL_CREDITS__8 1558#define DC__OPP_OPTC_SF_PIXEL_CREDITS 8559#define DC__OPP_OPTC_SF_PIXEL_CREDITS__8 1560#define DC__SFR_SFT_ROUND_TRIP_DELAY 5561#define DC__SFR_SFT_ROUND_TRIP_DELAY__5 1562#define DC__REPEATER_PROJECT_MAX 8563#define DC__REPEATER_PROJECT_MAX__8 1564#define DC__SURFACE_422_CAPABLE 0565#define DC__SURFACE_422_CAPABLE__0 1566#endif567