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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright 2021 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26#include "core_types.h"27 28#ifndef __DCN20_FPU_H__29#define __DCN20_FPU_H__30 31void dcn20_populate_dml_writeback_from_context(struct dc *dc,32 struct resource_context *res_ctx,33 display_e2e_pipe_params_st *pipes);34 35void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params,36 struct dc_state *context,37 display_e2e_pipe_params_st *pipes,38 int pipe_cnt, int i);39void dcn20_calculate_dlg_params(struct dc *dc,40 struct dc_state *context,41 display_e2e_pipe_params_st *pipes,42 int pipe_cnt,43 int vlevel);44int dcn20_populate_dml_pipes_from_context(struct dc *dc,45 struct dc_state *context,46 display_e2e_pipe_params_st *pipes,47 bool fast_validate);48void dcn20_calculate_wm(struct dc *dc,49 struct dc_state *context,50 display_e2e_pipe_params_st *pipes,51 int *out_pipe_cnt,52 int *pipe_split_from,53 int vlevel,54 bool fast_validate);55void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb,56 struct pp_smu_nv_clock_table max_clocks);57void dcn20_update_bounding_box(struct dc *dc,58 struct _vcs_dpi_soc_bounding_box_st *bb,59 struct pp_smu_nv_clock_table *max_clocks,60 unsigned int *uclk_states,61 unsigned int num_states);62void dcn20_patch_bounding_box(struct dc *dc,63 struct _vcs_dpi_soc_bounding_box_st *bb);64bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,65 bool fast_validate, display_e2e_pipe_params_st *pipes);66void dcn20_fpu_set_wm_ranges(int i,67 struct pp_smu_wm_range_sets *ranges,68 struct _vcs_dpi_soc_bounding_box_st *loaded_bb);69void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,70 int vlevel,71 int max_mpc_comb,72 int pipe_idx,73 bool is_validating_bw);74 75int dcn21_populate_dml_pipes_from_context(struct dc *dc,76 struct dc_state *context,77 display_e2e_pipe_params_st *pipes,78 bool fast_validate);79bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, bool80 fast_validate, display_e2e_pipe_params_st *pipes);81void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);82 83void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);84 85void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,86 struct resource_context *res_ctx,87 display_e2e_pipe_params_st *pipes);88 89#endif /* __DCN20_FPU_H__ */90