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1/*2 * Copyright 2020-2021 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25#include "resource.h"26#include "clk_mgr.h"27#include "reg_helper.h"28#include "dcn_calc_math.h"29#include "dcn20/dcn20_resource.h"30#include "dcn30/dcn30_resource.h"31 32#include "clk_mgr/dcn30/dcn30_smu11_driver_if.h"33#include "display_mode_vba_30.h"34#include "dcn30_fpu.h"35 36#define REG(reg)\37 optc1->tg_regs->reg38 39#define CTX \40 optc1->base.ctx41 42#undef FN43#define FN(reg_name, field_name) \44 optc1->tg_shift->field_name, optc1->tg_mask->field_name45 46 47struct _vcs_dpi_ip_params_st dcn3_0_ip = {48 .use_min_dcfclk = 0,49 .clamp_min_dcfclk = 0,50 .odm_capable = 1,51 .gpuvm_enable = 0,52 .hostvm_enable = 0,53 .gpuvm_max_page_table_levels = 4,54 .hostvm_max_page_table_levels = 4,55 .hostvm_cached_page_table_levels = 0,56 .pte_group_size_bytes = 2048,57 .num_dsc = 6,58 .rob_buffer_size_kbytes = 184,59 .det_buffer_size_kbytes = 184,60 .dpte_buffer_size_in_pte_reqs_luma = 84,61 .pde_proc_buffer_size_64k_reqs = 48,62 .dpp_output_buffer_pixels = 2560,63 .opp_output_buffer_lines = 1,64 .pixel_chunk_size_kbytes = 8,65 .pte_enable = 1,66 .max_page_table_levels = 2,67 .pte_chunk_size_kbytes = 2, // ?68 .meta_chunk_size_kbytes = 2,69 .writeback_chunk_size_kbytes = 8,70 .line_buffer_size_bits = 789504,71 .is_line_buffer_bpp_fixed = 0, // ?72 .line_buffer_fixed_bpp = 0, // ?73 .dcc_supported = true,74 .writeback_interface_buffer_size_kbytes = 90,75 .writeback_line_buffer_buffer_size = 0,76 .max_line_buffer_lines = 12,77 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 65664078 .writeback_chroma_buffer_size_kbytes = 8,79 .writeback_chroma_line_buffer_width_pixels = 4,80 .writeback_max_hscl_ratio = 1,81 .writeback_max_vscl_ratio = 1,82 .writeback_min_hscl_ratio = 1,83 .writeback_min_vscl_ratio = 1,84 .writeback_max_hscl_taps = 1,85 .writeback_max_vscl_taps = 1,86 .writeback_line_buffer_luma_buffer_size = 0,87 .writeback_line_buffer_chroma_buffer_size = 14643,88 .cursor_buffer_size = 8,89 .cursor_chunk_size = 2,90 .max_num_otg = 6,91 .max_num_dpp = 6,92 .max_num_wb = 1,93 .max_dchub_pscl_bw_pix_per_clk = 4,94 .max_pscl_lb_bw_pix_per_clk = 2,95 .max_lb_vscl_bw_pix_per_clk = 4,96 .max_vscl_hscl_bw_pix_per_clk = 4,97 .max_hscl_ratio = 6,98 .max_vscl_ratio = 6,99 .hscl_mults = 4,100 .vscl_mults = 4,101 .max_hscl_taps = 8,102 .max_vscl_taps = 8,103 .dispclk_ramp_margin_percent = 1,104 .underscan_factor = 1.11,105 .min_vblank_lines = 32,106 .dppclk_delay_subtotal = 46,107 .dynamic_metadata_vm_enabled = true,108 .dppclk_delay_scl_lb_only = 16,109 .dppclk_delay_scl = 50,110 .dppclk_delay_cnvc_formatter = 27,111 .dppclk_delay_cnvc_cursor = 6,112 .dispclk_delay_subtotal = 119,113 .dcfclk_cstate_latency = 5.2, // SRExitTime114 .max_inter_dcn_tile_repeaters = 8,115 .max_num_hdmi_frl_outputs = 1,116 .odm_combine_4to1_supported = true,117 118 .xfc_supported = false,119 .xfc_fill_bw_overhead_percent = 10.0,120 .xfc_fill_constant_bytes = 0,121 .gfx7_compat_tiling_supported = 0,122 .number_of_cursors = 1,123};124 125struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {126 .clock_limits = {127 {128 .state = 0,129 .dispclk_mhz = 562.0,130 .dppclk_mhz = 300.0,131 .phyclk_mhz = 300.0,132 .phyclk_d18_mhz = 667.0,133 .dscclk_mhz = 405.6,134 },135 },136 137 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */138 .num_states = 1,139 .sr_exit_time_us = 15.5,140 .sr_enter_plus_exit_time_us = 20,141 .urgent_latency_us = 4.0,142 .urgent_latency_pixel_data_only_us = 4.0,143 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,144 .urgent_latency_vm_data_only_us = 4.0,145 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,146 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,147 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,148 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,149 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,150 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,151 .max_avg_sdp_bw_use_normal_percent = 60.0,152 .max_avg_dram_bw_use_normal_percent = 40.0,153 .writeback_latency_us = 12.0,154 .max_request_size_bytes = 256,155 .fabric_datapath_to_dcn_data_return_bytes = 64,156 .dcn_downspread_percent = 0.5,157 .downspread_percent = 0.38,158 .dram_page_open_time_ns = 50.0,159 .dram_rw_turnaround_time_ns = 17.5,160 .dram_return_buffer_per_channel_bytes = 8192,161 .round_trip_ping_latency_dcfclk_cycles = 191,162 .urgent_out_of_order_return_per_channel_bytes = 4096,163 .channel_interleave_bytes = 256,164 .num_banks = 8,165 .gpuvm_min_page_size_bytes = 4096,166 .hostvm_min_page_size_bytes = 4096,167 .dram_clock_change_latency_us = 404,168 .dummy_pstate_latency_us = 5,169 .writeback_dram_clock_change_latency_us = 23.0,170 .return_bus_width_bytes = 64,171 .dispclk_dppclk_vco_speed_mhz = 3650,172 .xfc_bus_transport_time_us = 20, // ?173 .xfc_xbuf_latency_tolerance_us = 4, // ?174 .use_urgent_burst_bw = 1, // ?175 .do_urgent_latency_adjustment = true,176 .urgent_latency_adjustment_fabric_clock_component_us = 1.0,177 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,178};179 180 181void optc3_fpu_set_vrr_m_const(struct timing_generator *optc,182 double vtotal_avg)183{184 struct optc *optc1 = DCN10TG_FROM_TG(optc);185 double vtotal_min, vtotal_max;186 double ratio, modulo, phase;187 uint32_t vblank_start;188 uint32_t v_total_mask_value = 0;189 190 dc_assert_fp_enabled();191 192 /* Compute VTOTAL_MIN and VTOTAL_MAX, so that193 * VOTAL_MAX - VTOTAL_MIN = 1194 */195 v_total_mask_value = 16;196 vtotal_min = dcn_bw_floor(vtotal_avg);197 vtotal_max = dcn_bw_ceil(vtotal_avg);198 199 /* Check that bottom VBLANK is at least 2 lines tall when running with200 * VTOTAL_MIN. Note that VTOTAL registers are defined as 'total number201 * of lines in a frame - 1'.202 */203 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START,204 &vblank_start);205 ASSERT(vtotal_min >= vblank_start + 1);206 207 /* Special case where the average frame rate can be achieved208 * without using the DTO209 */210 if (vtotal_min == vtotal_max) {211 REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, (uint32_t)vtotal_min);212 213 optc->funcs->set_vtotal_min_max(optc, 0, 0);214 REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, 0);215 REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, 0);216 REG_UPDATE_3(OTG_V_TOTAL_CONTROL,217 OTG_V_TOTAL_MIN_SEL, 0,218 OTG_V_TOTAL_MAX_SEL, 0,219 OTG_SET_V_TOTAL_MIN_MASK_EN, 0);220 return;221 }222 223 ratio = vtotal_max - vtotal_avg;224 modulo = 65536.0 * 65536.0 - 1.0; /* 2^32 - 1 */225 phase = ratio * modulo;226 227 /* Special cases where the DTO phase gets rounded to 0 or228 * to DTO modulo229 */230 if (phase <= 0 || phase >= modulo) {231 REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL,232 phase <= 0 ?233 (uint32_t)vtotal_max : (uint32_t)vtotal_min);234 REG_SET(OTG_V_TOTAL_MIN, 0, OTG_V_TOTAL_MIN, 0);235 REG_SET(OTG_V_TOTAL_MAX, 0, OTG_V_TOTAL_MAX, 0);236 REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, 0);237 REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, 0);238 REG_UPDATE_3(OTG_V_TOTAL_CONTROL,239 OTG_V_TOTAL_MIN_SEL, 0,240 OTG_V_TOTAL_MAX_SEL, 0,241 OTG_SET_V_TOTAL_MIN_MASK_EN, 0);242 return;243 }244 REG_UPDATE_6(OTG_V_TOTAL_CONTROL,245 OTG_V_TOTAL_MIN_SEL, 1,246 OTG_V_TOTAL_MAX_SEL, 1,247 OTG_SET_V_TOTAL_MIN_MASK_EN, 1,248 OTG_SET_V_TOTAL_MIN_MASK, v_total_mask_value,249 OTG_VTOTAL_MID_REPLACING_MIN_EN, 0,250 OTG_VTOTAL_MID_REPLACING_MAX_EN, 0);251 REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, (uint32_t)vtotal_min);252 optc->funcs->set_vtotal_min_max(optc, vtotal_min, vtotal_max);253 REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, (uint32_t)phase);254 REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, (uint32_t)modulo);255}256 257void dcn30_fpu_populate_dml_writeback_from_context(258 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)259{260 int pipe_cnt, i, j;261 double max_calc_writeback_dispclk;262 double writeback_dispclk;263 struct writeback_st dout_wb = {0};264 265 dc_assert_fp_enabled();266 267 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {268 struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;269 270 if (!stream)271 continue;272 max_calc_writeback_dispclk = 0;273 274 /* Set writeback information */275 pipes[pipe_cnt].dout.wb_enable = 0;276 pipes[pipe_cnt].dout.num_active_wb = 0;277 for (j = 0; j < stream->num_wb_info; j++) {278 struct dc_writeback_info *wb_info = &stream->writeback_info[j];279 280 if (wb_info->wb_enabled && wb_info->writeback_source_plane &&281 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {282 pipes[pipe_cnt].dout.wb_enable = 1;283 pipes[pipe_cnt].dout.num_active_wb++;284 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ?285 wb_info->dwb_params.cnv_params.crop_height :286 wb_info->dwb_params.cnv_params.src_height;287 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ?288 wb_info->dwb_params.cnv_params.crop_width :289 wb_info->dwb_params.cnv_params.src_width;290 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;291 dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;292 293 /* For IP that doesn't support WB scaling, set h/v taps to 1 to avoid DML validation failure */294 if (dc->dml.ip.writeback_max_hscl_taps > 1) {295 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;296 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;297 } else {298 dout_wb.wb_htaps_luma = 1;299 dout_wb.wb_vtaps_luma = 1;300 }301 dout_wb.wb_htaps_chroma = 0;302 dout_wb.wb_vtaps_chroma = 0;303 dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?304 (double)wb_info->dwb_params.cnv_params.crop_width /305 (double)wb_info->dwb_params.dest_width :306 (double)wb_info->dwb_params.cnv_params.src_width /307 (double)wb_info->dwb_params.dest_width;308 dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ?309 (double)wb_info->dwb_params.cnv_params.crop_height /310 (double)wb_info->dwb_params.dest_height :311 (double)wb_info->dwb_params.cnv_params.src_height /312 (double)wb_info->dwb_params.dest_height;313 if (wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||314 wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)315 dout_wb.wb_pixel_format = dm_444_64;316 else317 dout_wb.wb_pixel_format = dm_444_32;318 319 /* Workaround for cases where multiple writebacks are connected to same plane320 * In which case, need to compute worst case and set the associated writeback parameters321 * This workaround is necessary due to DML computation assuming only 1 set of writeback322 * parameters per pipe323 */324 writeback_dispclk = dml30_CalculateWriteBackDISPCLK(325 dout_wb.wb_pixel_format,326 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,327 dout_wb.wb_hratio,328 dout_wb.wb_vratio,329 dout_wb.wb_htaps_luma,330 dout_wb.wb_vtaps_luma,331 dout_wb.wb_src_width,332 dout_wb.wb_dst_width,333 pipes[pipe_cnt].pipe.dest.htotal,334 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size);335 336 if (writeback_dispclk > max_calc_writeback_dispclk) {337 max_calc_writeback_dispclk = writeback_dispclk;338 pipes[pipe_cnt].dout.wb = dout_wb;339 }340 }341 }342 343 pipe_cnt++;344 }345}346 347void dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params,348 struct display_mode_lib *dml,349 display_e2e_pipe_params_st *pipes,350 int pipe_cnt,351 int cur_pipe)352{353 int i;354 355 dc_assert_fp_enabled();356 357 for (i = 0; i < ARRAY_SIZE(wb_arb_params->cli_watermark); i++) {358 wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000;359 wb_arb_params->pstate_watermark[i] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;360 }361 362 wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */363}364 365void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)366{367 368 dc_assert_fp_enabled();369 370 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {371 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||372 context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0)373 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;374 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;375 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;376 }377}378 379void dcn30_fpu_calculate_wm_and_dlg(380 struct dc *dc, struct dc_state *context,381 display_e2e_pipe_params_st *pipes,382 int pipe_cnt,383 int vlevel)384{385 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;386 int i, pipe_idx;387 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb];388 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;389 unsigned int dummy_latency_index = 0;390 struct dc_stream_status *stream_status = NULL;391 392 dc_assert_fp_enabled();393 394 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;395 for (i = 0; i < context->stream_count; i++) {396 stream_status = NULL;397 if (context->streams[i])398 stream_status = dc_state_get_stream_status(context, context->streams[i]);399 if (stream_status)400 stream_status->fpo_in_use = false;401 }402 403 if (!pstate_en) {404 /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */405 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching =406 dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);407 408 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {409 dummy_latency_index = dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(dc,410 context, pipes, pipe_cnt, vlevel);411 412 /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch413 * we reinstate the original dram_clock_change_latency_us on the context414 * and all variables that may have changed up to this point, except the415 * newly found dummy_latency_index416 */417 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;418 dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false, true);419 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;420 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];421 pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;422 }423 }424 425 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)426 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;427 428 pipes[0].clks_cfg.voltage = vlevel;429 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;430 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;431 432 /* Set B:433 * DCFCLK: 1GHz or min required above 1GHz434 * FCLK/UCLK: Max435 */436 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {437 if (vlevel == 0) {438 pipes[0].clks_cfg.voltage = 1;439 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;440 }441 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;442 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;443 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;444 }445 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;446 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;447 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;448 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;449 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;450 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;451 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;452 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;453 454 pipes[0].clks_cfg.voltage = vlevel;455 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;456 457 /* Set D:458 * DCFCLK: Min Required459 * FCLK(proportional to UCLK): 1GHz or Max460 * MALL stutter, sr_enter_exit = 4, sr_exit = 2us461 */462 /*463 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {464 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;465 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;466 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;467 }468 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;469 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;470 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;471 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;472 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;473 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;474 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;475 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;476 */477 478 /* Set C:479 * DCFCLK: Min Required480 * FCLK(proportional to UCLK): 1GHz or Max481 * pstate latency overridden to 5us482 */483 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {484 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;485 unsigned int min_dram_speed_mts_margin = 160;486 487 context->bw_ctx.dml.soc.dram_clock_change_latency_us =488 dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;489 490 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==491 dm_dram_clock_change_unsupported) {492 int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries - 1;493 494 min_dram_speed_mts =495 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;496 }497 498 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {499 /* find largest table entry that is lower than dram speed,500 * but lower than DPM0 still uses DPM0501 */502 for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--)503 if (min_dram_speed_mts + min_dram_speed_mts_margin >504 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)505 break;506 }507 508 context->bw_ctx.dml.soc.dram_clock_change_latency_us =509 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;510 511 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;512 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;513 }514 515 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;516 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;517 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;518 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;519 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;520 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;521 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;522 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;523 524 if (!pstate_en) {525 /* The only difference between A and C is p-state latency, if p-state is not supported we want to526 * calculate DLG based on dummy p-state latency, and max out the set A p-state watermark527 */528 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;529 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;530 } else {531 /* Set A:532 * DCFCLK: Min Required533 * FCLK(proportional to UCLK): 1GHz or Max534 *535 * Set A calculated last so that following calculations are based on Set A536 */537 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);538 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;539 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;540 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;541 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;542 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;543 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;544 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;545 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;546 }547 548 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;549 550 /* Make set D = set A until set D is enabled */551 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;552 553 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {554 if (!context->res_ctx.pipe_ctx[i].stream)555 continue;556 557 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);558 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);559 560 if (dc->config.forced_clocks) {561 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;562 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;563 }564 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)565 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;566 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)567 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;568 569 pipe_idx++;570 }571 572 // WA: restrict FPO to use first non-strobe mode (NV24 BW issue)573 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching &&574 dc->dml.soc.num_chans <= 4 &&575 context->bw_ctx.dml.vba.DRAMSpeed <= 1700 &&576 context->bw_ctx.dml.vba.DRAMSpeed >= 1500) {577 578 for (i = 0; i < dc->dml.soc.num_states; i++) {579 if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) {580 context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts;581 break;582 }583 }584 }585 586 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);587 588 if (!pstate_en)589 /* Restore full p-state latency */590 context->bw_ctx.dml.soc.dram_clock_change_latency_us =591 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;592 593 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)594 dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(dc, context);595}596 597void dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc)598{599 dc_assert_fp_enabled();600 601 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)602 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;603}604 605void dcn30_fpu_update_max_clk(struct dc_bounding_box_max_clk *dcn30_bb_max_clk)606{607 dc_assert_fp_enabled();608 609 if (!dcn30_bb_max_clk->max_dcfclk_mhz)610 dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz;611 if (!dcn30_bb_max_clk->max_dispclk_mhz)612 dcn30_bb_max_clk->max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz;613 if (!dcn30_bb_max_clk->max_dppclk_mhz)614 dcn30_bb_max_clk->max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz;615 if (!dcn30_bb_max_clk->max_phyclk_mhz)616 dcn30_bb_max_clk->max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz;617}618 619void dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,620 unsigned int *optimal_dcfclk,621 unsigned int *optimal_fclk)622{623 double bw_from_dram, bw_from_dram1, bw_from_dram2;624 625 dc_assert_fp_enabled();626 627 bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans *628 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100);629 bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans *630 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100);631 632 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;633 634 if (optimal_fclk)635 *optimal_fclk = bw_from_dram /636 (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));637 638 if (optimal_dcfclk)639 *optimal_dcfclk = bw_from_dram /640 (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));641}642 643void dcn30_fpu_update_bw_bounding_box(struct dc *dc,644 struct clk_bw_params *bw_params,645 struct dc_bounding_box_max_clk *dcn30_bb_max_clk,646 unsigned int *dcfclk_mhz,647 unsigned int *dram_speed_mts)648{649 unsigned int i;650 651 dc_assert_fp_enabled();652 653 dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;654 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;655 656 for (i = 0; i < dcn3_0_soc.num_states; i++) {657 dcn3_0_soc.clock_limits[i].state = i;658 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];659 dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];660 dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];661 662 /* Fill all states with max values of all other clocks */663 dcn3_0_soc.clock_limits[i].dispclk_mhz = dcn30_bb_max_clk->max_dispclk_mhz;664 dcn3_0_soc.clock_limits[i].dppclk_mhz = dcn30_bb_max_clk->max_dppclk_mhz;665 dcn3_0_soc.clock_limits[i].phyclk_mhz = dcn30_bb_max_clk->max_phyclk_mhz;666 dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;667 /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */668 /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */669 dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz;670 dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz;671 dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz;672 }673 /* re-init DML with updated bb */674 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);675 if (dc->current_state)676 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);677 678}679 680/**681 * dcn30_find_dummy_latency_index_for_fw_based_mclk_switch() - Finds682 * dummy_latency_index when MCLK switching using firmware based vblank stretch683 * is enabled. This function will iterate through the table of dummy pstate684 * latencies until the lowest value that allows685 * dm_allow_self_refresh_and_mclk_switch to happen is found686 *687 * @dc: Current DC state688 * @context: new dc state689 * @pipes: DML pipe params690 * @pipe_cnt: number of DML pipes691 * @vlevel: Voltage level calculated by DML692 *693 * Return: lowest dummy_latency_index value694 */695int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,696 struct dc_state *context,697 display_e2e_pipe_params_st *pipes,698 int pipe_cnt,699 int vlevel)700{701 const int max_latency_table_entries = 4;702 int dummy_latency_index = 0;703 704 dc_assert_fp_enabled();705 706 while (dummy_latency_index < max_latency_table_entries) {707 context->bw_ctx.dml.soc.dram_clock_change_latency_us =708 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;709 dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false, true);710 711 if (context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank ==712 dm_allow_self_refresh_and_mclk_switch)713 break;714 715 dummy_latency_index++;716 }717 718 if (dummy_latency_index == max_latency_table_entries) {719 ASSERT(dummy_latency_index != max_latency_table_entries);720 /* If the execution gets here, it means dummy p_states are721 * not possible. This should never happen and would mean722 * something is severely wrong.723 * Here we reset dummy_latency_index to 3, because it is724 * better to have underflows than system crashes.725 */726 dummy_latency_index = 3;727 }728 729 return dummy_latency_index;730}731 732void dcn3_fpu_build_wm_range_table(struct clk_mgr *base)733{734 /* defaults */735 double pstate_latency_us = base->ctx->dc->dml.soc.dram_clock_change_latency_us;736 double sr_exit_time_us = base->ctx->dc->dml.soc.sr_exit_time_us;737 double sr_enter_plus_exit_time_us = base->ctx->dc->dml.soc.sr_enter_plus_exit_time_us;738 uint16_t min_uclk_mhz = base->bw_params->clk_table.entries[0].memclk_mhz;739 740 dc_assert_fp_enabled();741 742 /* Set A - Normal - default values*/743 base->bw_params->wm_table.nv_entries[WM_A].valid = true;744 base->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;745 base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;746 base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;747 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;748 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0;749 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;750 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;751 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;752 753 /* Set B - Performance - higher minimum clocks */754// base->bw_params->wm_table.nv_entries[WM_B].valid = true;755// base->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;756// base->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;757// base->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;758// base->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;759// base->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = TUNED VALUE;760// base->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;761// base->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = TUNED VALUE;762// base->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;763 764 /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */765 base->bw_params->wm_table.nv_entries[WM_C].valid = true;766 base->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 0;767 base->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;768 base->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;769 base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;770 base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0;771 base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;772 base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;773 base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;774 base->bw_params->dummy_pstate_table[0].dram_speed_mts = 1600;775 base->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;776 base->bw_params->dummy_pstate_table[1].dram_speed_mts = 8000;777 base->bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;778 base->bw_params->dummy_pstate_table[2].dram_speed_mts = 10000;779 base->bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;780 base->bw_params->dummy_pstate_table[3].dram_speed_mts = 16000;781 base->bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;782 783 /* Set D - MALL - SR enter and exit times adjusted for MALL */784 base->bw_params->wm_table.nv_entries[WM_D].valid = true;785 base->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us;786 base->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2;787 base->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4;788 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;789 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0;790 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;791 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;792 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;793}794 795void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip)796{797 dc_assert_fp_enabled();798 799 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {800 struct bp_soc_bb_info bb_info = {0};801 802 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {803 if (bb_info.dram_clock_change_latency_100ns > 0)804 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;805 806 if (bb_info.dram_sr_enter_exit_latency_100ns > 0)807 dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;808 809 if (bb_info.dram_sr_exit_latency_100ns > 0)810 dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;811 }812 }813}814