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1/*2 * Copyright 2020-2021 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: AMD23 *24 */25 26#ifndef __DCN30_FPU_H__27#define __DCN30_FPU_H__28 29#include "core_types.h"30#include "dcn20/dcn20_optc.h"31 32void optc3_fpu_set_vrr_m_const(struct timing_generator *optc,33 double vtotal_avg);34 35void dcn30_fpu_populate_dml_writeback_from_context(36 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);37 38void dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params,39 struct display_mode_lib *dml,40 display_e2e_pipe_params_st *pipes,41 int pipe_cnt,42 int cur_pipe);43 44void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);45 46void dcn30_fpu_calculate_wm_and_dlg(47 struct dc *dc, struct dc_state *context,48 display_e2e_pipe_params_st *pipes,49 int pipe_cnt,50 int vlevel);51 52void dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc);53 54void dcn30_fpu_update_max_clk(struct dc_bounding_box_max_clk *dcn30_bb_max_clk);55 56void dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,57 unsigned int *optimal_dcfclk,58 unsigned int *optimal_fclk);59 60void dcn30_fpu_update_bw_bounding_box(struct dc *dc,61 struct clk_bw_params *bw_params,62 struct dc_bounding_box_max_clk *dcn30_bb_max_clk,63 unsigned int *dcfclk_mhz,64 unsigned int *dram_speed_mts);65 66int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,67 struct dc_state *context,68 display_e2e_pipe_params_st *pipes,69 int pipe_cnt,70 int vlevel);71 72void dcn3_fpu_build_wm_range_table(struct clk_mgr *base);73 74void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip);75 76#endif /* __DCN30_FPU_H__*/77