81 lines · c
1/* SPDX-License-Identifier: MIT */2/*3 * Copyright 2022 Advanced Micro Devices, Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 *23 * Authors: AMD24 *25 */26 27#ifndef __DCN32_FPU_H__28#define __DCN32_FPU_H__29 30#include "clk_mgr_internal.h"31 32void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr);33 34void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,35 struct dc_state *context,36 display_e2e_pipe_params_st *pipes,37 int pipe_cnt);38 39void dcn32_set_phantom_stream_timing(struct dc *dc,40 struct dc_state *context,41 struct pipe_ctx *ref_pipe,42 struct dc_stream_state *phantom_stream,43 display_e2e_pipe_params_st *pipes,44 unsigned int pipe_cnt,45 unsigned int dc_pipe_idx);46 47bool dcn32_internal_validate_bw(struct dc *dc,48 struct dc_state *context,49 display_e2e_pipe_params_st *pipes,50 int *pipe_cnt_out,51 int *vlevel_out,52 bool fast_validate);53 54void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,55 display_e2e_pipe_params_st *pipes,56 int pipe_cnt,57 int vlevel);58 59void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);60 61int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,62 struct dc_state *context,63 display_e2e_pipe_params_st *pipes,64 int pipe_cnt,65 int vlevel);66 67void dcn32_patch_dpm_table(struct clk_bw_params *bw_params);68 69void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,70 int pipe_cnt);71 72void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream);73 74bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req);75 76void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context);77 78void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb);79 80#endif81